KR20080007939A - Fabrication method of nano floating gate non-volatile memory device - Google Patents

Abstract

A nano-floating gate type non-volatile memory device is provided to obtain high capacitance and to manufacture a high-speed non-volatile memory device by using a metal nano-particle layer. A semiconductor substrate including an SOI substrate(11), and an insulating layer(12) and an upper silicon layer(13) stacked on the SOI substrate is prepared. The upper silicon layer is patterned and a first tunnel barrier insulating layer(14) is stacked on the exposed insulating layer and the upper silicon layer. A second tunnel barrier insulating layer(15) is stacked on the first tunnel barrier insulating layer. A metal and metal oxide nano-particles layer(16) is deposited on the second tunnel barrier insulating layer to form a nano-quantum dot. A nano-floating gate is formed by depositing a first and second control insulating layers(17,18) on the nano-quantum dot. A source/drain channel region(19) is formed by implanting ions into the exposed upper silicon layer. A silicon insulating layer(20) is formed and etched. A metal electrode(21) is formed.

Description

Fabrication method of nano floating gate non-volatile memory device

1 to 11 are manufacturing steps for explaining a method of manufacturing a nano floating gate type nonvolatile memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11: SOI substrate 12: insulating layer

13: upper silicon layer 14: first tunnel barrier insulating film

15 second tunnel barrier insulating film 16: metal and metal oxide nanoparticle layer

17: first control insulating film 18: second control insulating film

19 source and drain channel 20 silicon insulating film

21: metal electrode

The present invention relates to a method for manufacturing a nano-floating gate type nonvolatile memory device, and more particularly, asymmetric tunnel barriers for metal and metal oxide nanoparticle layers or metal oxide nanoparticle layers chemically formed in polymer thin films formed by physical vapor deposition. The present invention relates to a method for manufacturing a nano floating gate type nonvolatile memory device which can be manufactured between an insulating film and a control insulating film.

In general, nonvolatile memory technology has the advantages of both erasable-programmable read-only memory (EPROM) and electrically erasable-programmable read-only memory (EPEROM), as well as both DRAM and read only memory (ROM). Memory.

In future, non-volatile memory needs to increase storage capacity and improve performance. Non-volatile memory devices fabricated by using a conventional polysilicon floating gate as a storage electrode have difficulty in achieving high integration / high performance. A type of memory has been developed and researched instead. Such a memory device is called nano-floating gate memory (NFGM).

In the case of the NFGM as described above, direct tunneling is used to perform an operation of storing and erasing charges.

In order to store charge by applying a small voltage to the nanoparticle layer, a tunnel barrier insulating film is usually formed at 5 nm or less, and then the nanoparticle layer is scattered thereon.

At this time, the nanoparticle layer to be used should use a metal and a metal oxide, which forms a quantum well structure with a large difference in electron affinity, which is a property of the metal and metal oxide nanoparticles. Improve retention time.

For the low power effect of the NFGM, the thin tunnel barrier insulating film can easily store charges because it uses a direct tunnel method, but when forming the tunnel barrier insulating film, it is difficult to form a perfect insulating film with a thickness of 5 nm or less, and due to continuous stress of the insulating film due to direct tunneling. Due to this, a part of the insulating film is broken, and the well depth of the metal and metal oxide nanoparticle layer is too low, so that the information storage time is fast, but a problem in that a higher voltage is required to be executed than the information storage is required for erasing.

In other words, the thin tunnel barrier insulating film can speed up the storage of information, but the voltage applied to the deletion of the information must be higher and a high voltage must be applied to discharge the charge from the well to the channel region. It means the continuous stress is applied to the thin tunnel barrier insulating film.

Meanwhile, Korean Patent Registration No. 0585849, which is a method of manufacturing a metal oxide nanoparticle layer by a chemical method, requires charge to be stored in a metal oxide present in a polyimide to fabricate a nonvolatile memory device. As the constant value is 2.9 or less, the tunnel barrier insulating film and the control insulating film formed of the insulating film of the polyimide have a technical problem that is difficult to apply to the nonvolatile memory device.

Accordingly, the present invention is invented to solve the above problems, the metal and metal oxide nanoparticle layer prepared by physical vapor deposition and chemical reaction between the high dielectric material and the tunnel barrier insulating film and the control insulating film of silicon oxide film Forming a semiconductor substrate, forming an asymmetric tunnel barrier insulating film on the semiconductor substrate, and forming a metal and metal oxide nanoparticle layer on the asymmetric tunnel barrier insulating film to form nano quantum dots. And forming a non-symmetrical control insulating film on the nanoparticle layer to form metal and metal oxide nano floating gates.

Hereinafter, the features of the present invention for achieving the above object are as follows.

A method of manufacturing a nano floating gate nonvolatile memory device according to the present invention includes preparing a semiconductor substrate in which an insulating layer and an upper silicon layer are sequentially stacked on an SOI substrate;

Patterning the upper silicon layer and stacking a first tunnel barrier insulating film on the exposed insulating layer and the upper silicon layer;

Stacking a second tunnel barrier insulating film on the first tunnel barrier insulating film;

Forming a nano quantum dot by forming a metal and a metal oxide nanoparticle layer on the second tunnel barrier insulating layer by a physical deposition method or a chemical method using a polymer material;

Forming a nano floating gate by forming first and second control insulating layers on the nano quantum dots of the formed metal and metal oxide nanoparticle layers;

A fifth step of forming a source and a drain channel region by etching ions, leaving only the region where the gate is to be formed using a mask to form the source, drain, and gate, and then implanting ions into the exposed upper silicon film;

And forming a silicon insulating film to form electrodes of the source, drain, and gate, and etching the electrode forming portions of the source, drain, and gate to be exposed, and then forming a metal electrode.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to a method of manufacturing a nano floating gate type nonvolatile memory device by forming a gate with a metal oxide nanoparticle layer formed between a metal and a metal oxide nanoparticle layer or a polymer material between an asymmetric tunnel barrier insulating film and a control insulating film. According to the present invention, after forming an asymmetric tunnel barrier insulating film on a silicon-on-insulator (SOI) substrate made of silicon and an insulating layer, a floating gate including a nanoparticle layer is fabricated to store information and to read and erase information. A method of manufacturing a floating gate type nonvolatile memory device.

1 to 11 are manufacturing steps for explaining a method of manufacturing a nano floating gate type nonvolatile memory device according to an embodiment of the present invention.

First, an SOI substrate made of silicon and an insulating layer is provided. An insulating layer is formed on the SOI substrate 11, and an upper silicon layer 13 is formed on the SOI substrate 11.

In addition, as shown in FIG. 2, the upper silicon layer 13 may be etched to form a source, a drain, and a gate. In this case, the source, drain, and the like may be used to etch the upper silicon layer 13. An etching process is performed using a gated patterned mask.

Next, as shown in FIG. 3, the first tunnel barrier insulating layer 14 is stacked on the upper silicon layer 13 on which the etching process is completed.

At this time, the first tunnel barrier insulating film 14 is a silicon oxide (SiO ₂ ), silicon nitride (SiO _2.1 N ₁ , SiO _1.3 N ₁ ) -based dry oxidation (Physical Vapor Deposition; PVD) It is formed as.

In addition, the silicon nitride formed at this time may be formed by adjusting the mixing ratio of nitrogen in the dry oxidation method and physical vapor deposition process.

This uses the same material as the second control insulating film 18 described later.

The thickness of the first tunnel barrier insulating film 14 formed at this time is limited to 1 to 3 nm to be molded.

The thickness of the first tunnel barrier insulating layer 14 should be at least 1 nm.

That is, when the voltage is less than 1 nm, the first tunnel barrier insulating film 14 does not endure stress when the voltage is applied for charge storage, and thus the insulating film is destroyed, which may cause a leakage current.

In addition, when the thickness is formed to exceed 3 nm, there is a problem that it is difficult to implement the effect of the asymmetric tunnel barrier insulating film which is a preferred embodiment of the present invention.

4 illustrates an atomic layer of a second tunnel barrier insulating layer 14 made of a high dielectric material such as hafnium oxide (HfO ₂ ) or zirconium oxide (ZrO ₂ ) having a thickness of 5 to 7 nm on the first tunnel barrier insulating layer 14. It is formed by Atomic Layer Deposition (ALD) and physical vapor deposition.

In this case, the thicknesses of the first and second tunnel barrier insulating films 14 and 15 should be less than or equal to 8 nm in order to produce a tunnel effect, and the thickness of the second tunnel barrier insulating film 15 may be the first tunnel barrier insulating film ( The thickness shall be adjusted according to the thickness of 14).

Here, since the second tunnel barrier insulating film 15 uses a high dielectric material, the second tunnel barrier insulating film 15 exhibits very thin silicon oxide with a thickness of 5 to 7 nm.

In other words, the first tunnel barrier insulating film 14 having a thickness of 3 nm and the second tunnel barrier insulating film 15 having a thickness of 5 nm exhibit the effects of the tunnel barrier insulating film of silicon oxide having a thickness of about 4 nm.

On the other hand, the material used as the second tunnel barrier insulating film 15 is the same material as the first control insulating film 17 to be described later.

As shown in FIG. 4, the first and second tunnel barrier insulating layers 14 and 15 which are asymmetrical to each other are used as the second tunnel barrier insulating layer according to the present invention. 15).

Next, as shown in FIG. 5, the metal and metal oxide nanoparticle layers 16 are formed to form nano quantum dots.

At this time, the metal and metal oxide nanoparticle layer 16 having a particle size of 3 to 4 nm in diameter formed as described above has a density of 1 x 10 ¹² to 5 x 10 ¹² cm ^-2 and a thickness of 0.5 to 1 nm. do.

The reason for limiting the diameter of the nanoparticle layer to a size of 3 to 4 nm is that if the particle size is less than 3 nm, the nanoparticle layer cannot be manufactured by physical vapor deposition and pulse laser lamination, and the band gap of the nanoparticle layer This increases and the charge storage characteristic is significantly lowered. On the other hand, if it exceeds 4 nm, the uniformity is significantly lowered, thereby causing instability of the threshold voltage.

In addition, when the density is less than 1 x 10 ¹² cm ^-2 , the threshold voltage is too small and the amount of charge stored in the memory device is small, so that the efficiency of the memory is drastically reduced, whereas when the density exceeds 5x10 ¹² cm ^-2 , the particles Since the size of is to be small, the charge retention characteristics are reduced.

In addition, as shown in FIG. 6, first and second control insulating layers 17 and 18 are stacked on the metal and metal oxide nanoparticle layer 16 to form nano floating gates. 17, the second tunnel barrier insulating layer 15 and the second control insulating layer 18 are stacked with the same material as the first tunnel barrier insulating layer 14.

This is because both walls of the well structure of the metal and metal oxide nanoparticle layer 16 distributed between the first and second tunnel barrier insulating films 14 and 15 and the first and second control insulating films 17 and 18 are the same. This is because the energy level at which the electric charge inside the well is stored is formed at a height.

The first control insulating layer 17 is formed of atomic layer deposition (ALD) using the same high dielectric materials as hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), and the like as the second tunnel barrier insulating layer 15. And physical vapor deposition.

The thickness of the first control insulating film 17 formed at this time is 5 to 10 nm or less.

This is because when the high dielectric materials such as hafnium oxide (HfO ₂ ) and zirconium oxide (ZrO ₂ ) exceed 10 nm, the etching process by dry etching is difficult, whereas 5 nm If less, the insulating film may be destroyed or a leakage current may be generated by a voltage applied when the charge stored in the nano floating gate is removed from the first control insulating film 17.

In addition, since the second control insulating layer 18 is formed of the same material as the first tunnel barrier insulating layer 14, SiO ₂ , SiO _2.1 N ₁ , and SiO _1.3 N ₁ may be formed by physical vapor deposition (PVD). Is formed.

The thickness of the second control insulating film 18 formed at this time is 5 to 10 nm or less.

The second control insulating film 18 is intended to protect the first control insulating film 17 and to form a metal electrode thereon, so that a sufficient voltage can be applied to the first control insulating film 17. It is preferable not to exceed nm, and leakage current may occur when formed below 5 nm.

Here, the nano floating gate is formed of a metal oxide nanoparticle layer formed by a polyimide solvent N-Metyl-2-Pyrrolidone (NMP) of a polymer material and a precursor Biphenyltertracaboxylic Dianhydide-p-Phenylenediamind (BPDA-PDA).

In addition, the second control insulating film 18 is formed of the same material as the first tunnel barrier insulating film 14, and is formed of SiO ₂ , SiO _2.1 N ₁ , SiO _1.3 N _1, and hafnium oxide (HfO ₂ ). .

This is to reduce the complexity of the device process, and to prevent the charge stored in the nano floating gate from moving toward the gate due to the difference in the band gap.

On the other hand, the second tunnel barrier insulating film 15, the metal and metal oxide nanoparticle layer 16, and the first control insulating film 17 stacked on the first tunnel barrier insulating film 14 are formed simultaneously due to the characteristics of the manufacturing method.

As described above, the first tunnel barrier insulating layer 14 may be formed of silicon oxide, silicon nitride, and a high dielectric material, and the second control insulating layer 18 may form the first tunnel barrier insulating layer 14. It is formed of the same material as when.

Meanwhile, FIG. 7 is a view illustrating etching the remaining regions leaving only the gate region in order to form a gate electrode, and FIG. 8 illustrates forming a source and a drain in the upper silicon layer 13 after the etching process as shown in FIG. 7. In order to form the channel using the ion implantation method, it is preferable that the MOSFET structure.

FIG. 9 shows that the silicon insulating film 20 is formed to form electrodes on the source, drain, and gate. In FIG. 10, the formed silicon insulating film 20 is removed through an etching process, and FIG. 11 shows the etching. The metal electrode 21 is formed after etching to expose the electrode forming portions of the source, drain, and gate on the silicon insulating film 20 removed through the process.

As described above, according to the method of manufacturing a nano-floating gate type nonvolatile memory device according to the present invention, it is possible to expand the material applicability of a silicon-based memory device, and use a metal nanoparticle layer to achieve high capacity and high speed of nonvolatile memory. Since it is possible to manufacture the memory device, there is a high applicability to the next-generation nonvolatile memory device.

Claims (7)

Preparing a semiconductor substrate in which an insulating layer and an upper silicon layer are sequentially stacked on the SOI substrate; Patterning the upper silicon layer and stacking a first tunnel barrier insulating film on the exposed insulating layer and the upper silicon layer; Stacking a second tunnel barrier insulating film on the first tunnel barrier insulating film; Forming a nano quantum dot by forming a metal and a metal oxide nanoparticle layer on the second tunnel barrier insulating layer by a physical deposition method or a chemical method using a polymer material; Forming a nano floating gate by forming first and second control insulating layers on the nano quantum dots of the formed metal and metal oxide nanoparticle layers; A fifth step of forming a source and a drain channel region by etching ions, leaving only the region where the gate is to be formed using a mask to form the source, drain, and gate, and then implanting ions into the exposed upper silicon film; And a sixth step of forming a silicon insulating film to form electrodes of the source, drain, and gate, etching the exposed electrode forming portions of the source, drain, and gate, and forming a metal electrode. A method of manufacturing a floating gate type nonvolatile memory device. The method according to claim 1, The first tunnel barrier insulating film is silicon oxide (SiO ₂ ) and silicon nitride (SiO _2.1 N ₁ , SiO _1.3 N ₁ ), and is formed using dry oxidiation and physical vapor deposition (PVD). Method of manufacturing a nano floating gate type nonvolatile memory device, characterized in that. The method according to claim 1 or 2, The first tunnel barrier insulating film is formed of any one material selected from silicon oxide (SiO ₂ ) and silicon nitride (SiO _2.1 N ₁ , SiO _1.3 N ₁ ), and stacked on the SOI substrate with a thickness of 1 to 3 nm. A method of manufacturing a nano floating gate type nonvolatile memory device. The method according to claim 1, The second tunnel barrier insulating film is formed of any one selected from high-k dielectric materials such as hafnium oxide (HfO ₂ ) and zirconium oxide (ZrO ₂ ), and is characterized in that the nano-layer is laminated with a thickness of 5 to 7 nm. A method of manufacturing a floating gate type nonvolatile memory device. The method according to claim 1, The metal and metal oxide nanoparticle layers have a particle size of 3 to 4 nm in diameter, a density of 1 x 10 ¹² to 5 x 10 ¹² cm ^-2 , and a thickness of 0.5 to 1 nm. Method of manufacturing a memory device. The method according to claim 1, The first control insulating layer is formed of any one material selected from high dielectric materials such as hafnium oxide (HfO ₂ ) and zirconium oxide (ZrO ₂ ), and has an atomic layer on the metal and metal oxide nanoparticle layer with a thickness of 5 to 10 nm. A method of manufacturing a nano-floating gate type nonvolatile memory device, which is formed by an Atomic Layer Deposition (ALD) and a Physical Vapor Deposition (PVD). The method according to claim 1, The second control insulating layer is formed of any one selected from silicon oxide (SiO ₂ ) and silicon nitride (SiO _2.1 N ₁ , SiO _1.3 N ₁ ), and has a thickness of 5 to 10 nm on the first control insulating layer. A method of manufacturing a nano-floating gate type nonvolatile memory device, which is formed by physical vapor deposition (PVD).

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