KR20080003042A - Electrostatic discharge protection element - Google Patents

Abstract

An electrostatic discharge protection element is provided to reduce the area of an electrostatic discharge protection element by forming a clamp device in a region where a dual diode is formed. A second conductive well is formed in a predetermined region of a semiconductor substrate(10) of a first conductivity type. A first conductive well of a higher density than that of the semiconductor substrate is formed in a predetermined region of the semiconductor substrate, coming in contact with the second conductive well and parallel with the second conductive well. A first conductive diode is formed in the center of the second conductive well. A second conductive diode is formed in the first conductive well, parallel with the first conductive diode. A first impurity region of the first conductivity type is formed in the second conductive well, separated from the first conductive diode by a predetermined interval and surrounding the first conductive diode. A gate is formed in a predetermined region on the semiconductor substrate, separated from one side of the second conductive diode. A second impurity region of the second conductivity type is formed in the first conductive well under both sides of the gate. In the first conductive diode, a third impurity region of the first conductivity type is formed in the center of the second conductive well, and a fourth impurity region of the second conductivity type is formed at both sides of the third impurity region.

Description

Electrostatic discharge protection element

1 is a block diagram showing an electrostatic discharge protection circuit using a dual diode of the prior art.

2 is a layout showing the structure of the electrostatic discharge protection element according to the first embodiment of the present invention.

3 is a cross-sectional view taken along the line X-X 'of the electrostatic discharge protection device of FIG.

4A to 4B show an electrostatic discharge path of an electrostatic discharge protection circuit using the electrostatic discharge protection element of the present invention.

5A-5B are cross-sectional views of the electrostatic discharge path of FIGS. 4A-4B.

6 is a cross-sectional view showing a structure of an electrostatic discharge protection device according to a second embodiment of the present invention.

7 is a cross-sectional view showing a structure of an electrostatic discharge protection device according to a third embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to an electrostatic protection circuit using a dual diode.

Semiconductor devices are very sensitive to high voltages coming from external electrostatic discharges (or electrostatic currents). When a high voltage flows into an internal circuit of a semiconductor device at a time due to the electrostatic discharge (ESD) phenomenon, the internal circuit itself is destroyed by destroying a thin insulating film, a channel, etc. formed in the internal circuit. Therefore, the semiconductor device installs an ESD protection circuit between the pad and the internal circuit to protect the internal circuit from the ESD, so as to discharge in advance to prevent the instantaneous high voltage or high current from entering the internal circuit.

Protection elements used in such ESD protection devices are mainly diodes, resistors, and transistors. Recently, silicon controlled rectifiers (SCRs) using PN junctions are referred to as SCRs. Also used).

However, since the diode has a large reverse turn on voltage and low electrostatic discharge protection in the reverse state, the dual diode is used to prevent the reverse turn-on of the diode and to use the forward characteristic. ).

1 is a block diagram showing an ESD protection circuit using a dual diode of the prior art.

As shown in FIG. 1, in the conventional ESD protection circuit using dual diodes, diodes D01 and D02 are disposed on both sides of a pad PAD, and clamps are provided between power rails. By further placing, it is possible to provide the forward characteristics of the diode to all discharge paths.

In addition, the resistance component between the clamp and the diodes D01 and D02 should be minimized in order to induce forward characteristics of the diodes D01 and D02. For this purpose, a clamp must be placed as close to the diode as possible.

As described above, in the case of using the conventional dual diode as the ESD protection device, there is a problem in that the area of the ESD protection circuit increases due to the clamp device additionally provided. In addition, in a situation where the size of the pad and the spacing between the pads are reduced, there is a problem that it becomes increasingly difficult to place a clamp having a large area close to the diode.

When the SCR is used as an ESD protection element, the current consumption per unit area is large, but due to the high trigger voltage (or turn-on voltage and threshold voltage) of the SCR, the ESD protection circuit operates when static electricity is generated. There is a problem that the gate oxide film of the semiconductor internal device may be damaged before.

Accordingly, an object of the present invention is to provide an ESD protection device having an improved area by embedding a clamp device in a dual diode.

Another object of the present invention is to provide an ESD protection device having improved performance by improving forward characteristics of a dual diode.

In order to achieve the above object, the electrostatic discharge protection device of the present invention, the second conductivity type formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well; A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; A gate spaced apart from one side of the second conductive diode by a predetermined region and formed in a predetermined region on the semiconductor substrate; And a second impurity region of a second conductivity type formed in the first conductivity type well below both sides of the gate.

In the first conductive diode, a third impurity region of a first conductivity type is formed in a center portion of the second conductivity type well, and the second conductivity type fourth is parallel to the both sides of the third impurity region at predetermined intervals. Impurity regions are formed.

Preferably, the third impurity region is connected to the input / output pad, and the fourth impurity region is connected to the power supply terminal.

In the second conductive diode, a fifth impurity region of the second conductivity type is formed in the center of the first conductivity type well, and the sixth conductivity type sixth electrode is parallel to the second impurity region at predetermined intervals. Impurity regions are formed.

Preferably, the fifth impurity region is connected to the input / output pad, and the sixth impurity region is connected to the ground terminal.

The second conductivity type impurity region formed under one side of the gate is formed in the first conductivity type well and is connected to a ground terminal.

The second impurity region of the second conductivity type formed under the other side of the gate is formed over the first conductivity type well and the second conductivity type well.

The gate is an NMOS gate, and the gate is preferably connected to the ground terminal.

Another electrostatic discharge protection device of the present invention for achieving the object of the present invention, the second conductivity type formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well; A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; A gate spaced apart from one side of the second conductive diode by a predetermined region and formed in a predetermined region on the semiconductor substrate; Second impurity regions of a second conductivity type formed in the first conductivity type wells below both sides of the gate; And trigger assistance means for applying a voltage detected in response to the initial generation of static electricity to one side of the second impurity region.

The trigger auxiliary means comprises a resistor and a capacitor connected in series between the voltage terminal and the ground terminal.

Preferably, the trigger assist means detects a voltage drop occurring at the node between the resistor and the capacitor.

Another electrostatic discharge protection device of the present invention for achieving the object of the present invention, the second conductivity type formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well; A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; And a second impurity region of a second conductivity type spaced apart from one side of the second conductivity type diode and formed in the first conductivity type well. Characterized in that configured to include.

In the first conductive diode, a third impurity region of a first conductivity type is formed in a center portion of the second conductivity type well, and the second conductivity type fourth is parallel to the both sides of the third impurity region at predetermined intervals. Impurity regions are formed.

Preferably, the third impurity region is connected to the input / output pad, and the fourth impurity region is connected to the power supply terminal.

In the second conductive diode, a fifth impurity region of a second conductivity type is formed in a center portion of the first conductivity type well, and the first conductivity type first electrode is formed in parallel with a predetermined interval spaced on both sides of the fifth impurity region. 6 impurity regions are formed.

Preferably, the fifth impurity region is connected to the input / output pad, and the sixth impurity region is connected to the ground terminal.

One side of the second conductivity type impurity region is formed in the first conductivity type well and is connected to a ground terminal, and the other side of the second conductivity type impurity region is formed in the first conductivity type well and the second conductivity type well. It is preferable to form over.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

In addition, in all the figures for demonstrating an embodiment, the thing which has the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a layout showing the structure of the electrostatic discharge protection element according to the first embodiment of the present invention.

The first embodiment of FIG. 2 is an ESD protection device in which a clamp is used by using a part in a junction region where a dual diode is formed. The clamp of FIG. 2 is an improved trigger voltage to improve the high trigger voltage of the SCR. Low Voltage Triggered Silicon Controlled Rectifier (LVTSCR, hereinafter referred to as LVTSCR).

Referring to FIG. 2, the ESD protection device according to the first embodiment forms the N well region 20 and the P well region 30 in the semiconductor substrate 10 to form a dual diode. Then, the P-type diode 40 which is one of the dual diodes is formed in the N well region 20, and the N-type diode 50 which is the other one of the dual diodes is formed in the P well region 30. In addition, an LVTSCR 60 including an additional junction region and an NMOS transistor is formed in a portion of the N well region 20 and the P well region 30 in which a dual diode is formed.

In more detail, in the N well region 20, a P-type impurity region 62 is formed to be spaced apart from the P-type diode 40 by a predetermined interval and surround the P-type diode 40.

In the P well region 30, N-type impurity regions 66 and 68 are formed at both sides with a predetermined distance from one side of the N-type diode 50 at the center of the gate 64 of the NMOS transistor. In this case, the N-type impurity region 66 is formed to overlap the N well region 20 and the P well region 30.

3 is a cross-sectional view taken along the line X-X 'of the electrostatic discharge protection device of FIG.

Referring to FIG. 3, the N well region 20 and the P well region 30 are formed to abut on the P-type semiconductor substrate 10.

The P-type diode 40 formed in the N well region 20 has a P-type impurity region 42 formed at the center thereof, is connected to the input / output pad PAD, and is spaced apart at predetermined intervals from both sides of the P-type impurity region 42. N-type impurity regions 44 and 46 are formed in parallel and connected to the power supply terminal VDD.

In addition, the P-type impurity region 62, which is additionally spaced apart from the P-type diode 40 by a predetermined interval in the N well region 20, is connected to the power supply terminal VDD to serve as an anode of the embedded LVTSCR 60. Do it.

The N-type diode 50 formed in the P well region 30 has an N-type impurity region 52 formed at a central portion thereof, is connected to the input / output pad PAD, and is spaced a predetermined distance from both sides of the N-type impurity region 52. P-type impurity regions 54 and 56 are formed in parallel and connected to the ground terminal VSS.

The N-type diode 50 is spaced apart from one side of the N-type diode 50 in the P well region 30, and the N-type is formed on both sides of the gate 64 formed by interposing a gate oxide film in a predetermined region on the semiconductor substrate 10. Impurity regions 66 and 68 are formed. Here, the gate 64 is an NMOS gate, and the N-type impurity region 66 is formed over the N well region 20 and the P well region 30.

The gate 64 and the N-type impurity regions 66 and 68 thus formed form an NMOS transistor. In this case, the gate 64 and the N-type impurity region 68 are connected to the ground terminal VSS to serve as a cathode of the LVTSCR 60, and to the N well region 20 and the P well region 30. The N-type impurity region 66 formed over exists in a floating state, and serves to lower the breakdown voltage in the intermediate junction region.

As described above, an additional junction region (P-type impurity region 62) and NMOS transistors 64, 66, 68 are disposed in the region where the dual diode is formed, thereby forming a dual diode incorporating the LVTSCR 60 clamp. .

An electrostatic discharge path of an ESD protection circuit using such an ESD protection element is shown in FIGS. 4A to 4B.

First, referring to FIG. 4A, the electrostatic discharge path of the ESD protection circuit is shown. Referring to FIG. 1, in the case where positive static electricity is generated from the input / output pad PAD, the P-type diode 40 and the built-in LVTSCR clamp ( 60 shows a current path formed to the ground terminal VSS.

In addition, in FIG. 4A, when negative static electricity is generated from the input / output pad PAD, an input / output pad (N / O diode 50) is passed through the N-type diode 50 at the ground terminal VSS to dissipate the negative static electricity. Current path generated by PAD).

Next, referring to FIG. 4B, the electrostatic discharge path of the ESD protection circuit is shown. Referring to FIG. 4B, reference numeral 3 of FIG. 4B indicates that when positive static electricity is generated from the input / output pad PAD, a power supply terminal (P) is connected through the P-type diode 40. VDD) shows a current path.

In addition, reference numeral 4 of FIG. 4B denotes an LVTSCR clamp 60 and a ground terminal VSS built in the power supply terminal VDD in order to dissipate the negative static electricity when negative static electricity is generated from the input / output pad PAD. The current path generated through the N-type diode 50 to the input / output pad PAD is shown.

5A to 5B are cross-sectional views of the electrostatic discharge path of FIGS. 4A to 4B.

Referring to FIG. 5A, referring to the current path of FIG. 1 in detail in FIG. 4A, the positive static electricity generated from the input / output pad PAD is transferred to the N well region through the P-type impurity region 42 of the P-type diode 40. 20 flows into the line to which the power supply terminal VDD is connected through the N-type impurity regions 44 and 46 on both sides of the P-type impurity region 42. Then, the P-type impurity region 62 corresponding to the anode of the LVTSCR formed in the N well region 20 flows back into the N well region 20 and the N-type impurity region 68 formed in the P well region 30. Is discharged to the ground terminal VSS.

Referring to FIG. 5A, referring to the current path of FIG. 2 in detail in FIG. 4A, the negative static electricity generated from the input / output pad PAD is transferred to the P-type impurity region 54 of the N-type diode 50 at the ground terminal VSS. , And through the P well region 30 through 56, through the N-type impurity region 52, and by the current path formed by the input / output pad PAD.

Referring to FIG. 5B, when the discharge path of reference numeral 3 of FIG. 4B is described in detail, the positive static electricity generated from the input / output pad PAD is transferred to the N well region through the P-type impurity region 42 of the P-type diode 40. 20, discharged to the power supply terminal VDD through the N-type impurity regions 44 and 46 on both sides of the P-type impurity region 42.

Referring to FIG. 5B, referring to the current path indicated by reference numeral 4 of FIG. 4B, the positive static electricity generated from the input / output pad PAD is N well region 20 corresponding to the anode of the LVTSCR built in the power supply terminal VDD. Is connected to the ground terminal (VSS) line through the N-type impurity region 68 formed in the P well region 30, and is formed through the P-type impurity region 62 in the P well region 30. It is extinguished by the current path formed through the P well region 30 through the 54 and 56 through the N-type impurity region 52 to the input / output pad PAD.

 By using such a dual diode with a built-in clamp as an ESD protection device, the area of the ESD protection circuit is improved.

In addition, by embedding the clamp within the dual diode, the distance between the diode and the clamp is reduced to reduce the resistance, resulting in improved performance of the ESD protection circuit.

6 is a cross-sectional view showing the structure of an electrostatic discharge protection device according to a second embodiment of the present invention.

The electrostatic discharge protection device of FIG. 6 is formed so that the N well region 20 and the P well region 30 abut on the semiconductor substrate 10 to form a dual diode, and the N well region 20 is formed of the dual diode. One P-type diode 40 is formed, and the other N-type diode 50 of the dual diodes is formed in the P well region 30. The structure is similar to that of FIG. 3 in which an LVTSCR 60 including an additional junction region and an NMOS transistor is formed in a portion of the N well region 20 and the P well region 30 in which a dual diode is formed.

However, the electrostatic discharge protection device according to the second embodiment of FIG. 6 further includes a trigger assistance means 70 in addition to the electrostatic discharge protection device according to the first embodiment of FIG. 3.

The trigger auxiliary means 70 includes a resistor R1 and a capacitor C1 connected in series between the voltage terminal VDD and the ground terminal VSS.

In addition, the trigger auxiliary means 70 detects a voltage drop generated at the node between the resistor R1 and the capacitor C1 in response to an alternating current at the initial stage of static electricity generation and is present in a floating state in FIG. 3. The N-type impurity region 66 formed over the well region 20 and the P well region 30 is applied.

Therefore, when static electricity is generated and the voltage of the input / output pad PAD rises, the bipolar transistor parasitic in the NMOS transistor is operated prior to the LVTSCR, thereby improving the operation speed of the ESD protection circuit.

7 is a cross-sectional view showing the structure of an electrostatic discharge protection device according to a third embodiment of the present invention.

The third embodiment of FIG. 7 is an ESD protection device in which a clamp is used by using a part in a junction region where a dual diode is formed, and the clamp included in FIG. 7 is an improved modification number to improve the high trigger voltage of the SCR. Modified lateral Silicon Controlled Rectifier (MLSCR, hereinafter referred to as MLSCR). The structure of the MLSCR is similar to that of the LVTSCR, except that a thick oxide film is used in place of the gate of the LVTSCR.

Referring to FIG. 7, the ESD protection device according to the third embodiment forms the N well region 20 and the P well region 30 in the P-type semiconductor substrate 10 to form a dual diode. Then, the P-type diode 40 which is one of the dual diodes is formed in the N well region 20, and the N-type diode 50 which is the other one of the dual diodes is formed in the P well region 30. In addition, an additional junction region is formed in a portion of the N well region 20 and the P well region 30 in which the dual diode is formed to form the MLSCR 80.

In more detail, the P-type diode 40 formed in the N well region 20 has a P-type impurity region 42 formed at the center thereof and is connected to the input / output pad PAD, and both sides of the P-type impurity region 42 are formed. N-type impurity regions 44 and 46 are formed to be spaced apart from each other at a predetermined interval so as to be connected to the power supply terminal VDD.

In addition, the P-type impurity region 82, which is additionally spaced apart from the P-type diode 40 by a predetermined interval in the N well region 20, is connected to the power supply terminal VDD to serve as an anode of the embedded MLSCR 80. Do it.

The N-type diode 50 formed in the P well region 30 is formed with an N-type impurity region 52 at a central portion thereof, connected to the input / output pad PAD, and spaced apart from each other by both sides of the N-type impurity region 52. As a result, P-type impurity regions 54 and 56 are formed in parallel and connected to the ground terminal VSS.

N-type impurity regions 84 and 86 are formed in the P well region 30 by being spaced apart from one side of the N-type diode 50 by a predetermined interval. Here, a thick oxide film (not shown) is formed between one side of the N-type impurity region 84 and one side of the N-type impurity region 86 facing each other, so that these N-type impurity regions 84 and 86 are isolated.

In addition, the N-type impurity region 84 is formed over the N well region 20 and the P well region 30 and exists in a floating state, and serves to lower the breakdown voltage in the intermediate junction region. The other N-type impurity region 86 is connected to the ground terminal VSS to serve as a cathode of the MLSCR 80.

As described above, additional diodes (P-type impurity regions 82 and N-type impurity regions 84 and 86) are disposed in the region where the dual diodes are formed, thereby forming a dual diode incorporating the MLSCR 80 clamp. .

The electrostatic discharge path of the ESD protection circuit using the ESD protection device according to the third embodiment of FIG. 7 is the same as the electrostatic discharge path of the ESD protection circuit using the ESD protection device according to the first embodiment of FIG. Let's do it.

Meanwhile, in the above-described embodiment of the present invention, the dual diode having the LVTSCR or the MLSCR as a clamp is illustrated and described. The configuration of the present invention can be applied to dual diodes in which various SCRs are embedded as clamps.

Therefore, according to the present invention, the clamp element is formed in the region where the dual diode is formed, thereby improving the area of the element, thereby reducing the area of the ESD protection element.

In addition, according to the present invention, by forming the clamp element in the region in which the dual diode is formed, the resistance component between the dual diode and the clamp is lowered by shortening the distance between the diode and the clamp, thereby improving the discharge performance of the ESD protection element. .

Claims (23)

A second conductivity type well formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well;  A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; A gate spaced apart from one side of the second conductive diode by a predetermined region and formed in a predetermined region on the semiconductor substrate; And Second impurity regions of a second conductivity type formed in the first conductivity type wells below both sides of the gate; Electrostatic discharge protection element, characterized in that configured to include. The method of claim 1, In the first conductive diode, a third impurity region of a first conductivity type is formed in a center portion of the second conductivity type well, and a second conductivity type parallel electrode is spaced apart at a predetermined interval on both sides of the third impurity region. 4, wherein the impurity region is formed. The method of claim 2, And the third impurity region is connected to an input / output pad. The method of claim 2, And the fourth impurity region is connected to a power supply terminal. The method of claim 1, In the second conductive diode, a fifth impurity region of the second conductivity type is formed in the center of the first conductivity type well, and the sixth conductivity type sixth electrode is parallel to the second impurity region at predetermined intervals. An electrostatic discharge protection element, characterized in that an impurity region is formed. The method of claim 5, And the fifth impurity region is connected to an input / output pad. The method of claim 5, And the sixth impurity region is connected to a ground terminal. The method of claim 1, And the second conductivity type impurity region formed under one side of the gate is formed in the first conductivity type well and connected to a ground terminal. The method of claim 1, And the second impurity region of the second conductivity type formed under the other side of the gate is formed over the first conductivity type well and the second conductivity type well. The method of claim 1, And the gate is an NMOS gate. The method of claim 1, And the gate is connected to the ground terminal. A second conductivity type well formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well;  A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; A gate spaced apart from one side of the second conductive diode by a predetermined region and formed in a predetermined region on the semiconductor substrate; Second impurity regions of a second conductivity type formed in the first conductivity type wells below both sides of the gate; And Trigger assistance means for applying a voltage detected in response to an initial generation of static electricity to one side of the second impurity region; Electrostatic discharge protection element, characterized in that configured to include. The method of claim 12, And the trigger assisting means comprises a resistor and a capacitor connected in series between the voltage terminal and the ground terminal. The method of claim 13, And the trigger assisting means detects a voltage drop occurring at a node between the resistor and the capacitor. A second conductivity type well formed in a predetermined region of the first conductivity type semiconductor substrate; A first conductivity type well formed in contact with the second conductivity type well in a predetermined area of the semiconductor substrate at a higher concentration than the semiconductor substrate; A first conductivity type diode formed in a center portion of the second conductivity type well; A second conductive diode parallel to the first conductive diode and formed in the first conductive well;  A first impurity region of a first conductivity type formed in the second conductivity type well and spaced apart from the first conductivity type diode to surround the first conductivity type diode; And A second impurity region of a second conductivity type spaced apart from one side of the second conductivity type diode and formed in the first conductivity type well; Electrostatic discharge protection element, characterized in that configured to include. The method of claim 15, In the first conductive diode, a third impurity region of a first conductivity type is formed in a center portion of the second conductivity type well, and the second conductivity type fourth is parallel to the both sides of the third impurity region at predetermined intervals. An electrostatic discharge protection element, characterized in that an impurity region is formed. The method of claim 16, And the third impurity region is connected to an input / output pad. The method of claim 16, And the fourth impurity region is connected to a power supply terminal. The method of claim 15, In the second conductive diode, a fifth impurity region of the second conductivity type is formed in the center of the first conductivity type well, and the sixth conductivity type sixth electrode is parallel to the second impurity region at predetermined intervals. An electrostatic discharge protection element, characterized in that an impurity region is formed. The method of claim 19, And the fifth impurity region is connected to an input / output pad. The method of claim 19, And the sixth impurity region is connected to a ground terminal. The method of claim 15, One side of the second conductivity type impurity region is formed in the first conductivity type well, characterized in that connected to the ground terminal. The method of claim 15, And the other side of the second conductivity type impurity region is formed over the first conductivity type well and the second conductivity type well.

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