KR20080002124A - Display device - Google Patents

Abstract

A display device is provided to compensate a brightness difference according to a difference between hold periods of pixels on gate lines by compensating pixel data at different rates or changing a gamma voltage set according to gate lines simultaneously responding to black data, thereby keeping brightness in the front of an LCD panel and realizing an image completely. A display device comprises a gate driver(12), a data driver(14), a timing controller(16), an impulse driving controller(18), a scan line detector(20), and an adaptive gamma voltage generator(22). The scan line detector detects a gate line(GL1~GLn) enabled in response to a gate timing signal supplied from the timing controller to the gate driver. The adaptive gamma voltage generator supplies one of plural gamma voltage sets, of which the level increases gradually according to the gate line detected by the scan line detector, to the data driver.

Description

Display Device

In order to better understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram illustrating an embodiment of the adaptive gamma voltage generator of FIG. 1 in detail.

3 is a detailed block diagram illustrating another exemplary embodiment of the adaptive gamma voltage generator of FIG. 1.

4 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 5 is a detailed block diagram illustrating in detail the line adaptation compensator illustrated in FIG. 4.

`` Explanation of symbols for main parts of drawings ''

10 liquid crystal panel 12 gate driver

14: data driver 16: timing control unit

18 impulse drive control unit 20 scan line detection unit

22: adaptive gamma voltage generator

30 to 36: first to fourth gamma voltage generator 38: multiplexer

40: Look-up Table 42: DAC Array

The present invention relates to a liquid crystal display, an electroluminescent-type display, or a pixel driven by a switching element using amorphous silicon, polycrystalline silicon, or the like for each pixel. The present invention relates to a display device including a light emitting element such as a light emitting diode (LED), and more particularly to a display device for performing a blanking process.

A display device for holding light emitted from each of a plurality of pixels on a basis of a predetermined amount (for example, a period of length corresponding to one frame period) on the basis of image data input for each frame period. Liquid crystal display devices are becoming popular. In an active matrix liquid crystal display device, a switching element (eg, a thin film transistor) that supplies a pixel electrode and a video signal to each of a plurality of pixels arranged in a two-dimensional or matrix shape. ) Is installed. The video signal is supplied to the pixel electrode through the switching element, for example, from one of a plurality of data lines (called video signal lines) extending in the vertical direction of the screen. The switching elements are arranged at predetermined intervals (for example, 1) from one of a plurality of gate lines (called scan signal lines) extending across the plurality of data lines (for example, in the horizontal direction of the screen). Each frame period) receives a scan signal and supplies a video signal to one of the plurality of data lines to the pixel electrode. Therefore, the switching element maintains the pixel electrode at a potential based on the " video signal supplied thereto according to the previous scan signal " until the next scanning signal is received, and maintains the pixel provided with this pixel electrode at the desired brightness. .

This operation is in contrast to the impulse emission operation of a cathode-ray tube, which is represented by a braun tube that emits a phosphor installed at each pixel at the moment of receiving an image signal. With respect to this impulse light emission, the image display operation of the liquid crystal display device of the same active matrix system described above is often referred to as hold-type emission. In addition, image display such as an active matrix liquid crystal display device is also employed in a display device of an electroluminescence type (referred to as EL type) or a light emitting diode array type, and the operation is performed by controlling the voltage control of the pixel electrode described above. The description will be made by substituting the carrier injection amount control to the luminescence element or the light emitting diode.

The display device using such hold light emission displays an image by holding each brightness of the pixel within a predetermined period, and thus displays the image displayed according to, for example, another image between the successive pair of the frame periods. When replacing with, the pixel does not respond sufficiently. This phenomenon corresponds to a pixel set to a predetermined brightness in a certain frame period (e.g., the first frame period) even in the next frame period (e.g., the second frame period) following this frame period. It is explained from maintaining the brightness according to the previous frame period (the first frame period) until it is set to one brightness. In addition, this phenomenon is characterized in that a part of the video signal (or a corresponding amount of charge) sent to the pixel in any of the above-described frame periods (first frame period) is changed in the following frame period (second frame period). It is also explained from the so-called hysteresis of the video signal in each pixel, which interferes with the video signal (or the amount of electric charge accordingly) to be sent to the pixel. When a moving image is displayed by a display device (for example, a liquid crystal display) using hold type light emission, so-called blurring in which the outline of an object becomes unclear as compared to a cathode ray tube which emits pixels impulsely. Blurring Phenomenon is caused.

In order to solve this blurring phenomenon, a method of driving pixels in an impulse form is proposed by sequentially supplying image signals to the pixels in line units so that the pixels on at least two adjacent lines are blocked. In such an impulse driving method, since the pixels sequentially respond to the image signal in units of lines, the image display period differs by the line scanning period between the lines simultaneously blanked. As a result, a difference in luminance occurs between at least two pixel lines to which the blanking signal is simultaneously applied.

Accordingly, an object of the present invention is to provide a display device capable of maintaining uniform luminance even when pixels on at least two lines are simultaneously blanked.

In accordance with an aspect of the present invention, a display device includes: a display panel in which pixels are formed in a pixel area divided by a plurality of gate lines and a plurality of data lines; A gate driver enabling the plurality of gate lines sequentially and simultaneously enabling at least two or more adjacent gate lines at the same time; A data driver for supplying one line of pixel driving signals to the plurality of data lines when at least one of the plurality of gate lines is enabled; A timing controller which controls an operation timing of the gate driver and the data driver; An impulse driving control section for interpolating black line data for one line into video data to be supplied to the data driver; A scan line detector configured to detect a gate line enabled in response to a gate timing signal supplied from the timing controller to the gate driver; And an adaptive gamma voltage generator for supplying a data driver to any one of a plurality of gamma voltage sets whose level is gradually increased according to the gate line detected by the scan line detector.

According to an embodiment of the present invention, a display panel includes pixels in pixel regions divided by a plurality of gate lines and a plurality of data lines; A gate driver enabling the plurality of gate lines sequentially and simultaneously enabling at least two or more adjacent gate lines at the same time; A data driver for supplying one line of pixel driving signals to the plurality of data lines when at least one of the plurality of gate lines is enabled; A timing controller which controls an operation timing of the gate driver and the data driver; An impulse driving control section for interpolating black line data for one line into video data to be supplied to the data driver; And a line adaptation compensator configured to compensate the gray value of the video data to be supplied to the impulse driving controller according to the gate line.

In addition to the objects of the present invention as described above, other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 1, a gate driver 12 connected to a plurality of gate lines GL1 to GLn on a liquid crystal panel 10 and a data driver connected to a plurality of data lines DL1 to DLm on a liquid crystal panel 10. (14) is provided. The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are formed on the liquid crystal panel 10 to cross each other so that the plurality of pixel regions are distinguished. Each pixel area of the plurality of pixel regions switches a pixel driving signal to be supplied to a corresponding liquid crystal cell (not shown) from a corresponding data line DL in response to a scan signal on a corresponding gate line GL (not shown). Not formed). The liquid crystal cell adjusts the amount of light passing through the pixel region according to the voltage level of the pixel driving signal to enable an image to be displayed. As a result, a pixel including one thin film transistor and one liquid crystal cell is formed in each pixel area.

The gate driver 12 enables the plurality of gate lines GL1 to GLn sequentially for a predetermined period for one frame. While the plurality of gate lines GL1 to GLn are sequentially enabled, the plurality of gate lines GL1 to GLn are enabled at least two or more simultaneously. To this end, the gate driver 12 has a first enable pulse shifted sequentially in sequence smaller than the horizontal synchronization signal, and has a scan signal and a phase to be supplied to at least one adjacent gate line GL. And a plurality of scan signals having a second enable pulse having a matching width. The gate enable pulse included in each of the plurality of scan signals has a width smaller than that of the horizontal synchronization signal. The first and second enable pulses included in each of the plurality of scan signals are generated once per frame period.

Whenever one of the plurality of gate lines GL1 to GLn is enabled, the data driver 14 corresponds to the number of data lines DL1 to DLm corresponding to one pixel line (ie, one gate line). Pixel driving signals corresponding to the number of pixels arranged in the. Each pixel driving signal corresponding to one line is supplied to a corresponding pixel (ie, a liquid crystal cell) on the liquid crystal panel 10 via a corresponding data line DL. Each of the pixels arranged on the gate line GL passes an amount of light corresponding to a voltage level of the pixel driving signal. In order to generate one line of pixel driving signals, the data driver 14 sequentially inputs one line of pixel data for each period of the enable pulse included in the scan signal, and sequentially sequentially inputs one pixel of the pixel. Simultaneously convert data to analog form. When the plurality of gate lines GL1 to GLn are sequentially and exclusively enabled, the data driver 14 supplies a pixel driving signal having a voltage (or current) corresponding to the gray value of the pixel data on the data line DL. do. In contrast, when two or more gate lines are simultaneously enabled, the pixel driving signal having a voltage (or current) corresponding to a black gray value is supplied to all of the data lines DL1 to DLm, so that at least two are simultaneously enabled. The pixels on the above gate lines enter the turn-off state. As a result, the liquid crystal panel 10 is driven in an impulse manner.

The gate driver 12 and the data driver 14 are controlled by the timing controller 16. The timing control unit 16 receives a synchronization signal from an external video data source (for example, an image signal demodulation unit included in a television receiving module or a graphics card included in a computer system) not shown via a control transmission line DTL. Enter SYNC. The synchronization signals SYNC supplied from an external video data source include a data clock Dclk, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and the like. The timing controller 16 generates a plurality of scan signals using the synchronization signals SYNC to allow the gate driver 12 to double scan the gate lines GL1 to GLn on the liquid crystal panel 10 every frame. Generate gate control signals GCS required to operate. In addition, the timing controller 16 sequentially inputs one line of pixel data for each cycle in which the data driver 12 enables the gate line GL, and sequentially inputs one line of pixel data in analog form. It generates data control signals DCS necessary to convert and output the pixel driving signal. In addition, the timing controller 16 supplies the data driver 14 so that the black pixel data is inserted one line at a time while the pixel data for the image signal is sequentially supplied to the data driver 14 by one line. .

The impulse driving control unit 18 inputs the pixel data stream VDi divided in units of frames (one image unit) from the data reception line DRL. The impulse driving control unit 18 interpolates the black data VDb for each line in the pixel data stream VDi to generate an impulse driving pixel data stream VDip. In addition, the impulse driving control unit 18 may display the pixel data VDi in one frame period (hereinafter referred to as a "hold period") or display period of black data VDb in one frame period (hereinafter referred to as "blank"). Impulse cycle data) is specified. The impulse driving pixel data stream VDip generated by the impulse driving controller 18 is supplied to the data driver 14 by the timing controller 16. Based on the impulse period data, the timing controller 16 controls the operation timings of the gate driver 12 and the data driver 14 so that the pixels on the liquid crystal panel 10 are impulse driven at a period corresponding to a logic value of the impulse period data. do.

The liquid crystal display of FIG. 1 includes a scan line detector 20 and an adaptive gamma voltage generator 22 connected in series between the timing controller 16 and the data driver 14. The scan line detector 20 is configured to display pixels on a few gate lines among gate lines at which black data VDb is simultaneously written based on the scan clock Sclk supplied from the timing controller 16 to the gate driver 12. It is detected whether data VDi is written. The rank value of the gate line detected by the scan line detector 20 is the number of gate lines to which the black data VDb is simultaneously written for each period in which the pixel driving signal for the black data VDb is supplied to the data line DL. Increases by 1. For example, when the black data VDb is simultaneously written to four gate lines, the gate line output from the scan line identification unit 22 has a value of 0 to 3 or 1 to 4 once. To this end, the scan line detector 20 may be implemented as a cyclic counter that repeatedly counts a certain range of numbers in response to the scan clock Sclk from the timing controller 16. Also, in order to prevent an error that may occur every time a frame is changed, the scan line detector 20 may be initialized by the vertical synchronization signal Vsync from the timing controller 16.

The adaptive gamma voltage generator 22 supplies the data driver 14 with a gamma voltage set whose level gradually increases in accordance with the ranking of the gate lines detected by the scan line detector 20. For example, when the priority of the detected gate lines is "1", the lowest level gamma voltage set is generated in the adaptive gamma voltage generator 22. If the detected gate line has the highest rank "4", the adaptive gamma voltage generator 22 supplies the data driver 14 with the highest level of gamma voltage set. In other words, first to fourth gamma voltage sets having a level difference depending on the order of the detected gate lines are alternately supplied to the data driver 14.

The gamma voltage set showing the difference in levels causes the voltage of the pixel driving signal output from the data driver 14 to the data line DL to be adjusted high or low according to the priority of the detected gate line. Accordingly, a plurality of gate lines (for example, four gates) sequentially charging the pixel driving signal for the pixel data VDi and then simultaneously charging the pixel driving signal for the black data VDb. The difference in luminance that may appear between the lines) is avoided. As a result, in the liquid crystal display of the impulse driving method according to the embodiment of the present invention, the luminance is uniformly maintained on the entire surface of the liquid crystal panel 10, thereby enabling faithful reproduction of the image.

FIG. 2 is a detailed block diagram illustrating an example of the adaptive gamma voltage generator 22 illustrated in FIG. 1 in detail. Referring to FIG. 2, the adaptive gamma voltage generator 22 includes a multiplexer 38 connected to first to fourth gamma voltage generators 30 to 36.

Each of the first to fourth gamma voltage generators 30 to 36 generates a gamma voltage set having a difference in voltage level. The first gamma voltage set generated by the first gamma voltage generator 30 includes gamma voltages lower than the second gamma voltage set generated by the second gamma voltage generator 32. The second gamma voltage set generated by the second gamma voltage generator 32 includes gamma voltages lower than the third gamma voltage set generated by the third gamma voltage generator 34. The third gamma voltage set generated by the third gamma voltage generator 34 includes gamma voltages lower than the fourth gamma voltage set generated by the fourth gamma voltage generator 36.

The multiplexer 38 selects any one of the first to fourth gamma voltage sets according to the order of the gate lines from the scan line detector 22 shown in FIG. 1 and uses the selected gamma voltage set as the data shown in FIG. Supply to the driver 14. The gate line ranking is composed of 2-bit data so that the first to fourth gamma voltage sets can be selected.

FIG. 3 is a detailed block diagram illustrating another embodiment of the adaptive gamma voltage generator 22 shown in FIG. 1 in detail. In FIG. 3, the adaptive gamma voltage generator 22 has a digital-analog converter (hereinafter referred to as "DAC") array 42 connected to the look-up table 40. As shown in FIG.

The look-up table 40 supplies the gamma voltage data set to the DAC array 42 in response to the gate line ranking from the scan line detector 20 shown in FIG. To this end, the look-up table 40 stores gamma voltage data sets having different gray scale values in each storage area according to the value of the gate line rank. For example, the gamma voltage data set designated by the gate line rank of "1" includes gamma voltage data having lower gray level values compared to the gamma voltage data set designated by the gate line rank of "2". The gamma voltage data set designated by the gate line rank of "2" includes gamma voltage data having lower gray level values compared to the gamma voltage data set designated by the gate line rank of "3". As the gate line rank increases, gamma voltage data sets having gradation values that are increased are stored in the look-up table 40.

The DAC array 42 includes a DAC corresponding to the number of gamma voltage data included in the gamma voltage set. This DAC array 42 converts the gamma voltage data set from the look-up table 40 into analog form to generate gamma voltage sets that differ in voltage level according to gate line rank. The gamma voltage set generated in this DAC array 42 is supplied to the data driver 14 shown in FIG.

4 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention. The liquid crystal display of FIG. 4 has the same configuration as the liquid crystal display of FIG. 1 except for including the line adaptive data compensator 24 instead of the scan line detector 20 and the adaptive gamma voltage generator 22. Have The detailed description of the components in FIG. 4 having the same name and action and effect as those shown in FIG. 1 will be considered as supported by the description with respect to FIG. 1. In addition, components in FIG. 4 having the same names and working effects as those shown in FIG. 1 will be referred to by the same reference numerals as in FIG. 1.

The line adaptation compensator 26 inputs a pixel data stream VDi divided in units of frames (one image unit) from the data reception line DRL. In addition, the line adaptation compensator 36 inputs horizontal and vertical synchronization signals Hsync and Vsync from the control reception line CRL. The line adaptation compensator 26 determines whether the pixel data from the data receiving line DRL is for the pixel on the gate line of the gate lines simultaneously responding to the black data based on the horizontal synchronization signal Hsync (that is, Rank of the gate lines). The line adaptation compensator 26 determines a compensation rate according to the ranking of the detected gate lines, and compensates the pixel data VDi from the data receiving line DRL using the determined compensation rate. Is supplied to the impulse driving control unit 18. By the compensation pixel data VDc output from the line adaptation compensator 26, the pixel on the first gate line and the second (third and fourth) gate line among the pixels on the gate lines to which black data is simultaneously written The difference in luminance due to the difference in the hold period between the pixels in the image is compensated. As a result, the luminance is uniform on the entire surface of the liquid crystal panel 10, and the image is faithfully reproduced. The line adaptation compensator 26 recognizes the first gate line by the vertical synchronization signal Vsync to prevent an error of compensation.

The impulse driving control unit 18 interpolates the black data VDb for each line into the compensation pixel data stream VDc from the line adaptation compensator 26 to generate the impulse driving pixel data stream VDip. In addition, the impulse driving control unit 18 generates impulse period data specifying a display period of the pixel data VDi in one frame period or a display period of the black data VDb in one frame period. The impulse driving pixel data stream VDip generated by the impulse driving controller 18 is supplied to the data driver 14 by the timing controller 16. Based on the impulse period data, the timing controller 16 controls the operation timing of the gate driver 12 and the data driver 14 so that the pixels on the liquid crystal panel 10 drive the impulse at a period corresponding to a logic value of the impulse period data. To be.

FIG. 5 is a detailed block diagram illustrating in detail the line adaptation compensator 26 illustrated in FIG. 4. In FIG. 5, the line adaptation compensator 26 outputs pixel data VDi from a cyclic counter 50 for inputting horizontal and vertical synchronization signals Hsync and Vsync from a control reception line CRL and a data reception line DRL. Has a look-up table 52 for inputting.

The circulation counter 50 initializes the count value in the vertical blank period in response to the vertical synchronization signal Vsync. The circulation counter 50 repeatedly generates a compensation rate data specifying a compensation rate according to the gate line by repeatedly counting up to a count value corresponding to the number of gate lines simultaneously responding to black data in response to the horizontal synchronization signal Hsync. . The logic value of this compensation rate data is changed for each period of the horizontal synchronizing signal. This compensation rate data is supplied to the look-up table 52.

The look-up table 52 uses compensation rate data from the cyclic counter 50 as an upper address and pixel data VDi as a lower address to compensate pixel data VDc on a storage area corresponding to a logical value of those data. Is supplied to the impulse driving control unit 18 shown in FIG. To this end, the look-up table 52 stores compensation pixel data sets that compensate the pixel data VDi at different compensation rates in storage areas divided according to logical values of the compensation rate data from the circulation counter 50. . As a result, look-up table 52 stores as many compensation data sets as can be counted by circular counter 50.

As described above, the display device according to the present invention compensates the pixel data at different ratios or changes the gamma voltage set according to the gate lines simultaneously responding to the black data, so that the black data is simultaneously written on the gate lines. The difference in luminance due to the difference in the hold period between the pixels is compensated. As a result, the luminance is uniform on the entire surface of the liquid crystal panel 10, and the image is faithfully reproduced.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and a person of ordinary skill in the art without departing from the spirit and scope of the present invention. It will be apparent that various modifications, changes, and equivalent other embodiments are possible. Accordingly, the scope of the present invention to be protected should be defined by the appended claims.

Claims (10)

A display panel in which pixels are formed in a pixel area divided by a plurality of gate lines and a plurality of data lines; A gate driver enabling the plurality of gate lines sequentially and simultaneously enabling at least two or more adjacent gate lines at the same time; A data driver for supplying one line of pixel driving signals to the plurality of data lines when at least one of the plurality of gate lines is enabled; A timing controller which controls an operation timing of the gate driver and the data driver; An impulse driving control section for interpolating black line data for one line into video data to be supplied to the data driver; A scan line detector configured to detect a gate line enabled in response to a gate timing signal supplied from the timing controller to the gate driver; And And an adaptive gamma voltage generator for supplying a data driver to any one of a plurality of gamma voltage sets whose levels gradually increase according to the gate line detected by the scan line detector. The method of claim 1, And a counter for a clock signal supplied from the timing controller to the gate driver. The method of claim 2, And the counter repeatedly counts a predetermined range of numbers. The method of claim 1, wherein the adaptive gamma voltage generator A plurality of gamma voltage generators for generating a plurality of gamma voltage sets that gradually rise in voltage level; And And a selector configured to supply one of the plurality of gamma voltage sets to the data driver in response to a detection signal from the scan line detector. The method of claim 1, wherein the adaptive gamma voltage generator A look-up table that reads one gamma voltage data set according to a logic value of a detection signal from the scan line detector among the plurality of gamma voltage data sets for the plurality of gamma voltage sets; And And a digital-to-analog converter for converting the gamma voltage data set from the look-up table into a gamma voltage set in analog form and supplying the gamma voltage set to the data driver. The method of claim 1, And the display panel comprises a liquid crystal panel. A display panel in which pixels are formed in a pixel area divided by a plurality of gate lines and a plurality of data lines; A gate driver enabling the plurality of gate lines sequentially and simultaneously enabling at least two or more adjacent gate lines at the same time; A data driver for supplying one line of pixel driving signals to the plurality of data lines when at least one of the plurality of gate lines is enabled; A timing controller which controls an operation timing of the gate driver and the data driver; An impulse driving control section for interpolating black line data for one line into video data to be supplied to the data driver; And And a line adaptation compensator for compensating a gray value of video data to be supplied to the impulse driving controller according to the gate line. 8. The system of claim 7, wherein the line adaptation compensator A counter counting in response to the synchronization signal; And A look for supplying compensation video data corresponding to a count value from the counter and a gradation value of video data to be supplied to the impulse driving control unit among at least two sets or more of compensation video data according to at least two compensation rates; A display device comprising an up table. The method of claim 8, And the counter repeatedly counts a predetermined range of numbers. The method of claim 7, wherein And the display panel comprises a liquid crystal panel.

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