KR20080001222A - Flash memory device - Google Patents

Abstract

A flash memory device is provided to improve cycling and bake characteristics as decreasing a sensing level in a cell with a low current level. A flash memory device constitutes one cell string by connecting a plurality of cells serially, and constitutes one cell block using a plurality of cell strings, and constitutes one plane(400) using a plurality of cell blocks. The plane is divided into a top memory cell array(410) and a bottom memory cell array(420) as referring to a page buffer(430). The page buffer is an one side page buffer. The page buffer includes a top bit line selection part to select the top memory cell array, and a bottom bit line selection part to select the bottom memory cell array.

Description

Flash memory device

1 is a block diagram of a general cell string of a NAND type flash memory device.

2 is a block diagram of a plane of a conventional NAND type flash memory device.

3 is a configuration diagram of a page buffer applied to a conventional NAND flash memory device.

4 is a block diagram of a plane of the NAND-type flash memory device according to an embodiment of the present invention.

5 is a configuration diagram of a page buffer applied to a NAND type flash memory device according to an embodiment of the present invention.

6 is a circuit diagram illustrating an example of a page buffer applied to a NAND type flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

400: plane 410: upper memory cell array

420: lower memory cell array 430: page buffer

51: upper memory cell array 52: upper bit line selector

53: lower memory cell array 54: lower bit line selector

55: precharge portion 56: latch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND-type flash memory device. In particular, by placing a page buffer in the middle of a plane, a NAND-type flash can improve cell reliability by reducing leakage current by reducing the number of junctions connected to bit lines. It relates to a memory device.

It can be programmed and erased electrically, and does not need refresh function to rewrite data at regular intervals, and to develop a large capacity memory device that can store a lot of data. NAND type flash memory devices have been developed in which they are connected in series to form a string. The NAND type flash memory device also includes a plurality of cell strings configured in parallel to form a cell block.

As shown in FIG. 1, the cell block includes a plurality of cell strings 101 and 102 as well as a drain select transistor 110 between the cell strings 101 and 102 and the drain and the cell strings 101 and 102 and the common source, respectively. And a source select transistor 120. In addition, the cells constituting the cell strings 101 and 102 are connected to different word lines WL0 to WL31, and share the word lines WL0 to WL31 with cells of the same position of adjacent cell strings. In addition, the drain select transistor 110 and the source select transistor 120 are connected to the drain select line DSL and the source select line SSL, respectively. Here, the cell strings 101 and 102 are configured by the number of bit lines BL, and accordingly, the drain select transistor 110 and the source select transistor 120 are configured as much. For example, a cell block has 32 strings and 32 word lines and 4k byte lines for 1G bits.

As shown in FIG. 2, a plurality of cell blocks 200 to 20n, for example, 1023 cell blocks, constitute one plane 210. In addition, one cell block shares a common source and drain with adjacent cell blocks. That is, the cell block 201 is described as an example. The cell block 201 shares a common source line with the cell block 200 and shares a drain with the cell block 202. .

One page buffer 220 is positioned above or below the plane 210. That is, the page buffer 220 is positioned above the cell block 200 or the n cell block 20n. In addition, since the bit line extends from the page buffer 220 to the end of one plane 210, it is connected through all drain and drain contacts. Thus, for example, 1G has 1 drain contact per 2 blocks, and 1024 blocks per plane, so 512 drain contacts per bit line. In the case of 2G single-level cells, one plane consists of 2048 blocks, so 1024 drain contacts are connected per bit line.

3 is a block diagram illustrating a configuration of a page buffer of a general NAND type flash memory device.

Referring to FIG. 3, a page buffer includes a bit line selector 32 connected between a bit line (even and an odd) and a sensing node SO of a memory cell array 31 having a plurality of memory cells, and a sensing node ( A precharge unit 33 connected to the SO and a latch 34 connected between the sensing node SO and the input / output terminal YA. The bit line selector 32 selects an even bit line BLe or an odd bit line BLo according to a selection signal during a program, read or verify operation, and connects the even bit line BLo or an odd bit line BLo to the sensing node SO. The precharge unit 33 precharges the potential of the sensing node SO to a predetermined potential level. The latch 34 temporarily stores data input through the input / output terminal YA during programming and transmits the data to the selected bit line through the sensing node SO, or temporarily stores cell data loaded on the bit line during a read or verify operation. After output, output through I / O terminal (YA).

The page buffer detects the sensing current level and recognizes the erase when a current higher than the sensing current level flows into the bit line, and recognizes the program when the current flows below the sensing current level. The most important noise in determining the sense current level is the off-cell current, or bitline leakage current. The bit line leakage current mostly consists of drain contact leakage and drain select line (DSL) leakage. As a result, the sensing level of the page buffer is determined at a level in which bit margin is added to a margin.

However, in the case of a flash memory cell, the tunnel oxide film and the dielectric film must be kept at a sufficient thickness to secure retention characteristics, and as the cell size is reduced, the cell current becomes smaller. In addition, cycling and baking, the most important determinant of NAND-type flash memory devices, are much improved when the cell's sensing current level is lowered. Since the GM characteristic, which was reduced during cycling, is restored to its original state at bake, i.e., the slope is changed, the lower the sensing level, the lower the threshold voltage shift. Therefore, the sensing level of the page buffer should be sufficiently lowered to secure sufficient cell current and to improve cycling and bake threshold voltage shift characteristics. However, as already explained, there is a limit to lowering the sensing level due to drain contact leakage and drain select line leakage.

It is an object of the present invention to provide a flash memory device capable of sufficiently lowering a sensing level even in a cell having a low current level and improving cycling and baking characteristics.

Another object of the present invention is to place the page buffer in the middle of the plane, and to drive the upper memory cell array and the lower memory cell array separately around the page buffer to reduce the bit line leakage current to sufficiently lower the sensing level of the page buffer. To provide a flash memory device.

In a flash memory device according to an embodiment of the present invention, a plurality of cells are connected in series to form one cell string, the plurality of cell strings constitute one cell block, and the plurality of cell blocks are one plane. In the flash memory device constituting the memory device, the plane is divided into upper and lower memory cell arrays based on the one side page buffer.

The page buffer may include an upper bit line selector for selecting the upper memory cell array; And a lower bit line selector for selecting the lower memory cell array.

The upper bit line selector is connected in series between the even bit line and the odd bit line and applies first and second verify voltages to the even bit line and the odd bit line in response to first and second discharge signals, respectively. A transistor, coupled between the even bit line and the sense node, between the odd bit line and the sense node, respectively, selectively selecting the even bit line and the odd bit line in response to first and second bit line selection signals. Third and fourth transistors coupled to the sensing node.

In a flash memory device according to an embodiment of the present invention, a plurality of cells are connected in series to form one cell string, the plurality of cell strings constitute one cell block, and the plurality of cell blocks are one plane. Wherein the plane is divided into upper and lower memory cell arrays based on a one side page buffer, wherein the upper bit line selector is enabled to select a program of the upper memory cell array. Performing a read operation, or a verify operation, and executing a program, read operation, or verify operation of the selected lower memory cell array by enabling the lower bit line selector to select the upper bit line. The lower bit line selector is disabled while add is enabled. The upper bit line selection unit is disabled while the lower bit line select part is enabled.

The upper memory cell array and the lower memory cell array are implemented on different wells.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

4 is a configuration diagram of a plane of a NAND type flash memory device according to an embodiment of the present invention.

Referring to FIG. 4, in the NAND type flash memory device according to an embodiment of the present invention, a page buffer 430 is positioned between one plane 400. That is, the page buffer 430 is positioned in a predetermined region of one plane 400, preferably in the middle region of the plane 400, so that the plane 400 is divided into upper and lower memory cell arrays 410 and 420. . Since the plane 400 is composed of a plurality of cell blocks, for example, 1023 cell blocks, it is preferable that the page buffer 430 is located after their middle point, that is, after the 512th cell block from the top.

Since the page buffer 430 is located at an intermediate point of the plane 400, a plurality of cell blocks configured in the upper region divided by the page buffer 430, that is, the upper memory cell array 410 is close to the page buffer 430. It is preferable that a drain is formed in the part. Similarly, a plurality of cell blocks formed in the lower memory cell array 420 may also have a drain formed near the page buffer 430. In addition, the cell block shares the drain and common source with the adjacent cell block as already described.

As described above, when the page buffer 430 is positioned at an intermediate point of the plane 400, the length of the bit line is 1/2 shorter than that of the conventional art. Thus, the number of drain and drain contacts connected to the bit line is 1 less than that of the conventional art. Reduced to / 2. Therefore, the amount of leakage current can be reduced. In addition, since the memory cell block is operated by dividing the upper and lower parts by the one side pager buffer, the capacitance and the resistance component are also reduced to 1/2.

On the other hand, when the plane is configured as described above, the configuration of the page buffer 430 should be configured slightly different from the existing. The configuration of such a page buffer is shown in FIG.

Referring to FIG. 5, the page buffer according to the present invention includes an upper bit line selector 52 and a lower memory cell connected between the bit lines (even and odd) of the upper memory cell array 51 and the sensing node SO. A lower bit line selector 54 connected between the bit lines (even and odd) of the array 53 and the sensing node SO, a precharge unit 55 connected to the sensing node SO, and a sensing node SO; And a latch 56 connected between the input and output terminals YA. The upper bit line selector 52 and the lower bit line selector 54 may be implemented by a general selection circuit.

The upper bit line selector 52 selects an even bit line Ble or an odd bit line BLo of the upper memory cell array 51 according to the upper select signal during the program, read, and verify operations. Connect to Similarly, the lower bit line selector 53 selects an even bit line Ble or an odd bit line BLo of the lower memory cell array 53 according to the lower select signal during program, read, and verify operations. SO).

The precharge unit 55 precharges the potential of the sensing node SO to a predetermined potential level. In addition, the latch 56 temporarily stores data input through the input / output terminal YA during programming and then transmits the selected data to the selected bit line through the sensing node SO, or stores the cell data loaded on the bit line during a read or verify operation. After temporary storage, it is output through the input / output terminal (YA).

FIG. 6 is a circuit diagram illustrating an embodiment of a page buffer applied to a plane structure of a NAND type flash memory device according to an exemplary embodiment.

Referring to FIG. 6, the upper bit line selector 62 may include a plurality of transistors, and the first and second NMOS transistors N601 and N602 may include the first even and first odd discharge signals DISCH1e and Each of them is driven according to DISCH1o to apply the verify voltage VIRPWR to the memory cell string of the upper memory cell array 61 connected to the even bit line BLe or the odd bit line BLO. The third and fourth NMOS transistors N63 and N64 are driven according to the first even and first odd bit line selection signals BSL1e and BSL1o, respectively, so that the bit lines and the sensing node SO of the upper memory cell array 61 are driven. Connect it.

Like the upper bit line selector 62, the lower bit line selector 64 also includes a plurality of transistors, wherein the fifth and sixth NMOS transistors N65 and N66 are second even and second odd discharges. The verification voltage VIRPWR is applied to the memory cell strings of the lower memory cell array 63 connected to the even bit line BLe or the odd bit line BLo by driving the signals DISCH2e and DISCH2o, respectively. The seventh and eighth NMOS transistors N67 and N68 are driven according to the second even and second odd bit line selection signals BSL2e and BSL2o, respectively, so that the bit lines and the sensing node SO of the lower memory cell array 63 are respectively. Connect it.

The page buffer applied to the plane structure of the NAND type flash memory device of the present invention configured as described above should connect only one memory cell array of the upper memory cell array 61 or the lower memory cell array 63. That is, the page buffer is not connected to the lower memory cell array 63 while the page buffer is connected to the upper memory cell array 61. This operation selects the lower memory cell array 63 while the first discharge signals DISCH1e and DISCH1o or the first bit line selection signals BSL1e and BSL1o for selecting the upper memory cell array 61 are enabled. This is possible because the second discharge signals DISCH2e and DISCH2o or the second bit line selection signals BSL2e and BSL2o are disabled.

In addition, in order to implement a page buffer between the upper memory cell array 61 and the lower memory cell array 63 as described above, the page buffer should not be implemented on the triple P well. Therefore, the upper memory cell array 61 and the lower memory cell array 63 should be implemented on different triple P wells with a page buffer boundary.

As described above, according to the present invention, a page buffer is implemented at an intermediate position of the plane, and the upper and lower memory cell arrays separated by the page buffers are connected to each other so that the length of the bit line is 1/2. As a result, the number of drain and drain contacts connected to the bit lines is reduced by one half. Therefore, the amount of leakage current can be reduced to reduce the page buffer sensing current level, thereby significantly improving the cycling and baking characteristics, which is one of the most important factors for determining the quality of NAND-type flash memory device products. In addition, even if the cell size is reduced, the necessity of controlling the thickness of the tunnel oxide film and the dielectric film for securing the cell current is reduced. In addition, since the page buffer sensitivity is improved, the erase margin and the sensing margin for the program cell are improved. In addition, since the memory cell block is operated by dividing the upper and lower parts by the one side pager buffer, the capacitance and the resistance component are also reduced to 1/2.

Claims (7)

A flash memory device in which a plurality of cells are connected in series to form one cell string, a plurality of the cell strings constitute one cell block, and a plurality of the cell blocks constitute one plane, And the plane is divided into upper and lower memory cell arrays based on a page buffer. The method of claim 1, And the page buffer is a one side page buffer. The memory device of claim 1, wherein the page buffer comprises: an upper bit line selector for selecting the upper memory cell array; And And a lower bit line selector for selecting the lower memory cell array. The method of claim 3, wherein each of the upper bit line selector and the lower bit line selector First and second transistors connected in series between the even bit line and the odd bit line and applying a verify voltage to the even bit line and the odd bit line in response to first and second discharge signals, respectively; And A sensing node connected between the even bit line and the sensing node, between the odd bit line and the sensing node, respectively, selectively detecting the even bit line and the odd bit line in response to first and second bit line selection signals; A flash memory device comprising a third and fourth transistor connected to the. 4. The flash memory device of claim 3, wherein the upper memory cell array and the lower memory cell array are implemented on different wells. A plurality of cells are connected in series to form one cell string, the plurality of cell strings constitute one cell block, the plurality of cell blocks constitute one plane, and the plane is based on a page buffer. In the method of operating a flash memory device divided into upper and lower memory cell array, Executing the program, read, or verify operation of the selected upper memory cell array by enabling the upper bit line selector; And Performing a program, a read operation, or a verify operation of the selected lower memory cell array by enabling the lower bit line selector to be selected; And the lower bit line selector is disabled while the upper bitline selector is enabled, and the upper bitline selector is disabled while the lower bitline selector is enabled. The method of claim 6, And the page buffer is a one side page buffer.

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