KR20070120456A - Pixel array preventing the cross talk between unit pixels and image sensor using the pixel - Google Patents

Abstract

A pixel array having a three-dimensional structure for signal interference between unit pixels is provided to transfer a charge corresponding to an image signal detected by one wafer to another wafer without causing distortion by performing each optimum process on a first wafer for embodying a photodiode and a transfer transistor and a second wafer for embodying transistors for converting an image charge detected by the transfer transistor into an electric signal. A plurality of photodiodes(14) generate charges corresponding to incident image signals. A plurality of transfer transistors respectively transfer the charges generated by the plurality of photodiodes to a corresponding floating diffusion region(15). A plurality of STIs(shallow trench isolations) surround one of the plurality of photodiodes and a transfer transistor connected to the one photodiode. A first super contact(30) is extended from the lower part of the plurality of STIs to the lower surface of the substrate. A second super contact(16) penetrates a partial region of the plurality of STIs and the first super contact. A first wafer includes the abovementioned elements. The charges accumulated in the floating diffusion region are transferred to a second wafer through the second super contact. An insulation material can be filled in the first super contact, composed of a nitride layer or a dual layer of a nitride layer and an oxide layer.

Description

Pixel array preventing the cross talk between unit pixels and Image sensor using the pixel}

1 shows a planar structure of a conventional image sensor.

2 shows a conventional image sensor having a three-dimensional structure.

3 shows a pixel circuit constituting a pixel array having a three-dimensional structure.

4 is a partial cross-sectional view of the first wafer implementing the photodiode and the transfer transistor in the pixel array having a three-dimensional structure according to the present invention.

FIG. 5 is a cross-sectional view of a portion of a second wafer that implements elements other than a photodiode and a transfer transistor in a pixel array having a three-dimensional structure according to the present invention.

6 shows a manufacturing process of an image sensor having a pixel array having a three-dimensional structure according to the present invention.

FIG. 7 shows a top view of the photodiode, transfer transistor and STI shown in FIG. 4.

FIG. 8 illustrates before the super contact is generated during the manufacturing process of the photodiode and the transfer transistor shown in FIG. 4.

FIG. 9 illustrates immediately after a super contact is created after the process of FIG. 8.

10 illustrates a mechanism in which a pixel array according to the present invention prevents signal interference between unit pixels.

11 is a cross-sectional view of an image sensor using a pixel array according to the present invention.

12 is another embodiment of a pixel array having a three-dimensional structure according to the present invention.

The present invention relates to a pixel array and an image sensor, and more particularly to a pixel array having a three-dimensional structure and an image sensor having the pixel array.

In general, an image sensor is known to have a significantly lower manufacturing yield than other products. For example, in order to further improve the dark characteristic, which is the characteristic of reproducing the original image in the dark, among the electrical characteristics representing the performance of the image sensor, not only the optimal circuit but also the application of a special process is required. Incorporation of technical skills is required.

When a special process is introduced to the standard semiconductor process to improve the dark characteristics of the image sensor, the dark characteristics of the image sensor may be improved, but the overall performance of the image sensor may be deteriorated by changing the electrical characteristics of the unit components, especially transistors. It can also act as a disadvantage. Therefore, simply inserting a special process into a standard process can be problematic.

1 shows a planar structure of a conventional image sensor.

Referring to FIG. 1, the image sensor includes a pixel array including a photodiode and a video signal conversion circuit for converting a video signal detected by the photodiode into an electrical signal. Unit), an ADC unit for converting an analog signal into a digital signal, and an amplifier (AMP) unit for amplifying a fine signal.

Referring to FIG. 1, a conventional image sensor is manufactured by applying a standard semiconductor process to a single wafer. The pixel array and other functional blocks (addressing unit, ADC unit, amplifying unit, etc.) forming the characteristics of the image sensor are manufactured. This is implemented simultaneously on one wafer. Therefore, as described above, the image sensor produced through a standard semiconductor process including a special process added to improve the cancer characteristics has a disadvantage in that the yield is lowered due to the problem that the characteristics of various components are changed.

It is believed that the influence of the cancer characteristics of the image sensor is the degree of impact caused by plasma during etching, whether or not sufficient heat treatment is used to alleviate the impact, and various metallic contaminations that may occur during the process. . In order to remedy this problem, introduction of a special process to the standard semiconductor manufacturing process is required.

2 shows a conventional image sensor having a three-dimensional structure.

Referring to FIG. 2, an image sensor having a three-dimensional structure implements a pixel array on one wafer and the other functional blocks on another wafer. Die sorting of chips fabricated on these two different wafers is used to combine them into two layers.

That is, by distinguishing the wafer on which a functional block, which may be used using a standard semiconductor process, and the wafer on which a functional block, on which a special block is to be additionally used, are formed to improve the cancer characteristics, the wafer is formed on a single wafer as in the prior art. The disadvantages of forming all functional blocks can be improved.

Although not shown in FIG. 2, in the pixel array, a plurality of unit pixels are two-dimensionally arranged. Each of the unit pixels includes a unit photodiode and a unit image signal conversion circuit for converting charges generated by the photodiode generated by the image signal into an electrical signal. The photodiode generates charges corresponding to the incident image signal. The larger the area of the photodiode, the wider the variation of the charges generated corresponding to the incident image signal will be. Therefore, the wider the area of the photodiode, the higher the electrical signal conversion capability of the image sensor image signal.

Accordingly, a method of dividing a pixel array implemented in one wafer into two wafers has been proposed.

3 shows a pixel circuit constituting a pixel array having a three-dimensional structure.

Referring to FIG. 3, a pixel circuit includes a photodiode and an image signal conversion circuit for converting an image signal detected by the photodiode into an electrical signal. The video signal conversion circuit includes a transfer transistor Tx, a reset transistor Rx, a conversion transistor Fx, and a selection transistor Sx.

In the case of a pixel array having a three-dimensional structure, a photodiode (PD) and a transfer transistor (Tx) are implemented on one wafer (left portion of the dotted line), and the other three transistors (Rx, Fx, and Sx) are arranged on the other wafer. Implement in (the right part of the dashed line). As described above, the image signal detected by the photodiode implemented on one wafer is transferred to one terminal of the reset transistor Rx implemented on the other wafer and the gate terminal of the conversion transistor Fx via the transfer transistor Tx. Should be.

When the pixel circuit is implemented using two wafers as described above, a problem arises that the charge corresponding to the image signal detected by one wafer must be transferred to the other wafer without being distorted.

In addition, as the area of the photodiode becomes relatively large, an image signal to be introduced into a neighboring photodiode may be incorrectly introduced, and a charge corresponding to the image signal detected from the neighboring photodiode may be incorrectly introduced. The problem of preventing signal interference between unit pixels also occurs.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a pixel array having a three-dimensional structure in which signal interference between unit pixels may be prevented, and charges generated in one wafer may be transferred to another wafer.

Another object of the present invention is to provide a pixel array having a three-dimensional structure in which signal interference between unit pixels can be prevented and charges generated in one wafer can be transferred to another wafer. To provide a sensor.

The pixel array having a three-dimensional structure according to the present invention for achieving the above technical problem, is implemented by dividing the photodiode, transfer transistor, reset transistor, conversion transistor and the selection transistor to the first wafer and the second wafer, respectively, and the first wafer And a three-dimensional structure that connects the chip implemented in the second wafer up and down. The first wafer includes a plurality of photodiodes for generating charges corresponding to an incident image signal, a plurality of transfer transistors for transferring charges generated from the plurality of photodiodes to a corresponding floating diffusion region, and the plurality of photodiodes. A first super contact extending from the bottom of the plurality of STIs to a lower surface of the wafer, the plurality of STIs each surrounding one of the photodiodes and one transfer transistor connected to the one photodiode; ) And a second super contact penetrating through a plurality of STIs and partial regions of the first super contact, wherein charges accumulated in the floating diffusion region are transferred to the second wafer through the second super contact. Is delivered to.

According to another aspect of the present invention, an image sensor includes a pixel array, a plurality of color filters, and a plurality of micro lenses.

The pixel array may include a chip obtained by dividing a photodiode, a transfer transistor, a reset transistor, a conversion transistor, and a selection transistor on a first wafer and a second wafer, respectively, and die sorting the first wafer and the second wafer. It has a three-dimensional structure that is connected up and down. The plurality of color filters are installed on the pixel array. The plurality of micro lenses is installed on the plurality of color filters.

The first wafer includes a plurality of photodiodes for generating charges corresponding to an incident image signal, a plurality of transfer transistors for transferring charges generated from the plurality of photodiodes to a corresponding floating diffusion region, and the plurality of photodiodes. A plurality of STIs each surrounding one of the photodiodes and one transfer transistor connected to the one photodiode, a first super contact extending from the bottom of the plurality of STIs to the bottom surface of the wafer And a second super contact penetrating the plurality of STI rings and a partial region of the first super contact. The second wafer includes a plurality of reset transistors, a plurality of conversion transistors, and a plurality of selection transistors for converting charges transferred through the second super contact into an electrical signal.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a partial cross-sectional view of the first wafer implementing the photodiode and the transfer transistor in the pixel array having a three-dimensional structure according to the present invention.

Referring to FIG. 4, the photodiode 14 and the transfer transistor Tx are installed in a circled area surrounded by a shallow trench insulator (STI), and a first super contact 30 is formed below the STI. do. The first super contact 30 is installed to prevent signal interference between unit pixels. Like the STI, the first super contact 30 surrounds a space in which the photodiode 14 and the transfer transistor Tx are formed. It may also be called the ring 30. The first super contact 30 penetrates from the STI to the bottom of the first wafer and fills the insulating material. In some cases, it is possible to be filled with the same insulating material as the STI. A second super contact 1 is formed in a portion of the first super contact 30. The second super contact 16 is a charge transfer path 16 through which the charges accumulated in the floating diffusion regions 15 and FD are transferred to the second wafer via the metal line M1, and the second super contact. In other words, the charge transfer path 16 penetrates to the bottom surface of the first wafer. At the end of the charge transfer passage 16, a micro bumper 17, which serves as a buffer when combined with a second wafer to be described later, is installed.

A photodiode, a transfer transistor, an STI, and a super contact implemented in the first wafer illustrated in FIG. 4 will be described later in more detail.

FIG. 5 is a cross-sectional view of a portion of a second wafer that implements elements other than a photodiode and a transfer transistor in a pixel array having a three-dimensional structure according to the present invention.

Referring to FIG. 5, the second wafer is provided with a reset transistor Rx, a conversion transistor Fx, and a selection transistor Sx. The conductor 18 at the top of the figure is joined to the bumper 17 shown in FIG. 4. Accordingly, the charges accumulated in the floating diffusion regions 15 and FD of the first wafer are transferred to the one terminal of the reset transistor Rx and the conversion transistor via the charge transfer path 16, the bumper 17, and the conductor 18. Are delivered to the gate terminals of Fx).

Hereinafter, a process of actually implementing the two wafers shown in FIGS. 4 and 5 will be described. In general, an image sensor is implemented by stacking a color filter and a micro lens on top of a pixel array. Therefore, in order to implement an image sensor, a pixel array must be manufactured first. In the following, the above contents are mixed and explained.

6 shows a manufacturing process of an image sensor having a pixel array having a three-dimensional structure according to the present invention.

Referring to Figure 6, the manufacturing process 600 of the image sensor,

Forming a first wafer having a photodiode and a transfer transistor (S110);

-Polishing the first wafer back surface (S120),

Forming a first super contact penetrating the first wafer (S130),

Forming a micro bumper on one side of the first super contact (S140),

Forming a second wafer including the remaining transistors other than the photodiode and the transfer transistor in the pixel circuit (S150);

A wafer arrangement step (S160) of arranging the first wafer and the second wafer up and down;

-Bonding the electrodes of the first wafer and the electrodes of the second wafer corresponding to the electrodes of the first wafer (S170) and

Forming a color filter on the first wafer (S180);

In some cases, after forming the first super contact (S130) and before forming the micro bumper (S140), a step of forming a second super contact (S135) may be added. In addition, a step (S155) of grinding the back surface of the second wafer may be added between the forming of the second wafer (S150) and the wafer arranging step (S160).

Each of the above steps will be described in more detail.

In the first wafer forming step S110, a photodiode 14, a transfer transistor Tx, a floating diffusion region FD, and a metal line M1 are formed on the front surface of the first wafer using a semiconductor process.

In this case, the process applied to the first wafer can be applied to the purpose of improving the sensor unique characteristics such as cancer characteristics and sensitivity, and furthermore, to apply a specialized process to meet the special characteristics requirements of the orderer.

In the first wafer rear surface polishing step S120, the back side is polished to have a thickness of 30 μm or less through a grinding process or a chemical mechanical polishing (CMP) process. The polished surface is treated using an etching process. In this case, the first wafer back surface polishing step S120 may be performed by bonding glass or another silicon wafer to the front surface of the first wafer according to a specific use or situation.

In the first super contact forming step (S130), a buried interconnection process or a super contact process is performed as a basic process for bonding the wafer, and an alignment key is formed on the back surface of the polished first wafer. The first super contact is formed on the rear surface of the first wafer by photo etching and tungsten plug (W-PLUG).

In some cases, after the first super contact forming step (S130), a nitride film (SiN) is deposited on the back surface of the first wafer or a nitride layer and a silicon oxide (SiO 2) bilayer are deposited in order to improve the cancer characteristics of the image sensor. A second super contact may be additionally formed along the periphery of the photodiode by the CMP process (S135).

In the micro bumper forming step S140, the micro bumper is formed on the surface of the first super contact formed in the first super contact forming step S130 through a micro bumper process.

In the second wafer forming step S150, a reset transistor Rx, a conversion transistor Fx, and a selection transistor Sx are installed on the entire surface of the second wafer using a semiconductor process. In some cases, a step (S155) of grinding the back surface of the second wafer may be added.

In the wafer arranging step S160, the first wafer and the second wafer are arranged up and down so that the micro bumper 17 portion of the first wafer and the conductor 18 of the second wafer are coupled to each other. In the method of arranging the first wafer and the second wafer up and down, the first wafer and the second wafer are arranged vertically by penetrating a specific portion of the first wafer through infrared ray transmission, etching, and laser punching. Infrared (IR) transmission can be arranged without a hole in the wafer, and the etching and laser punching method is arranged up and down through the optical pattern recognition by drilling a hole in the wafer.

In the wafer bonding step S170, the micro bumper 17 portion of the first wafer and the conductor 18 of the second wafer are bonded.

In the color forming step (S180), the color filter and the microlens are stacked in order on the first wafer.

In the first wafer forming step S110, 0.18 μm or 90 nm process technology may be used for the epitaxially grown wafer, and in the second wafer forming step S150, 0.25 μm or 0.35 μm process is performed for the silicon wafer. Technology can be used.

The special process proposed in the present invention is the first super contact and the second super contact process. Hereinafter, how the first super contact and the second super contact are used will be described.

FIG. 7 shows a top view of the photodiode, transfer transistor and STI shown in FIG. 4.

Referring to FIG. 7, a transfer transistor Tx is formed at one corner of a rectangular photo diode, and a metal line M1 is formed on the floating diffusion region FD (not shown). The photodiode and transfer transistor are surrounded by STIs. In the drawing, the STI is shown as surrounding all the slopes of the unit pixel region, but some surfaces or surfaces may be opened.

FIG. 8 illustrates before the super contact is generated during the manufacturing process of the photodiode and the transfer transistor shown in FIG. 4.

FIG. 8 is a cross-sectional view of the photodiode and the transfer transistor along the A-B line shown in FIG. 7, before the super contact is still formed in the STI. Referring to FIG. 8, a charge e generated in an arbitrary unit pixel surrounded by an STI by an image signal may be transferred to a neighboring unit pixel beyond the STI. In this case, signal interference between unit pixels occurs. One of the core ideas of the present invention is to form a first super contact to prevent signal interference between such unit pixels.

FIG. 9 illustrates immediately after a super contact is created after the process of FIG. 8.

The first super contact 30 is formed to the end of the wafer toward the bottom of the STI shown in FIG. 8, and FIG. 9 reverses the top and bottom of the wafer shown in FIG. 8. In this case, a second super contact 16 is formed at a predetermined portion of the first super contact, that is, overlapping with the metal M1 formed on the floating diffusion region, and the second super contact 16 is formed of the metal ( It is filled with the same conductive material or conductive material as M1). The second super contact 16 is used as the charge transfer path 16.

In the conventional case, the via contact formed in a portion of the photodiode is used as the charge transfer path 16, which is a reason for reducing the area of the photodiode. However, in the pixel array according to the present invention, the area of the photodiode is relatively increased as the pixel array is installed in a portion of the first super contact 30. Therefore, it is clear that an image sensor using a pixel array having an increased area of the photodiode will have improved dark characteristics.

Referring to FIG. 9, where the second super contact 16 is formed is indicated by B. Referring to FIG. 8, it can be seen that it is near the floating diffusion region adjacent to the transfer transistor Tx.

10 is a cross-sectional view of a pixel array according to the present invention.

Referring to FIG. 10, a pixel array is arranged on top of a chip sorted from a first wafer on which a photodiode and a transfer transistor are implemented, from a second wafer including transistors other than a transfer transistor in an image signal conversion circuit. It can implement by laminating | stacking. At this time, the two chips are electrically connected to each other through the conductor electrode.

11 is a cross-sectional view of an image sensor using a pixel array according to the present invention.

Referring to FIG. 11, an image sensor according to the present invention is implemented by stacking a color filter and a micro lens on an upper portion of a pixel array according to the present invention illustrated in FIG. 10, ie, on a chip obtained by die sorting a first wafer.

In the above description, the unit photodiode and the transfer transistor implemented in the first wafer and the reset transistor, the conversion transistor, and the selection transistor corresponding to those implemented in the second wafer have been described. However, a pixel array and an image sensor having a three-dimensional structure according to the present invention include at least two photodiodes in which a reset transistor, a conversion transistor, and a selection transistor implemented in a second wafer are implemented in a first wafer, and two transfer transistors corresponding thereto. The same may be applied to a structure in which they are shared.

12 is another embodiment of a pixel array having a three-dimensional structure according to the present invention.

Referring to FIG. 12, two photodiodes PD0 and PD1 implemented in the first wafer and two transfer transistors Tx0 and Tx1 connected to the first wafer are respectively configured in one reset transistor Rx implemented in the second wafer. In this case, one conversion transistor Fx and one selection transistor Sx are commonly used.

In this case, since the number of transistors to be implemented in the second wafer is reduced, there is an advantage in that the second wafer has room to additionally install other functional blocks.

As described above, the pixel array having the three-dimensional structure and the image sensor including the pixel array according to the present invention can cope with the demand for adding various functions of the consumer without increasing the total chip area, Due to the ease of incorporation of specialized processes that can improve the properties, it is easy to manufacture high-performance products. In addition, an optimal process can be applied to the first wafer to implement the photodiode and the transfer transistor and the second wafer to implement the transistors to convert the image charges detected through the transfer transistor into electrical signals. have.

Claims (7)

A three-dimensional structure using photodiodes, transfer transistors, reset transistors, conversion transistors, and selection transistors divided into a first wafer and a second wafer, respectively, and connecting chips implemented in the first wafer and the second wafer up and down. In a pixel array having In the first wafer, A plurality of photodiodes for generating charges corresponding to an incident image signal; A plurality of transfer transistors respectively transferring charges generated by the plurality of photodiodes to a corresponding floating diffusion region; A plurality of STIs each surrounding one photodiode of the plurality of photodiodes and one transfer transistor connected to the one photodiode; A first super contact extending from a bottom of the plurality of STIs to a bottom surface of a wafer; And A second super contact penetrating a plurality of regions of the STI and the first super contact; The charges accumulated in the floating diffusion region are transferred to the second wafer through the second super contact, the pixel array having a three-dimensional structure. The method of claim 1, wherein the first super contact, Pixel array having a three-dimensional structure characterized in that the insulating material is filled. The method of claim 2, wherein the insulating material, The pixel array having a three-dimensional structure, characterized in that the same as the insulating material constituting the STI. The method of claim 2, wherein the insulating material, A pixel array having a three-dimensional structure, which is a double layer of a nitride film, a nitride film, and an oxide film. The method of claim 1, wherein the second super contact, Pixel array having a three-dimensional structure characterized in that the conductive material is filled. The method of claim 5, wherein the conductive material, The pixel array having a three-dimensional structure, characterized in that the same material as the metal line formed in the floating diffusion region. A photodiode, a transfer transistor, a reset transistor, a conversion transistor, and a selection transistor are separately installed on the first wafer and the second wafer, and the chips obtained by die sorting the first wafer and the second wafer are connected up and down. A pixel array having a three-dimensional structure; A plurality of color filters installed on the pixel array; And It has a micro lens installed on the plurality of color filters, The first wafer, A plurality of photodiodes for generating charges corresponding to incident image signals; A plurality of transfer transistors respectively transferring charges generated by the plurality of photodiodes to a corresponding floating diffusion region; A plurality of STIs each surrounding one photodiode of the plurality of photodiodes and one transfer transistor connected to the one photodiode; A first super contact extending from a bottom of the plurality of STIs to a bottom surface of a wafer; And A second super contact penetrating the plurality of STI rings and a partial region of the first super contact; The second wafer, And a plurality of reset transistors, a plurality of conversion transistors, and a plurality of selection transistors for converting charges transferred through the second super contact into an electrical signal.

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