KR20070118920A - Digital processing apparatus having shared memory and method for accessing to partitioned area in shared memory - Google Patents

Abstract

A digital processing device equipped with a shared memory and a method for accessing a partitioned area of the shared memory are provided to minimize a data transfer time and optimize an operation speed of each controller by assigning a dedicated area to a plurality of processors combined to the shared memory. A memory(310) is divided into a plurality of partitioned areas, and is equipped with a first and a second ports. An MP(Main Processor)(210) is combined with the first port through an MP-SM(Shared Memory) bus, writes raw data by connecting to one partitioned area through the MP-SM bus, and outputs a processing command for the raw data through an MP-AP(Application Processor) bus. An AP(220) is combined with the second port through the AP-SM bus, is combined with the MP through the MP-AP bus, and reads/processes the raw data stored in the partitioned area through the AP-SM bus by corresponding to the received processing command. The AP reads the raw data stored in the partitioned area by using storage position or default storage position whether the storage position of the raw data is received from the MP through the MP-AP bus.

Description

Digital processing apparatus having shared memory and method for accessing to partitioned area in shared memory

1 is a block diagram of a mobile communication terminal having a conventional camera function.

2 is a diagram illustrating a coupling structure between a conventional main controller, an additional controller, and respective memories;

3 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating a method for varying a size of a partitioned storage area according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to another exemplary embodiment of the present invention.

7 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to an exemplary embodiment of the present invention.

8 is a diagram illustrating a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention.

9 is a flowchart illustrating a process of accessing a divided storage area by an arbitrary control unit according to an exemplary embodiment of the present invention.

10 is a diagram illustrating a divided state of a storage area of a memory unit according to another exemplary embodiment of the present invention.

11 is a view illustrating a coupling structure between a main controller, an additional controller, a memory unit, and a display device according to an exemplary embodiment of the present invention.

12 is a diagram illustrating a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention.

FIG. 13 is a data flow diagram illustrating a sequential connection and processing procedure of a control unit according to access authority control for a divided storage area according to an exemplary embodiment of the present invention. FIG.

14-16 illustrate a conventional memory sharing structure.

FIG. 17 is a flowchart illustrating a data writing method using another memory in the memory sharing structure of FIG. 16. FIG.

Figure 18 illustrates a memory sharing structure in accordance with one preferred embodiment of the present invention.

FIG. 19 illustrates a process of storing processing data of a main controller in a memory dependent on an additional controller in a non-driven state according to an exemplary embodiment of the present invention; FIG.

20 is a diagram illustrating a process of storing, by a second additional control unit, processing data in a memory that is dependent on a first additional control unit in a non-driven state according to another exemplary embodiment of the present invention.

Fig. 21 is a diagram showing the configuration of a device in which a plurality of conventional memories are used.

22 is a schematic block diagram of a conventional additional control unit.

FIG. 23 schematically illustrates a configuration of an apparatus combined with a plurality of memories according to an exemplary embodiment of the present invention. FIG.

24 is a schematic block diagram of an additional controller according to an exemplary embodiment of the present invention.

FIG. 25 illustrates pin usage (pin muxing tables) of a memory interface in accordance with one preferred embodiment of the present invention. FIG.

The present invention relates to a digital processing device, and more particularly, to a digital processing device having a plurality of processors.

The portable terminal of the digital processing device is an electronic device that is formed in a small size in order to perform a function such as a game or a mobile communication, so that the user can easily carry it. The portable terminal may include a mobile communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), and the like.

Among them, a mobile communication terminal is essentially a device implemented so that a mobile user can make a telephone call with a remote receiver. However, due to the development of science and technology, recent mobile communication terminals have additional functions such as a camera function and a multimedia data reproduction function in addition to the essential functions such as a telephone call function, a short message transmission and reception function, and an address book management function.

1 is a block diagram of a mobile communication terminal having a conventional camera function.

Referring to FIG. 1, the mobile communication terminal 100 having a camera function includes a high frequency processor 110, an A / D converter 115, a D / A converter 120, a controller 125, and a power supply 130. ), A key input unit 135, a main memory 140, a display unit 145, a camera 150, an image processing unit 155, and an auxiliary memory 160.

The high frequency processor 110 processes the high frequency signal received through the antenna or transmitted through the antenna.

The A / D converter 115 converts an analog signal output from the high frequency processor 110 into a digital signal and transmits the analog signal to the controller 125.

The D / A converter 120 converts the digital signal output from the controller 125 into an analog signal and transmits the analog signal to the high frequency processor 110.

The controller 125 controls the overall operation of the mobile communication terminal 100. The controller 125 may include a central processing unit (CPU) or a micro-controller.

The power supply unit 130 is a means for supplying power required for the mobile communication terminal 100 to operate. The power supply unit 130 may be combined with an external power source or a battery.

The key input unit 135 generates key data for performing various function setting, dialing, etc. of the mobile communication terminal 100 and transmits the generated key data to the controller 125.

The main memory 140 stores an operation program, various data, and the like of the mobile communication terminal 100. The main memory 140 may be configured as a flash memory or an electrically erasable programmable read only memory (EEPROM).

The display unit 145 displays an operation state of the mobile communication terminal 100 and an external image captured by the camera 150.

The camera 150 captures an external image (subject), and the image processor 155 processes the captured image by the camera 150.

The image processor 155 performs functions such as color interpolation, gamma correction, image quality correction, JPEG encoding, and the like.

The auxiliary memory 160 stores an external image processed by the image processor 155.

As described above, the mobile communication terminal 100 having a camera function includes a plurality of processors (that is, a main processor and one or more application processors for performing additional functions). Here, the operation of the application processor may be controlled by the main processor. That is, as shown in FIG. 1, a controller 125 for controlling the overall function of the mobile communication terminal 100 and an image processor 155 for controlling the camera function are included. In addition, each processor is configured to be coupled to a separate memory, respectively. In the present specification, the main processor, the main controller, the application processor, and the additional controller will be used interchangeably.

The type of application processors may differ depending on what additional functions are equipped in the portable terminal. For example, an application processor for performing a camera function may perform a function such as JPEG encoding or JPEG decoding, and an application processor for performing a video playback function may include a video file (eg, MPEG4). , DIVX, and H.264) may be encoded and decoded, and an application processor for performing a music file reproduction function may perform encoding and decoding of a music file. Of course, there may also be an application processor that can integrally perform the various functions described above. Each of these controllers individually has a memory for storing data processed by the controller. Therefore, according to the related art, as the function of the portable terminal becomes more multifunctional, there is a problem that the quantity of the controller and the quantity of the memory must also increase.

2 is a diagram illustrating a coupling structure between a conventional main controller, an additional controller, and respective memories.

Referring to FIG. 2, the main controller 210 and the additional controller 220 transmit and receive information through the bus BUS 1, and the main controller 210 is coupled through the main memory 230 and the bus 2. The additional control unit 220 and the additional memory 240 are coupled through the bus 3. The bus refers to a common purpose electrical passage used to transmit information between a controller, a main memory, and an input / output device in a computer. The bus includes a line for information indicating the address of each device or the location of the storage device and a line for distinguishing various data transfer operations to be performed.

As shown in FIG. 2, each of the controllers 210 and 220 is independently coupled to each of the memories 230 and 240, so that the main controller 210 may change the main memory 230 according to what is being performed. ) To read the data stored in the additional memory 220 to the additional control unit 220 through the host interface or to request the additional control unit 220 to read the data stored in the additional memory 240.

In this case, as the amount of data transmitted and received between the main control unit 210 and the additional control unit 220 increases, each control unit 210 or 220 operates according to a request of the other control unit rather than its own process (ie, memory access, host interface operation, etc.). The problem is that more time is spent).

The above-described problem has a problem of causing bottlenecks in data transmission and reception between the main control unit 210 and the additional control unit 220 as the functions performed in the portable terminal increase and the amount of data to be processed increases.

As a result, the above-described problems are a cause of weakening the overall performance of the multifunctional portable terminal.

Accordingly, an object of the present invention for solving the above problems is to allocate a dedicated area to each of the plurality of controllers coupled to the shared memory, thereby minimizing data transfer time, and sharing to optimize the operation speed of each controller. A digital processing apparatus having a memory and a method of accessing a partition of a shared memory are provided.

Another object of the present invention is to provide a digital processing apparatus having a shared memory capable of optimal memory partitioning by allocating a storage area of the memory as a shared area and a dedicated area for each of the controllers, and a method of accessing a partitioned area of the shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory that facilitates sharing of necessary data by sharing a single memory with a plurality of controllers, and a method of accessing a partition of the shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory capable of processing data with high efficiency by eliminating unnecessary time loss of data stored in a specific memory between control units and a method of accessing a partition of the shared memory. To provide.

It is still another object of the present invention to divide a storage area of a shared memory into a plurality of partitions and to allow access of a plurality of controllers to each partition, thereby enabling digital processing having a shared memory capable of minimizing data transfer time between the controllers. A method of accessing a partition of a device and a shared memory is provided.

It is still another object of the present invention to enable a plurality of controllers to access a storage area of a shared memory divided into a plurality of regions, so that each controller can be in charge of its own process to optimize the operation speed and efficiency of each controller. A digital processing apparatus having a shared memory and a partition access method of the shared memory are provided.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory and a method for accessing a shared memory having a shared memory, which can easily control the shared memory in software by dividing and using the shared memory.

It is still another object of the present invention to provide a digital processing having a shared memory in which a plurality of controllers can access and access a divided storage area of a shared memory in a manner that data can be immediately transferred by transfer of only access authority. A method of accessing a partition of a device and a shared memory is provided.

It is still another object of the present invention to generate and output state information (i.e., occupied state information) for a storage area in which a shared memory is partitioned, and have a digital memory having a shared memory capable of simplifying the control sequence of each controller as much as possible. A method of accessing a partition of a processing device and a shared memory is provided.

Still another object of the present invention is that the main controller sequentially writes arbitrary data to the divided storage area of the shared memory, and the additional controller sequentially accesses the storage area recorded by the main controller to read the data. The present invention provides a digital processing apparatus having a shared memory and a partition access method of the shared memory capable of maximizing data transfer speed by performing an operation.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory capable of controlling operations of a plurality of additional controllers by a main controller having a simple configuration, and a method of accessing a partition of the shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory capable of optimizing the processing efficiency of the main memory by performing no or minimizing bus control function by the main memory and a method of accessing a partition of the shared memory.

It is still another object of the present invention to provide a shared memory capable of minimizing unnecessary power consumption by eliminating unnecessary processing operations for storing data generated or requested by another additional control unit in a memory in which the additional control unit which is not driven is dependent. The present invention provides a method for accessing a partition of a digital processing device and a shared memory.

Still another object of the present invention is to provide a digital processing apparatus having a shared memory capable of minimizing processing time due to data storage by omitting the processing operation of another additional control unit when storing data to be stored in a memory dependent on the other additional control unit; It is to provide a partition access method of shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory capable of maximizing the available memory size available to each controller and a method of accessing a partition of the shared memory.

It is still another object of the present invention to provide a digital processing device having a shared memory to which bypass logic is applied, which is much simpler than a conventional bus control logic, and a method of accessing a partition of the shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory and a method of accessing a partition of the shared memory, which can simplify the memory interface structure to be combined with a plurality of memories as much as possible.

Another object of the present invention is to increase the efficiency of the additional control unit by minimizing the number of pins included in the memory interface, and also to the digital processing apparatus having a shared memory capable of reducing the operating current for driving the additional control unit. It is to provide a partition access method of shared memory.

It is still another object of the present invention to provide a digital processing apparatus having a shared memory capable of lowering the price of an additional control unit by simplifying a memory interface structure that can be integrated into a plurality of memories, and a method of accessing a partition of the shared memory. will be.

Another object of the present invention is to solve the problem of having to pull out the pin for a function that is not always used, by opening only the path of the interface to be used by sharing the memory interface to operate only the logic corresponding thereto A digital processing apparatus having a shared memory capable of more efficient operation and a method of accessing a partition of the shared memory are provided.

Other objects of the present invention will be readily understood through the following description.

In order to achieve the above objects, according to one aspect of the present invention, a digital processing device is provided.

A portable terminal according to an embodiment of the present invention comprises a memory unit; Combined through the memory unit and an AP (Shared Memory) bus (BUS), the raw data stored in the memory unit accessed through the AP-SM bus is processed to correspond to a processing instruction. An additional control unit for storing the information; And a main control unit coupled to the memory unit through a Main Processor (MP) -SM bus, and coupled to the additional control unit through an MP-AP bus to transmit the processing command to the additional control unit through the MP-AP bus. Include. The storage area of the memory unit may be divided into a first dedicated area accessible only by the additional control unit, a second dedicated area accessible only by the main control unit, a common area accessible by the additional control unit and the main control unit, and a variable area. The variable area may be variably changed to be included in at least one of the first dedicated area, the second dedicated area, and the common area to correspond to area division information generated by one of the main control unit and the additional control unit. Can be.

The memory unit may have an independent interface structure for transmitting and receiving information with the additional control unit through the AP-SM bus and transmitting and receiving information with the main control unit through the MP-SM bus.

The first control unit generates the area partitioning information and transmits the divided information to the second control unit through the MP-AP bus, wherein the first control unit is either the main control unit or the additional control unit, and the second control unit is the main control unit. Alternatively, the additional control unit may be another one.

The first control unit accessing the common area generates area repartitioning information when the size of data to be recorded is greater than the size of a recordable capacity of the common area, and generates the first dedicated area by the area repartitioning information. Some or all of the variable regions included in at least one of the second dedicated regions may be included as the common region, thereby expanding the size of the common region.

The MP-SM bus may have priority among the AP-SM bus and the MP-SM bus.

The processing instruction may include instruction information on a processing type of the raw data and a storage location of the raw data. The processing instruction may further include location information for storing the raw data processed to correspond to the indication information.

According to another preferred embodiment of the present invention, a digital processing device includes a memory unit; An additional control unit coupled to the memory unit through an AP-SM bus and processing and storing raw data stored in the memory unit connected through the AP-SM bus according to a processing command; And the processing command coupled to the memory unit through an MP-SM bus, and coupled to the additional control unit through an MP-AP bus to indicate instruction information about a processing type of the raw data and a storage location of the raw data. It may include a main control unit for transmitting to the additional control unit via the MP-AP bus. Here, the storage area of the memory unit is divided into a plurality of divided storage areas accessible by the additional control unit via the AP-SM bus, and accessible by the main control unit via the MP-SM bus, and the memory unit is A first port for transmitting and receiving information to and from the additional control unit through an AP-SM bus and a second port for transmitting and receiving information to and from the main control unit through the MP-SM bus may be provided.

When either the main controller or the additional controller accesses any one of the divided storage areas, the access state information may be transmitted to the other of the main controller or the additional controller through the MP-AP bus.

The area partitioning information corresponding to the size of the divided storage areas may be set by either the main controller or the additional controller and transferred to the other of the main controller or the additional controller via the MP-AP bus. .

The processing instruction may further include location information for storing the raw data processed to correspond to the indication information.

The plurality of divided storage areas may include a data transfer area for transferring data between the additional control unit and the main control unit.

According to still another aspect of the present invention, there is provided a digital processing apparatus comprising: a memory unit having a first port and a second port divided into a plurality of divided storage regions; Coupled to the first port through an MP-SM bus, connected to any one of the divided storage areas through the MP-SM bus to record raw data, and then outputs a processing command of the raw data through an MP-AP bus. A main control unit; And the AP-SM bus coupled to the second port through an AP-SM bus, coupled to the main controller via the MP-AP bus, and corresponding to the processing command received through the MP-AP bus. An additional control unit may be configured to read and process the raw data recorded in the divided storage area of the memory unit through the read unit. Here, each of the divided storage areas may be accessed by the additional controller through the AP-SM bus, the main controller may be connected through the MP-SM bus, and the additional controller may be connected to the MP-AP bus. The raw data recorded in the divided storage area may be read using the storage location information or storage location information set as a default according to whether storage location information on which the raw data is recorded is received from the main controller. .

At least one of the plurality of divided storage areas may be a data transfer area for transferring data between the additional control unit and the main control unit, and the raw data may be recorded in the data transfer area.

The processing instruction may include instruction information on a processing type of the raw data and the storage location information. The apparatus may further include location information for storing the raw data processed to correspond to the indication information.

When either the main controller or the additional controller accesses any one of the divided storage areas, the access state information may be transmitted to the other of the main controller or the additional controller through the MP-AP bus.

The area partitioning information corresponding to the size of the divided storage areas may be set by either the main controller or the additional controller and transferred to the other of the main controller or the additional controller via the MP-AP bus. .

According to another preferred embodiment of the present invention, a digital processing device includes an output device; a memory unit including m (any natural number of 2 to n (natural numbers of two or more)) divided storage areas; The output unit is coupled to the memory unit through an AP-SM bus, reads raw data recorded in an arbitrary divided storage area accessed through the AP-SM bus, processes the data corresponding to a processing instruction, and then outputs the output device. An additional control unit to be output through; And the additional control unit coupled to the additional control unit through the MP-AP bus to transmit the processing command to the additional control unit through the MP-AP bus, and coupled to the memory unit and the MP-SM bus to divide and store the raw data. It may include a main control unit for recording in the area. The memory unit may generate connection state information of the additional controller or the main controller of the divided storage area and transmit the generated state information to the additional controller and the main controller.

The additional control unit reads the raw data by accessing the divided storage area where the main control unit releases the connection after recording the raw data with reference to the connection state information.

The memory unit may include a first port for transmitting and receiving a control signal and the raw data to and from the additional controller through the AP-SM bus, and a source for transmitting and receiving the control signal and the raw data to and from the main controller through the MP-SM bus. It can have two ports.

The additional control unit and the main control unit may not be simultaneously connected to one divided storage area by the connection state information.

Area division information corresponding to the size or quantity of the divided storage areas is set by a first control unit which is either the main control unit or the additional control unit, and the other of the main control unit or the additional control unit via the second bus. It may be delivered to the second control unit.

The access state information may be information about a writeable state and a readable state corresponding to the divided storage area.

According to still another aspect of the present invention, there is provided a digital processing apparatus, comprising: an additional controller configured to perform a preset additional function, wherein the additional function includes at least one of a camera function and a multimedia data reproduction function; An additional memory unit coupled or inserted to be slaved to the additional control unit; And a main control unit coupled to the additional control unit to control driving start or driving termination of the additional control unit. Here, when the additional control unit does not occupy a bus corresponding to the additional memory, the additional control unit may switch a route so that the main control unit and the additional memory unit are directly coupled.

When the additional control unit does not occupy a bus corresponding to the additional memory, when the additional control unit enters a non-driven state, and when the additional control unit is in a driving state but does not use the additional memory. It may be at least one of.

The additional control unit includes bypass logic to switch the path, and the bypass logic is performed immediately after the additional control unit enters a non-driven state. The additional control unit may transmit corresponding state information to the main control unit.

The additional control unit includes bypass logic to switch the path, and the bypass logic detects that the additional control unit has entered a non-driven state by controlling the driving termination. It may be performed by a command from the main controller.

The main controller may write the processed or processed data to the additional memory through the path.

An additional processor of the digital processing apparatus according to another preferred embodiment of the present invention, wherein the digital processing apparatus includes a main processor and an additional processor that performs a preset additional function controlled by the main processor and is coupled to a plurality of memories. A processing unit which performs the preset additional function; A path controller configured to set an information transmission / reception path with any one of a first memory and a second memory coupled through a shared memory interface under the control of the processing unit; A first memory controller configured to transmit and receive information to and from the first memory through a first memory interface and the path controller; And a second memory controller configured to transmit and receive information to and from the second memory through a second memory interface and the path controller. Here, when the total number of pins for the interface with the first memory is n (natural number), and the total number of pins for the interface with the second memory is m (natural number greater than n), the shared memory interface May include k (natural numbers) pins, any one of 1 to n−1, the first memory interface may include nk pins, and the second memory interface may include mk pins.

A bus controller may be further configured to perform bus control under the control of the processing unit, and the path controller may set the information transmission / reception path by a path control signal received from the bus controller.

The additional processor may include one or more pins for transmitting at least one of a clock (CLK) signal and a chip select (CS) signal.

The first memory may be any one of an internal memory and a removable memory, and the second memory may be another one of the internal memory and the removable memory.

The removable memory may be any one of a Secure Digital (SD) card, a Compact Flash (CF) memory card, an eXtreme Digital Picture Card (XD), a Memory Stick (MS), and a Multi-Media Card (MMC).

In order to achieve the above objects, according to one aspect of the present invention, there is provided a recording medium in which a memory access method or / and a program for performing the method is recorded.

According to a preferred embodiment of the present invention, a memory unit, a main control unit coupled to the memory unit via an MP-SM bus, and the memory unit is coupled via an AP-SM bus and connected to the main control unit via an MP-AP bus. In the digital processing apparatus including a combined additional control unit, in the method of varying the size of the partition area of the memory unit, the main control unit by setting the area partitioning information for dividing the storage area of the memory unit into a plurality of partition areas; Transmitting to the additional control unit, wherein the divided area includes at least a first dedicated area accessible only by the main control unit, a second dedicated area accessible only by the additional control unit, accessible by the main control unit and the additional main control unit And a common area and a variable area, wherein the variable area includes the first area based on the area partitioning information. Configured to be included in at least one of a dedicated area, the second dedicated area, and the shared area; Accessing the common area by the main controller to record arbitrary data; Determining, by the main controller, whether the size of data to be recorded is equal to or less than a size of a recordable area of the common area; And in case of abnormality, providing a method of changing a size of a divided region of a memory unit including generating, by the main controller, region repartitioning information and transmitting the generated region repartition information to the additional controller. In this case, the variable area may include some or all of the variable areas included in at least one of the first dedicated area and the second dedicated area as the common area, thereby expanding the size of the common area.

The method of changing a divided area size of the memory unit may include: accessing the common area by the additional control unit to record arbitrary data; Determining, by the additional control unit, whether a size of data to be recorded is equal to or less than a size of a recordable area of the common area; And in case of abnormality, the additional control unit may transmit a region repartition request to the main control unit. Here, the main controller may generate the area repartition information in response to the area repartition request, and the size of the common area may be extended by the area repartition information.

Any one of the main controller and the additional controller accessed in the common area may transmit connection state information to the other of the main controller and the additional controller through the MP-AP bus.

According to another preferred embodiment of the present invention, a program of instructions, which can be executed by the digital processing apparatus for performing the multiple access control method of the partition of the shared memory, is tangibly implemented and read by the digital processing apparatus. In the recording medium for recording a program capable of-wherein the digital processing device includes a main control unit and an additional control unit, the main control unit is coupled to the memory unit via the MP-SM bus, the additional control unit is the AP-SM bus The main control unit and the additional control unit are coupled through an MP-AP bus, and a storage area of the memory unit is divided into a plurality of divided storage areas; In order for the first control unit, which is either to access the divided storage area, Determining whether or not said main control unit or the other one of the second control unit of the sub-control unit is already accessed to the partitioned storage area; Accessing the partitioned storage area by the first controller when the second controller does not access the partitioned storage area; Recording, by the first control unit, arbitrary data in the accessed divided storage area; And a recording medium on which a program is executed by the first control unit to terminate the access to the divided storage area.

When the first control unit accesses any divided storage area, the first control unit may transmit access state information to the second control unit via the MP-AP bus.

Area partitioning information corresponding to the sizes of the partitioned storage areas may be set by the first controller and transferred to the second controller through the MP-AP bus.

According to still another preferred embodiment of the present invention, a program of instructions that can be executed by a digital processing apparatus is tangibly implemented to perform a data transfer method between a plurality of control units using one memory unit. In a recording medium on which a program can be read, the memory unit comprising (a) m (any natural number of 2 to n (natural numbers of 2 or more)) divided storage areas stores first connection state information of each divided storage area. Generating and providing the first control unit and the second control unit through a first bus and a second bus; (b) the first control unit transmitting a processing instruction corresponding to any raw data to the second control unit via a third bus; (c) when the first controller accesses the first partitioned storage area through the first bus with reference to the first connection state information and starts writing the raw data, the memory unit divides the first partition. Transferring second connection state information indicating that a storage area is connected by the first control unit to the second control unit; (d) when the first controller terminates the connection to the first divided storage area, the memory unit transferring third connection state information indicating that the first divided storage area is accessible to the second controller; (e) when the second controller accesses the first partitioned storage area through the second bus with reference to the third connection state information and starts reading the raw data, the memory unit divides the first partition. Transmitting fourth connection state information indicating that a storage area is connected by the second control unit to the first control unit; And (f) a recording medium on which a program is executed by the second control unit for processing the read raw data to correspond to the processing instruction.

The step of causing the second control unit to output the processed raw data through the combined output device may be further executed.

The program determining whether the second controller has finished reading the raw data recorded in the first divided storage area; And when the reading is completed, the step of terminating the connection to the first divided storage area by the second controller may be performed after step (f).

The step (d) may include: determining, by the first controller, whether the storage space of the first divided storage area is used up; When all are used, ending the connection to the first divided storage area by the first controller; The memory unit generates the third connection state information including information indicating that the first divided storage region is available and information on whether the second divided storage region is accessible, and generates the third connection state information to the first controller and the second controller. Delivering; When the second divided storage area is accessible by referring to the third connection state information, the first controller accesses the second divided storage area through the first bus to write the raw data. Performing continuously; And generating, by the memory unit, fifth connection state information indicating that the second divided storage area is connected by the first controller, and transmitting the fifth connection state information to the second controller.

The program determining whether the second controller has finished reading the raw data recorded in the first divided storage area; When the reading is completed, terminating the connection to the first divided storage area by the second controller; Transmitting, by the memory unit, sixth connection state information indicating that the first divided storage area is accessible to the first controller; Determining, by the second controller, whether the seventh connection state information indicating that the second divided storage area is in an accessible state is received from the memory unit; And when the seventh connection state information is received, performing the step of continuously reading the raw data by accessing the second divided storage area by the second control unit may be performed after the step (f). have.

According to still another preferred embodiment of the present invention, in a digital processing apparatus including a plurality of controllers and at least one memory coupled to each controller, each memory for allowing another controller to use a memory dependent on any controller A method for allowing access, comprising: determining whether an additional control unit for performing a preset additional function is occupied by a bus corresponding to a combined additional memory; If it is not occupied, causing the additional control unit to perform bypass logic so that a route is switched such that the main control unit controlling the one or more additional control units and the additional memory unit are directly coupled; And determining, by the main controller, whether an additional memory area is additionally needed, and storing data to be processed or processed in the additional memory unit coupled through the path if necessary.

When the additional control unit does not occupy a bus corresponding to the additional memory, when the additional control unit enters a non-driven state, and when the additional control unit is in a driving state but does not use the additional memory. It may be at least one of.

The additional control unit may transmit corresponding state information to the main control unit after performing the bypass logic.

The additional control unit may determine whether the additional control unit occupies a bus corresponding to the additional memory by using whether the execution command of the bypass logic is received from the main control unit.

According to still another preferred embodiment of the present invention, in a digital processing apparatus including a plurality of controllers and at least one memory coupled to each controller, each memory for allowing another controller to use a memory dependent on any controller A method for allowing access, comprising: determining whether a first additional controller for performing a first preset additional function is occupied by a bus corresponding to a first additional memory coupled to the second additional memory; If not occupied, a route is switched such that the first additional control unit performs bypass logic to control one or more additional control units and the first additional memory unit is directly coupled. Bringing it back; Determining, by the second additional control unit for performing the second preset additional function, whether the available memory area is additionally needed; If necessary, requesting, by the second additional control unit, address information of any additional memory dependent on any additional control unit which is not driven; Receiving, by the second additional control unit, address information corresponding to the first additional memory from the main control unit; And storing, by the second additional control unit, the data to be processed or processed into the first additional memory corresponding to the address information by using the path.

According to still another preferred embodiment of the present invention, a main processor is performed by the additional processor of the digital processing apparatus including an additional processor that performs a predetermined additional function controlled by the main processor and is coupled to a plurality of memories. A memory interface sharing method, comprising: receiving a request for memory access to either internal memory or removable memory from the main processor; Establishing a path for access to a memory corresponding to the request; And transferring data received from the main processor to a corresponding memory through the set path. Here, the path is set through a separate memory interface independently connected to a memory corresponding to the request and a shared memory interface shared to a plurality of memories, and total pins for interfacing with the internal memory coupled to the additional processor. If the number of n is a natural number, and the total number of pins for the interface with the removable memory coupled to the additional processor is m (natural number greater than n), the shared memory interface is one to n-1 of Any one includes k (natural numbers) pins, a separate memory interface for the internal memory includes nk pins, and a separate memory interface for the removable memory may include mk pins.

Each of the individual memory interfaces may include one or more pins for transmitting at least one of a clock (CLK) signal and a chip select (CS) signal.

According to yet another preferred embodiment of the present invention, a program of instructions that can be executed by a digital processing apparatus is tangibly implemented to perform a memory interface sharing method, and a program that can be read by the digital processing apparatus is recorded. A recording medium, comprising: receiving, by an additional processor, a request for access to a memory from a main processor; Establishing a path for access to a memory corresponding to the request, wherein the path is established through a separate memory interface independently connected to a memory corresponding to the request and a shared memory interface shared to a plurality of memories -; And a recording medium on which a program for executing the step of transferring the data received from the main processor to the corresponding memory through the set path is provided. Here, the digital processing apparatus includes the main processor and the additional processor configured to perform an additional function preset by the control of the main processor, wherein the additional processor is simultaneously coupled to an internal memory and a removable memory. If the total number of pins for interface with the integrated memory coupled is n (natural number), and the total number of pins for interface with the removable memory coupled to the additional processor is m (natural number greater than n), the The shared memory interface includes k (natural numbers) pins, one of n to 1-1, the individual memory interface for the internal memory includes nk pins, and the individual memory interface for the removable memory is mk Pins may be included.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be denoted by the same reference numerals regardless of the reference numerals and redundant description thereof will be omitted. In addition, the present invention provides a digital processing apparatus or system of any type consisting of a plurality of controllers and a plurality of memories (for example, a mobile communication terminal, a PDA, a portable multimedia player (PMP), an MP3 player, a digital camera, a digital television, The same may be applied to a portable terminal such as an acoustic device and / or a home digital device provided in a home), but the following description will focus on the portable terminal for convenience of explanation and understanding.

Partition size variable

3 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to an exemplary embodiment of the present invention, and FIG. 4 is a diagram illustrating a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention. to be.

Referring to FIG. 3, the main control unit 210 and the additional control unit 220 transmit and receive information through a Main Processor (MP) -AP (Application Processor) bus (BUS), and the main control unit 210 and the memory unit 310. ) Transmits and receives information through a shared memory (MP-SM) bus, and the additional control unit 220 and the memory unit 310 are combined to transmit and receive information through the AP-SM bus. A bus is a common purpose electrical path used to transfer information between a controller, a main memory, and an input / output device in a computer. Here, the main controller 210 may be a processor for controlling the overall operation of the portable terminal. In addition, the additional control unit 220 may be a dedicated processor for processing MPEG4, 3D graphics, camera functions, and the like. The main controller 210 may control the operation of the additional controller 220.

The memory unit 310 includes one or more ports exclusively for transmitting and receiving information with the main controller 210 and one or more ports exclusively for transmitting and receiving information with the additional controller 220.

For example, as shown in FIG. 3, if the memory unit 310 is commonly combined with the main controller 210 and the additional controller 220, the two controllers 210 and 220 may be configured as one memory unit ( Since the structure using the 310 is used, the memory unit 310 must include two access ports. That is, two access ports are divided into first ports Addr_A and Data_A and second ports Addr_B and Data_B so that the first port is connected to the main controller 210, and the second port is the additional controller 220. It is set to connect with.

As shown in FIG. 4, the storage area of the memory unit 310 includes at least four areas (ie, the main control area 410, the common area 430, the additional control area 450 and the variable area). 420, 440), and as many as five regions (ie, the main control unit 210 dedicated area 410, the common area 430, the additional control area 450, and the first variable area 420). And the second variable region 440.

The first and second variable areas 420 and 440 are storage areas configured to be expanded when the capacity of any one of the main control area 410, the common area 430, or the additional control area 450 is insufficient. to be. The variable area may be a specific area (eg, a main control area 410) according to a request of each control (ie, a main control or an additional control) (for example, generation and sharing of region partition information—see FIG. 5). , At least one of the common area 430 and the additional control area 450 may be included in part or in whole. Therefore, the smallest storage area that can operate in a common area is the common area 430, and the maximum storage area is the sum of the first variable area 420, the common area 430, and the second variable area 440. Can be. Similarly, the size of the dedicated area that can be used exclusively by each control unit can also be increased or decreased depending on whether it includes the variable area. In the initial state, the first and second variable regions 420 and 440 may be partially or entirely included in at least one of the main controller dedicated region 410, the common region 430, or the additional controller exclusive region 450. It may be a storage area. The variable method of the divided storage areas will be described in detail later with reference to FIG. 5.

The main controller 210 may access the main controller dedicated area 410 and / or the common area 430 through the first port to process data, and the additional controller 220 may be the additional controller dedicated area through the second port. Data processing is possible by accessing the 450 and / or the common area 430. However, the common area 430 is limited such that the plurality of controllers 210 and 220 may not be connected at the same time.

A method of restricting a plurality of controllers 210 and 220 from being simultaneously connected to the common area 430 may include: a method in which a controller connected first notifies another controller of a connection fact (eg, connected address information, etc.), and a memory; When the controller 310 accesses the common area in the unit 310, there may be a method of notifying the other controller of the connection fact. That is, the main control unit 210 and the additional control unit 220 may simultaneously access the memory unit 310 through independent paths to process data, and in this case, collision between the two may be prevented.

However, if the digital processing device (hereinafter, the description will mainly be made on the case of a "portable terminal") according to the present invention is a mobile phone, the main function of the mobile phone is a phone call function. In the state where the telephone call is started, the access priority right to the common area 430 may be provided by the main controller 210 which is in charge of the telephone call function. For example, when a phone call is started while the additional control unit 220 performing the additional function is accessed in the common area 430, the main control unit 210 releases access to the common area 430 of the additional control unit 220. The additional control unit 220 may enable access to the common area 430 of the main control unit 210 by releasing access to the common area 430 according to a request of the main control unit 210.

Address information of a divided storage area among the storage areas of the memory unit 310 may be set and managed by the main controller 210, and the address information set by the main controller 210 may be additionally controlled 220. Provided and shared. Of course, the setting and management of the address information may also be performed by the additional control unit 220. If necessary, each control unit 210 or 220 may be set as another control unit 220 or 210 with authority to set address information. By providing the address information, the address information can be shared.

Information about the divided storage areas of the memory unit 310 may be recognized by each controller during a booting process of the portable terminal.

5 is a flowchart illustrating a method of varying a size of a partitioned storage area according to an exemplary embodiment of the present invention.

5 illustrates that the main controller 210 processes arbitrary data and stores the data in the common area 430, and then the additional controller 220 reprocesses the data stored in the common area 430 and re-stores the data in the common area 430. It will explain the process. In addition, the flowchart of FIG. 5 assumes that the main control unit 210 has authority to set the size of the common area 430 of the memory unit 310.

Referring to FIG. 5, in operation 505, the main controller 210 sets an address range of each divided storage area in order to divide the storage areas of the memory unit 310 into a plurality (ie, region partition information setting). do. That is, the main controller 210 writes an appropriate value in a register for dividing and setting the storage area of the memory unit 310.

The main control unit 210 transmits the area division information set in step 510 to the additional control unit 220, and the additional control unit 220 registers the area division information received in step 515, and thereby the main control unit 210 and the additional control unit 220. ) Share the partitioning information of the memory unit (310).

In operation 520, the main controller 210 determines whether the common area 430 of the storage area of the memory 310 is accessible. If it is not accessible (for example, the additional control unit 220 has already accessed the same area), the process waits at step 520.

However, if accessible, the flow advances to step 525 to determine whether the size of data to be recorded in the common area 430 exceeds the size of the recordable area of the common area 430. When the main control unit 210 is accessed in the common area 430, information indicating the access state of the main control unit 210 is transmitted to the additional control unit 220 so that the additional control unit 220 does not access the common area 430 at the same time. It needs to be sent. The corresponding information may be notified to the additional controller 220 by the main controller 210 or the memory 310. The information may be notified through a status register.

If the size of the data to be recorded is small, the flow proceeds to step 545 to store the data to be recorded in the common area 430. The data stored in the common area 430 may be a result of being processed by the main control unit 210 or data stored in the dedicated area 410 of the main control unit 210 for processing by the additional control unit 220. It may be data to be moved. The main controller 210 adds a processing instruction (for example, storage address information of the data, a processing form of the data (for example, decoding, etc.), etc.) so that the additional controller 220 can process the stored data. It may transmit to the control unit 220.

However, if the size of the data to be recorded exceeds the size of the recordable area, the main controller 210 resets the address range of each divided storage area in order to expand the common area 430 in step 530. Area repartitioning information).

The main control unit 210 transmits the area repartitioning information set in step 535 to the additional control unit 220, and the additional control unit 220 registers the area repartitioning information received in step 540, so that the main control unit 210 and the additional control unit ( The area redistribution information of the memory unit 310 is shared between the plurality of memory cells 220.

The main controller 210 stores the data to be recorded in the common area 430 extended in step 545. Of course, the main controller 210 may store the corresponding data in the extended common area 430 and then perform steps 535 and 540.

In operation 550, the additional controller 220 determines whether the common area 430 is accessible in the storage area of the memory 310. If it is not accessible (for example, if the main control unit 210 is still accessed in the same area), the process waits at step 550.

However, if accessible, the process proceeds to step 555 where data to be recorded and processed in the common area 430 is read. When the additional control unit 220 is accessed to the common area 430, information indicating the access state of the additional control unit 220 is transmitted to the main control unit 210 so that the main control unit 210 does not access the common area 430 at the same time. It needs to be transmitted as described above.

In operation 560, the additional controller 220 processes the read data in a preset manner. As described above, the processing form of the data may be instructed by the main controller 210.

In step 565, the additional controller 220 determines whether the common area 430 is accessible in the storage area of the memory 310. If it is not accessible (for example, when the main control unit 210 accesses the same area), the process waits at step 565.

However, if accessible, the process proceeds to step 570, where the additional controller 220 writes the data processed in step 560 to the common area 430. In this case, if the size of the data to be recorded exceeds the size of the recordable area of the common area 430, the additional control unit 220 transmits an area repartition request to the main control unit 210, and then to the main control unit 210. As a result, the common area 430 may be expanded to record corresponding data.

The main controller 210 has been described with reference to FIG. 5 based on a method of setting the size of each divided area in which the storage area of the memory unit 310 is divided.

However, it is apparent that the region division information may be shared by setting the size of the division area in the additional control unit 220 instead of the main control unit 210 and then transmitting the region division information to the main control unit 210.

Another method is to compare the size of the data to be recorded by the control unit currently accessed in the common area with the size of the recordable storage area, and set the region partition information so that the size of the common area is expanded when the data size is large. It is obvious that the method of transmission may also be applied. When the method is applied, the control unit accessed to the common area can reset the size of the partition by itself, thereby minimizing the amount of information (for example, request for subdivision of a region) transmitted between the plurality of control units. .

Although the detailed description of the two methods described above will be omitted by those skilled in the art through the above description will be omitted a separate description.

6 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to another exemplary embodiment of the present invention.

As illustrated in FIG. 6, the additional control unit 220 and the memory unit 310 may be implemented as one package 610. That is, by implementing the additional control unit 220 and the memory unit 310 in one package, the use area in the printed circuit board can be reduced, and as a result, the portable terminal can be miniaturized.

Multiple access control of partitions

7 is a diagram illustrating a coupling structure between a main controller, an additional controller, and a memory unit according to an exemplary embodiment of the present invention, and FIG. 8 is a diagram illustrating a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention. to be.

Referring to FIG. 7, the main controller 210 and the additional controller 220 transmit and receive information (for example, a processing command and status information) through a Main Processor (MP) -AP (Additional Processor) bus, The control unit 210 and the memory unit 310 transmit and receive data through the MP (Main Processor) -SM (Shared Memory) bus, and the additional control unit 220 and the memory unit 310 transmit data through the AP-SM bus. Combined to transmit and receive. Here, the main controller 210 may be a processor that controls the overall operation of the digital processing apparatus. In addition, the additional control unit 220 is a processor dedicated to processing MPEG4, 3D graphics, camera functions, MP3 file playback, etc., and may be controlled by the main control unit 210. A peripheral device such as a display device 710 may be coupled to the rear end of the additional control unit 220. Whether the data is to be output through the display apparatus 710 or the like may be controlled by the main controller 210 or the additional controller 220.

The memory unit 310 should be provided as an access port corresponding to the quantity of the control unit provided as a structure shared by a plurality of combined control units or sharing the memory unit 310. Although not shown, the memory unit 310 may include an internal controller for controlling an operation of the memory unit 310.

For example, as shown in FIGS. 7 and 8, when the memory unit 310 is commonly combined with the main control unit 210 and the additional control unit 220, the two control units 210 and 220 may be one unit. Since the structure using the memory unit 310, the memory unit 310 should be provided with two access ports (Access Port). That is, two access ports are divided into a first port 810 and a second port 820 so that the first port 810 is connected to the main controller 210, and the second port 820 is an additional controller ( 220). The main controller 210 and the additional controller 220 may each use an independent clock.

In addition, the storage area of the memory unit 310 may be divided into divided areas corresponding to the number of the combined control unit. This is to allow each control unit to simultaneously access the respective divided areas to perform data write. For example, when there are two control units coupled to the memory unit 310, as shown in FIG. 8, the memory unit 310 has two regions (ie, a first storage region 830 and a second storage region 840). Can be divided into Each of the divided regions 830 and 840 may be individually accessed unless the divided regions 830 and 840 are not assigned to a specific controller and accessed at the same time. This is to maintain the temporal consistency of the data continuously by setting the next process to proceed after the completion of either process. Of course, even if there are two controllers coupled to the memory unit 310, the storage area of the memory unit 310 may be divided into two or more.

The divided areas of the memory unit 310, that is, the sizes of the first storage area 830 and the second storage area 840 are predetermined as defaults, or the main control unit 210 and / or the additional control unit 220 are used. By the main control unit 210 and / or the additional control unit 220 to be divided into arbitrary sizes or at every required time point (for example, when the data to be recorded is larger than or equal to the size of the recordable area). It may be. That is, address information of the divided storage areas among the storage areas of the memory unit 310 may be set and managed by the main controller 210, and the address information set by the main controller 210 may be additionally controlled. Provided at 220 and shared. Of course, the setting and management of the address information may also be performed by the additional control unit 220. If necessary, each control unit 210 or 220 may be set as another control unit 220 or 210 with authority to set address information. By providing the address information, the address information can be shared. In this case, the information about the divided storage area of the memory unit 310 may be recognized by each controller in the booting process of the portable terminal. In addition, if the memory unit 310 is an SDRAM, regions may be divided in bank units. That is, a general SDRAM includes a RAS address, a CAS address, and a bank address, and typically consists of four banks. In this case, four banks may be divided into two and allocated to the first storage area 830 and the second storage area 840.

8, the first port 810 is shown at the first storage area 830, and the second port 820 is shown at the second storage area 840. The 820 does not mean that only one storage area is accessible. Therefore, when accessing through each port (810 or 820), it is natural that each of the divided storage areas (830, 840) can be accessed. As described above, however, if any one of the controllers has access to any one storage area for recording data, the other controller should be restricted from accessing the storage area. A method of restricting the plurality of controllers 210 and 220 from being connected to the first storage area 830 or the second storage area 840 at the same time may be performed by connecting the first controller to another controller. Address information, etc.), and a method of notifying a connection fact to another controller when an arbitrary controller is connected to the common area in the memory unit 310. That is, the main control unit 210 and the additional control unit 220 may simultaneously access the individual storage areas of the memory unit 310 through independent paths to process data, and in this case, collision between the two may be prevented.

9 is a flowchart illustrating a process of accessing the divided storage area by an arbitrary control unit according to an exemplary embodiment of the present invention.

The storage area of the memory unit 310 according to the present invention may be divided into a plurality of divided storage areas 830 and 840, and each controller may access one of the divided storage areas through an access port to record data ( Write) or the recorded data can be read. That is, the additional control unit 220 may freely access the second storage area 840 while the first storage area 830 is accessed by the main control unit 210. Therefore, each control unit has an advantage in that it is possible to simultaneously access each of the divided storage areas of the memory unit 310 and to process necessary data. However, when a plurality of controllers simultaneously access one divided storage area, data consistency may be impaired, so a limiting method is required. Of course, even if a plurality of controllers access the same divided storage area at the same time, any one controller may be allowed to record data and the other controller only reads data. Hereinafter, a method of preventing a plurality of controllers from simultaneously accessing one divided storage area will be described with reference to FIG. 9.

Referring to FIG. 9, in step 910, an arbitrary control unit (ie, either the main control unit 210 or the additional control unit 220, hereinafter referred to as a first control unit) may designate a specific divided storage area (ie, a first storage area). 830 or the second storage area 840 is determined.

If there is no need to access the partitioned storage area, the process waits at step 910.

However, when the divided storage area needs to be accessed, the first control part may have another control part (ie, the other one of the main control part 210 or the additional control part 220 hereinafter referred to as the second control part) in step 920. It is determined whether or not the user has already accessed. Whether the second control unit accesses an arbitrary divided storage area may be recognized through state information received from the control unit or the memory unit 310.

If the second control unit accesses the divided storage area, the process waits at step 920 until the second control unit ends the access state for the divided storage area.

However, if the partitioned storage area is accessible, the process proceeds to step 930 where the first controller accesses the partitioned storage area and transmits access status information indicating that the first controller accesses the partitioned storage area to the second controller. do. The access state information may be transmitted immediately before the access to the divided storage area, or may be transmitted to the second control unit by the memory unit 310 as described above.

In operation 940, the first controller determines whether storage of data to be recorded in the accessed divided storage area is completed. If the recording of the data to be recorded is not completed, the recording of the data is continued. If the recording of the data to be recorded is completed, access to the corresponding partition storage area is terminated in step 950. In addition, the first control unit or the memory unit 310 transmits the access termination information on the divided storage area to the second control unit to enable access of the second control unit.

As described above, in the divided storage area sharing method according to the present invention, since the main control unit 210 and the additional control unit 220 can access a plurality of divided storage areas by crossing each other, the data to be transferred between each partition is divided. After recording in a certain area of the storage area, the right to access the corresponding partitioned storage area is provided to the counterpart (for example, transmission of access termination information). Therefore, when the additional control unit 220 processes arbitrary data by the processing command of the main control unit 210, the rapid processing is possible. In this case, if necessary, the storage address information of the corresponding data may be delivered to the other party.

10 is a diagram illustrating a divided state of a storage area of a memory unit according to another exemplary embodiment of the present invention.

As illustrated in FIG. 10, the storage area of the memory unit 310 includes a plurality of divided storage areas (ie, a first storage area 1010, a second storage area 1020, a first data transfer area 1030, Second data transfer area 1040, etc.).

As shown in FIG. 8, in the method of dividing the storage area of the memory unit 310 into only the first storage area 810 and the second storage area 820, the first control unit (ie, the main control unit 210 or the addition unit). In order for the second controller (that is, the other of the main controller 210 or the additional controller 220) to use the data while the controller 220 has recorded the data in an arbitrary division storage area, Access to the partitioned storage area must be terminated.

However, even when a large amount of data is to be moved between the main control unit 210 and the additional control unit 220, such as graphics processing, if the separate data transfer area (1030, 1040) as shown in FIG. It is not necessary to give up access to the storage area 1010 or 1020 by moving only the data from each storage area to the corresponding data transmission area and then copying the information to other controllers to access the data transmission area. do. After the data to be transmitted to the other controller is stored in the data transfer area, the controller controls the bus to which the storage position information of the data and the processing instruction (for example, a processing type indication of the corresponding data) correspond to the other controller. Is passed through. Of course, the storage location information can be omitted if the data storage address in the data transfer area is set as the default. In this way, by transmitting and receiving an access right to the storage area itself storing the data between the plurality of controllers, data transmission / reception time for data processing can be reduced.

Of course, when a small amount of data needs to be transmitted between the plurality of control units, data may be transmitted and received through a bus connected between the control units even if the access to the divided storage area is not terminated.

Fast data delivery

Hereinafter, after the main controller 210 writes data to be processed by the additional controller 220 in a specific storage area, the additional controller 220 may access the corresponding storage area and read the data. Although only the process of controlling access rights in the memory unit 310 will be described, the person skilled in the art will know that any one first control unit (for example, the main control unit or the first additional control unit) is different from the second control unit (for example, After the data to be processed in the second additional control unit or the main control unit is written to a specific storage area, the access control is controlled in the memory unit so that the second control unit can access and read the storage area. It can be easily understood that the same can be applied to the method. Therefore, it is to be noted that the technical spirit of the present invention is not limited to the following descriptions merely by omitting descriptions of additional matters easily understood by those skilled in the art.

11 is a diagram illustrating a coupling structure between a main controller, an additional controller, a memory unit, and a display device according to an exemplary embodiment of the present invention, and FIG. 12 is a divided state of a storage area of a memory unit according to an exemplary embodiment of the present invention. The figure which shows.

Referring to FIG. 11, in the digital processing apparatus according to the present invention, the main controller 210 and the additional controller 220 are combined in a structure in which one memory unit 310 is shared. After the additional control unit 220, a display device 710 directly controlled by the main control unit 210 or controlled by the additional control unit 220 according to a processing command of the main control unit 210 is combined. Of course, the output device coupled according to the function of the additional control unit 220 may vary. In addition, although only one additional control unit 220 is illustrated in FIG. 11, it is obvious that the quantity or processing operation of the additional control unit may vary according to functions included in the digital processing device. In addition, the additional control unit may be controlled by the main control unit.

As illustrated in FIG. 11, the main control unit 210 and the additional control unit 220 may perform information (for example, a processing command such as a driving start command or a driving stop command of the display device 710 through a MP-AP bus). Information). The main control unit 210 is coupled to the memory unit 310 through the MP-SM bus to write arbitrary data (eg, polygon data, texture data, etc.) in a predetermined storage area of the memory unit 310. do. In addition, the additional control unit 220 is coupled to the memory unit 310 through the AP-SM bus to store data (ie, data recorded by the main control unit 210) recorded in a predetermined storage area of the memory unit 310. Read A bus is a common purpose electrical path used to transfer information between a controller, a main memory, and an input / output device in a computer. Here, the main controller 210 may be a processor that controls the overall operation of the digital processing device (eg, the portable terminal). In addition, the additional control unit 220 may be a dedicated processor for processing MPEG4, 3D graphics, camera functions, MP3 file playback, and the like. A peripheral device other than the illustrated display device 710 may be coupled to the rear end of the additional control unit 220.

The memory unit 310 is a structure shared by a plurality of combined controllers (that is, the main controller 210 and one or more additional controllers), and includes accesses corresponding to the number of controllers provided or sharing the memory unit 310. It has a port (Access Port). For example, as shown in FIGS. 11 and 12, when the memory unit 310 is commonly combined with the main control unit 210 and the additional control unit 220, the two control units 210 and 220 may be one unit. Since the memory unit 310 is structured, the memory unit 310 includes two access ports. That is, the two access ports are divided into a first port and a second port so that the first port is connected to the main controller 210 and the second port is connected to the additional controller 220. That is, although one memory core of the memory unit 310 is provided, a plurality of access ports may be provided. The main controller 210 and the additional controller 220 may use independent clocks, respectively. Although not shown, the memory unit 310 may include an internal controller for controlling internal operations.

In addition, the storage area of the memory unit 310 may be divided into a plurality of areas, and the number of storage areas may be at least two to at most n (natural numbers). For example, the quantity of the divided storage regions may match the quantity of the provided controllers. This allows each control unit to be individually connected to each partition at the same time via independent paths, without disturbing the necessary operations (e.g., writing or reading data) and without conflicting between them. To do so.

For example, when there are two control units coupled to the memory unit 310, as shown in FIG. 12, the memory unit 310 has two regions (ie, a first storage area 1210 and a second storage area 1220). Can be divided into Each of the divided regions 1210 and 1220 may be individually accessed unless it is assigned to a specific controller as a dedicated region and is not simultaneously accessed. This is to maintain the temporal consistency of the data continuously by setting the next process to proceed after the completion of either process. Of course, even if there are two controllers coupled to the memory unit 310, the storage area of the memory unit 310 may be divided into two or more.

Referring briefly to the signal input / output process illustrated in FIG. 12, when the main controller 210 wants to record specific data in the storage area A of the divided areas of the memory 310, the main controller 210 may store the memory 310. Address information for recording data (Addr_A: address signal of storage area A), data to be recorded (Data_A), and control signals (e.g., WE_A (Write Enable for indicating data recording to storage area A). ), The chip select signal CS_A (Chip Select_A), the clock CLK_A, and the like for the storage area A are transmitted. The memory unit 310 causes data received according to a command (ie, a write command) of the main controller 210 to be recorded in the storage area A. FIG. The main controller 210 terminates the connection with the storage area A when both the storage capacity of the storage area A is used by using the address information preset for the divided area and the address information indicated at the time of data recording. Provides to the controllers the occupancy state information (for example, information indicating that the connection to the storage area A has been terminated and data can be recorded by accessing the storage area B).

In addition, if the data recording is completed before the storage capacity of the storage area A is completely used, the main control unit 210 is satisfied by terminating the connection with the memory unit 310. In this case, the memory unit 310 also has the occupied state information. Since it is newly updated, it is provided to the controllers. If any data is recorded in the storage area A through the above-described process, the additional control unit 220 that reads out and uses the corresponding data includes address information (Addr_A: address signal of the storage area A) and control signals for reading data. (E.g., OE_A (Output Enable) for instructing data read from storage area A, chip select signal CS_A (Chip Select_A), clock CLK_A, etc.) to transmit data (e.g., Data_A) is read. Whether the additional control unit 220 may access the storage area A may be checked using the occupancy state information provided from the memory unit 310. For example, when "RBusy (Read Busy) _A" is the first state (for example, "Low State") among the occupancy state information provided from the memory unit 310, it may be recognized as being in a state capable of being accessed by reading. Can be. After the first controller writes data in an arbitrary storage area of the memory unit 310 and the second controller reads the recorded data by accessing the corresponding storage area after the data recording of the first controller is completed, This will be described in detail with reference to FIG. 13.

In addition, the size of the divided area of the memory unit 310, that is, the first storage area 1210 and the second storage area 1220 is predetermined as a default, or the main control unit 210 and / or the additional control unit. The main control unit 210 and / or the additional control unit 220 may be divided into arbitrary sizes by the 220, or may be changed by the main control unit 210 and / or the additional control unit 220 whenever necessary data (for example, when data to be recorded is larger than or equal to the size of the recordable area). It may be set. That is, address information of the divided storage areas among the entire storage areas of the memory unit 310 may be set and managed by the main controller 210, and the address information set by the main controller 210 may be added. The control unit 220 may be provided and shared. Of course, the setting and management of the address information may also be performed by the additional control unit 220. If necessary, each control unit 210 or 220 may be set as another control unit 220 or 210 with authority to set address information. By providing the address information, the address information can be shared. In this case, the information about the divided storage area of the memory unit 310 may be recognized by each controller in the booting process of the digital processing device (for example, the portable terminal).

In addition, if the memory unit 310 is an SDRAM, regions may be divided in bank units. That is, a general SDRAM includes a RAS address, a CAS address, and a bank address, and a bank generally consists of four banks. In this case, the four banks may be divided into two and allocated to the first storage area 1210 and the second storage area 1220.

FIG. 13 is a data flow diagram illustrating a sequential connection and processing procedure of a controller according to access authority control for a divided storage area according to an exemplary embodiment of the present invention.

In describing the sequential connection and processing of the control unit with reference to FIG. 13, the initial state is writable in all divided storage areas (hereinafter, assumed to be divided into only storage area A and storage area B) of the memory unit 310. It is assumed that the state (ie, WBusy (Write Busy) is Low) and the readable state (ie, RBusy (Read Busy) is Low) and the address size of each partition is 1000. In addition, the main control unit 210 records data in the order of the storage area A, the storage area B, and the storage area A, and the additional control unit 220 stores the data recorded by the main control unit 210 in the storage area A, the storage area. A case where the data is read in order of B and storage area A will be described.

Referring to FIG. 13, in operation 1305, the memory unit 310 provides first control state information to each controller to indicate that initial states of all divided storage areas are a writable state and a readable state.

If any information (eg, 3D graphics) is to be output via any peripheral device (eg, display device 710), the main controller 210 adds the additional coupled to the peripheral device in step 1315. The control unit 220 transmits a driving start command through the MP-AP bus.

Subsequently, the main controller 210 transmits a data storage command through the MP-SM bus to record arbitrary data in the storage area A in step 1320. As described above, the data storage command may include a data storage address, data to be written, and control signals (eg, WE_A, CS_A, CLK_A).

In operation 1325, since the main controller 210 is connected to the storage area A to perform data recording, the memory 310 receives second occupation state information indicating that the storage area A is occupied by the main control unit 210 for data recording. Provided to each control unit. The second occupancy state information includes only changed information (ie, WBusy_A = High) compared to the previous occupancy state information, or occupancy state information for all partitions (that is, WBusy_A = High, RBusy_A = Low, WBusy_B = Low, RBusy_B = Low).

The additional control unit 220 connects to the memory unit 310 according to the driving start command of step 1315 or enters into a storage area in which the main control unit 210 records data by using the occupancy state information provided from the memory unit 310. When the connection is possible, the memory 310 is connected to read the data recorded by the main controller 210. The additional control unit 220 may recognize in which divided storage area the main control unit 210 stores data only by a change state of the occupancy state information (that is, a change from WBusy_A = Low to WBusy_A = High) after receiving the driving start command. .

In operation 1330, the main controller 210 determines whether the storage space of the storage area A is used up. The main controller 210 may determine whether all storage spaces are used by comparing the data storage address included in the data storage command with the size of the data storage address pre-assigned to each divided storage area. Of course, the memory unit 310 may provide information on whether all the storage spaces of the divided storage regions are used. In addition, when recording of data to be transmitted to the additional controller 220 by the main controller 210 is completed, subsequent steps of the main controller 210 may be omitted.

If all the storage space has been used, the process proceeds to step 1335, but if the storage space remains, the process proceeds to step 1320 again. That is, the data storage command may be repeatedly transmitted to correspond to the new storage address and / or the new data until all the data to be recorded is recorded or the storage space of the storage area A is used up. However, the memory unit 310 maintains the occupation state of the main controller 210 for the storage area A until the main controller 210 connected to the storage area A releases the connection state. Therefore, the memory unit 310 does not need to repeatedly output the occupancy state information each time step 1320 is repeatedly performed, and it is sufficient to maintain the current occupancy state information.

Since the main controller 210 recognizes that the storage area B is in a recordable state (ie, WBusy = Low) through the second occupation state information provided through step 1325, recording the remaining data in the storage area B in step 1335. In order to transmit the data storage command to the memory unit 310 via the MP-SM bus. Of course, if the storage area B is connected by the other additional control unit, it will wait until the connection of the other additional control unit is released.

In operation 1340, the memory unit 310 provides third controllers with third occupation status information indicating that the main controller 210 has released the connection to the storage area A and has connected to the storage area B for data recording. As described above, the third occupied state information also includes only changed information (ie, WBusy_A = Low, WBusy_B = High) compared to the previous occupied state information, or occupied state information for all partitions (ie, WBusy_A = Low, RBusy_A = Low, WBusy_B = High, RBusy_B = Low).

The additional control unit 220 recognizes that the storage area A is disconnected from the main control unit 210 by the third occupation state information (and the second occupation state information) and is in a readable state (that is, RBusy_A = Low). In step 310, a read command of the data recorded in the storage area A is transmitted. As described above, the data read command may include a data storage address and control signals (eg, OE_A, CS_A, CLK_A).

In operation 1350, the memory unit 310 provides fourth controllers with occupancy status information indicating that the additional controller 220 accesses the storage area A to read data. As described above, the fourth occupation state information also includes only changed information (ie, RBusy_A = High) compared to the previous occupation state information, or occupies state information for all partitions (that is, WBusy_A = Low, RBusy_A = High, WBusy_B = High, RBusy_B = Low).

In step 1355-1, the additional controller 220 determines whether reading of data recorded in the storage area A is completed. Completion of reading of the stored data may be determined by comparing the size of the data storage address included in the data reading command with the size of the data storage address previously allocated to each divided storage area.

If the reading of all data recorded in the storage area A has not been completed, the flow advances to step 1345 to continue reading of the data. In this case, step 1350 may be omitted. However, if the reading of all data recorded in the storage area A is completed, the additional control unit 220 proceeds to step 1360-1 to release the connection to the storage area A.

In operation 1365, the memory unit 310 provides the controllers with fifth occupancy status information indicating that the additional controller 220 has released the connection to the storage area A. FIG. As described above, the fifth occupation state information also includes only changed information (ie, RBusy_A = Low) compared to the previous occupation state information, or occupies state information for all partitions (that is, WBusy_A = Low, RBusy_A = Low, WBusy_B = High, RBusy_B = Low). Thereafter, the additional control unit 220 waits until the storage area B can be accessed for reading data (that is, until the main control unit 210 finishes writing data to the storage area B and releases the connection).

Separately, the main controller 210 determines whether the storage space of the storage area B is used up in step 1355-2. The main controller 210 may determine whether all storage spaces are used by comparing the data storage address included in the data storage command with the size of the data storage address pre-assigned to each divided storage area. Of course, the memory unit 310 may provide information on whether all the storage spaces of the divided storage regions are used. In addition, when recording of data to be transmitted to the additional controller 220 by the main controller 210 is completed, subsequent steps of the main controller 210 may be omitted.

If all the storage space has been used, go to step 1360-2 to send a data storage command to the memory unit 310 to write data to the storage area A again, but if the storage space still remains in the storage area B, step 1335 Proceed back to. In this case, as described above, step 1340 may be omitted. The data stored in the storage area A in operation 1360-2 may be overwritten or deleted after the data stored in operation 1320 is deleted. However, step 1360-2 may be performed after the additional control unit 220 terminates the connection if the additional control unit 220 is still reading data from the storage area A. FIG.

In operation 1365, the memory unit 310 provides the sixth occupancy status information indicating that the main controller 210 has disconnected the storage area B and reconnected to the storage area A to each controller. As described above, the sixth occupied state information may also be configured to include only changed information (ie, WBusy_A = Low, WBusy_B = High) compared to the previous occupied state information, or include occupied state information for all partitions. .

As shown in FIG. 13, the main control unit 210 connected to the storage area B performs data recording, and the additional control unit 220 connected to the storage area A performs data reading. However, although the steps of the main controller 210 and the additional controller 220 are simultaneously performed in steps 1355-1 to 1365 of FIG. 13, they are shown in time-series order according to the processing capability of each controller or the difficulty of the processing operation. It is obvious that it may be reconstructed. In other words, the processing of each control unit is only performed separately in a separate operation. That is, the main control unit 210 for recording data in the storage area B may access the storage area B after determining whether any additional control unit is connected to the storage area A by using the fifth occupation state information. If so, access is made to the storage area A again and data is recorded. Separately, the additional control unit 220 which reads out the data recorded in the storage area A is connected to the storage area B if all data has been read (that is, whether the main control unit 210 or another additional control unit is connected). Is determined using the sixth occupancy state information, and if access is possible, the data is accessed to the storage area B to read data.

Through the above-described process, the main controller 210 does not need to transfer data to be processed by the additional controller 220 through the MP-AP bus, and ends the connection after completing storage in an arbitrary storage area and adds to the corresponding storage area. By allowing the control unit 220 to be connected, it is possible to quickly transmit data only by changing the connection subject to the storage area.

Allow individual memory access

In recent years, various attempts have been made to share a memory provided by each additional control unit with another additional control unit or the main control unit in order to expand storage space or improve processing efficiency. In this case, a controller (that is, a main controller or an optional additional controller) that can use a specific memory is distinguished by using a bus controller or a selector.

14 to 16 illustrate a conventional memory sharing structure.

Referring to FIG. 14, the plurality of additional controllers 1410, 1420, and 1430 are connected to the bus controller 1450 of the main controller 1440 and the plurality of additional memories 1460, 1470, and 1480 through each bus. do. Each additional memory may be a memory dependent on each additional control unit. Of course, the main controller 1440 may be dependent on itself, and may include a main memory (not shown) in which arbitrary data can be written by another additional controller. In general, in order to write arbitrary data in the additional memory subordinated to the additional memory subordinate to the other additional control part or each additional control part, each additional control part is provided with a bus controller (not shown) in the additional control part. It must be connected to memory. In this case, it is necessary to know which additional memory is currently used by each additional control unit. Also, since the data by the plurality of additional control units may be duplicated and recorded in the same storage area in the additional memory, there is a risk of bus collision. To this end, a separate bus controller 1450 must be provided in the main controller 1440. That is, the bus controller 1450 provided in the main controller 1440 manages additional memory connection states of the additional controllers to prevent bus collision or data duplication.

However, in the conventional memory sharing structure shown in FIG. 14, the configuration of the main controller 1440 becomes complicated, and the bus controller 1450 in the main controller 1440 needs to perform a function such as a bus control. The processing efficiency of its own function is reduced, and there is a problem that the entire system becomes more dependent on the main controller 1440.

Referring to FIG. 15, a plurality of additional controllers 1410 and 1420 are connected to a main controller 1440 and a plurality of memories 1460, 1470, and 1510 through respective buses BUS. Each additional memory may be a memory dependent on each additional control unit. In order for a plurality of controllers to share a plurality of memories, the controllers (ie, the main controller and the additional controllers) must be bus controlled by the main controller 1440 with interfaces with the memories. That is, the main controller 1440 should further include control logic for controlling the additional controller as well as the bus controller. In this state, the main control unit 1440 terminates the additional control unit or controls the additional control unit to be in an incapable state such that an additional control unit cannot use a specific memory.

However, the conventional memory sharing structure illustrated in FIG. 15 also complicates the configuration of the main controller 1440 and the bus controller 1450 in the main controller 1440 needs to perform functions such as bus control. The processing efficiency of its own function is reduced, and there is a problem that the entire system becomes more dependent on the main controller 1440.

16 illustrates a structure in which a plurality of controllers (that is, the main controller 1440 and the plurality of additional controllers 1410 and 1420) share one shared memory 1610. Like the memory sharing structure of FIG. 15, the memory sharing structure illustrated in FIG. 16, each controller (that is, each of the main controller and the additional controller) must have an interface with the shared memory 1410, and the bus is controlled by the main controller 1440. It must be controlled. That is, the main controller 1440 should further include control logic for controlling the additional controller as well as the bus controller.

Therefore, even in the memory sharing structure illustrated in FIG. 16, the main controller 1440 still has problems such as configuration complexity and low processing efficiency.

17 is a flowchart showing a data writing method using another memory in the above-described conventional memory sharing structure. That is, according to the conventional memory sharing structure, FIG. 17 illustrates a case in which the size of data to be written by the arbitrary additional control unit 1705 is larger than the storage capable storage area of the memory provided by the additional control unit 1705 or the additional storage area. If necessary, the process of storing the corresponding data in a memory provided by the other additional control unit or the main control unit 1440.

Referring to FIG. 17, in operation 1710, the optional additional controller 1705 performs a preset function. The additional control unit 1705 may be an additional processor for performing a camera function such as JPEG encoding or JPEG decoding, or an additional processor for a music file reproducing function for encoding a music file or decoding a music file. Can be.

In operation 1715, the additional control unit 1705 determines whether an additional storage area for storing data generated according to function execution or necessary for function execution is required. The additional storage area may be required when the size of data to be written is larger than the storage space of the memory provided in the memory.

If no additional storage area is needed (e.g., if the size of the data to be written is smaller than the storage area of the memory provided by itself), the process proceeds to step 1710 again. In this case, data that needs to be recorded will be recorded in a memory connected to the additional control unit 1705 or provided in the additional control unit 1705.

If the additional storage area is needed, the controller 1705 proceeds to step 1720 and the additional controller 1705 transmits a data bus occupancy permission request to the main controller 1440. The bus occupancy permission request is a request to occupy a specific bus in order to record arbitrary data in an arbitrary memory (that is, a memory dependent on the other additional control unit 1705 or a memory dependent on the main control unit 1440).

The main controller 1440 determines whether there is a bus (that is, a bus in a free state) that can be occupied by the additional controller 1705 in step 1725.

If the bus exists, the main controller 1440 transmits bus occupancy permission information to the additional controller 1705 in step 1730. According to the bus occupancy allowance information, the bus may be occupied only by the additional control unit, and the other additional control unit may not occupy the bus until the additional control unit releases the occupation.

In step 1735, the additional control unit 1705 transmits data to be recorded to the corresponding memory through the bus corresponding to the bus occupancy permission information to be recorded.

As described above, according to the conventional memory sharing structure, the main controller 1440 should perform bus control on all the additional controllers 1705. Therefore, since the main controller 1440 needs to have a bus controller, its configuration becomes complicated, and since the bus control for all additional controllers has to be performed, there is a problem in that processing efficiency of its own function is lowered.

In addition, when the main control unit 1440 controls the second additional control unit to access a specific memory controlled by the first additional control unit, the memory may exist inside the first additional control unit or may be located within the first additional control unit. Since the first additional control unit receives data from the second additional control unit and stores the data in the subordinate memory. In this case, the first additional control unit needs to perform a function of storing data generated by the second additional control unit instead of its own function, thereby causing power consumption and processing efficiency reduction due to unnecessary function execution.

18 is a diagram illustrating a memory sharing structure according to an embodiment of the present invention.

As illustrated in FIG. 18, a digital processing apparatus such as a portable terminal for performing a method of allowing individual memory access according to the present invention includes a main controller 1830 and a first and a second unit coupled to a main controller through a bus, respectively. The controller 1810 and 1820 and the first and second additional memories 1870 that depend on the first and second additional controllers 1810 and 1820, respectively.

Here, the main controller 1830 may be a processor that controls the overall operation of the portable terminal and may give an arbitrary command (for example, an operation start command or an operation end command) to each additional control unit. Although not shown in FIG. 18, the main controller 1830 may be combined with a separate main memory or include a main memory.

Also, the additional controllers 1810 and 1820 may be dedicated processors for processing MPEG4, 3D graphics, camera functions, and the like. In addition, in FIG. 18, only two additional controllers are assumed, but the number of additional controllers may be added or subtracted according to the types of functions included in the portable terminal.

In addition, it is easy to understand that the portable terminal to which the present invention can be applied is not limited to a specific type of terminal, but may be equally applicable to a digital processing apparatus including the main controller 1830, a plurality of additional controllers, and respective memories. Could be.

Each additional control unit 1810 or 1820 includes a bypass logic performing unit 1840 or 1850 for controlling whether an interface to a dependent additional memory 1860 or 1870 is performed. The bypass logic execution unit 1840 or 1850 may operate the additional memory 1860 or 1870 according to whether the additional control unit 1810 or 1820 is operated or inoperative (that is, whether the additional control unit uses the corresponding additional memory). Enable Bypass Logic to change the user's principal. In other words, the bypass logic performing units 1840 and 1850 may perform additional memory corresponding to data to be generated or processed by the additional control units 1810 and 1820 when the additional control units 1810 and 1820 are driven. If the additional controllers 1810 and 1820 are in a non-driven state, data transmitted from the main controller 1830 or the other additional controllers is stored in the additional memories 1860 and 1870. Set the path to be stored in. For example, when the additional control unit performs a camera function, if the execution of the camera function is not selected by the user, the additional control unit may be referred to as a non-driven state. In this case, the additional controller may be regarded as only a bridge that physically connects the main controller 1830 or the other additional controller with the additional memory.

In addition, since the additional control unit serves only as a bridge, it is not necessary to perform data reception and storage operation of the received data as in the conventional memory sharing structure, thereby eliminating unnecessary power consumption. If the controllers are implemented with, for example, CMOS ICs, no switching of the clock occurs and thus no power consumption can be seen.

In addition, the main controller 1830 or the other additional controllers have an effect of increasing the total amount of available memory even without additional memory expansion. The additional control unit may transmit corresponding state information to the main control unit 1830 when the non-driven state (eg, the sleep mode) is switched. Of course, the bypass logic execution unit 1840 or 1850 may be embedded in each additional control unit 1810 or 1820 in the form of any program for driving the bypass logic.

Each of the additional memories 1860 and 1870 may be an SRAM, an SDRAM, or the like, and may be embedded in each of the additional controllers 1810 and 1820.

As described above, in the present invention, since the main control unit combined with the plurality of additional control units does not need to perform the bus control function, the configuration of the main control unit is simplified and the number of processing operations is reduced, thereby reducing the load and subordinate to each control unit. The system interface is simplified because it is not necessary to separately provide an interface (i.e., a separate interface for writing data to the memory) connected to the memories.

As such, the main control unit does not need a separate interface for directly connecting to the additional memory by performing direct logic with each additional control unit, and thus requires a bus controller. The main system does not need to have a bus controller.

Features of the memory sharing structure according to the present invention compared to the conventional memory sharing structure will be easily understood through the following description.

19 is a diagram illustrating a process of storing processing data of a main controller in a memory dependent on an additional controller of a non-driven state according to an exemplary embodiment of the present invention.

Referring to FIG. 19, in operation 1910, the first additional controller 1810 determines whether a current state is a non-driven state or a non-driven state, which is the default. For example, when the first additional control unit 1810 is a component that performs a camera function, when the user is requested to execute the camera function, the first additional control unit 1810 is switched to a driving state. Of course, even when the first additional control unit 1810 is being driven, the first additional memory 1860 may not occupy a bus for storing arbitrary data. In this case, since the first additional control unit 1810 does not need to monopolize the first additional memory 1860, the first additional memory 1860 may be processed in the same manner as in the non-driven state. That is, when the current state of the first additional control unit 1810 is a non-drive state that is the default, the first additional memory 1860 is in the driving state even when the first additional control unit 1810 is in a driving state. Since the bypass logic can be performed when there is no need to write data to the first additional memory 1860, and so on, the following description will be referred to collectively as " a non-driven state. &Quot; do.

In the driving state, the data processed by the first additional controller 1810 or the data to be processed are stored in the first additional memory 1860.

In the case of switching to the non-driven state, etc., the first additional control unit 1810 drives the bypass logic in step 1915. When the bypass logic is driven, the route of the first additional memory 1860, which is dependent on the first additional control unit 1810, is directly connected to the main control unit 1830. This is because the first additional control unit 1810 is not driven, so there is no data processed or to be processed by the first additional control unit 1810, so that the first additional control unit 1810 and the first additional memory 1860 are connected. Because there is no need to keep it. The first additional control unit 1810 may transmit state information indicating that the first additional control unit 1810 has been switched to the non-driven state (the additional memory is not used) to the main control unit 1830 and / or the other additional control unit.

The main controller 1830 determines whether an additional storage area is required to perform the function uniquely assigned in step 1920 and to store the data processed or to be processed in step 1925. For example, when the main controller 1830 performs a function such as playing a video, an additional storage area may be needed because of the size of data to be processed or processed. Of course, when performing the function, even if the storage area is not insufficient, an additional storage area may be attempted to increase processing efficiency.

If an additional storage area is required, the main controller 1830 recognizes that the first additional controller 1810 is in a non-driven state (or the additional memory is not used) in step 1930 and removes the data to be stored. 1 is transmitted to the first additional memory 1860 subordinate to the additional control unit 1810. In addition, when the first controller 1830 intends to use the first additional memory 1860, the main controller 1830 may transmit state information indicating occupying the corresponding bus to the additional controllers.

In operation 1935, the first additional memory 1860 stores data transmitted from the main controller 1830. In this process, the first additional control unit 1810 performs a bypass logic to set the path in a form in which the first additional memory 1860 and the main control unit 1830 are directly connected (that is, as a bridge). As in the memory sharing structure, it is not necessary to perform a series of processes for receiving arbitrary data from the main controller 1830 and storing the received data in the first additional memory 1860. Therefore, it is possible to minimize processing time, power consumption, and the like, which are conventionally generated by unnecessary processing.

The method of allowing the main controller 1830 and the additional memory dependent on the additional control unit to be directly connected to the case where the arbitrary additional control unit is switched to the non-driven state has been described with reference to FIG. 19. In addition, the case in which the additional control unit transmits state information to the main control unit 1830 has been described.

However, the main controller may directly recognize whether the connected additional controllers are driven and whether the dependent additional memories are used, so that when the additional controller is switched to the non-driven state or when the additional controller is not used, the main controller is applicable. The bypass logic execution command may be transmitted to the additional control unit so that the bypass logic is executed by the corresponding additional control unit. In addition, the configuration as described above will be easily understood by those skilled in the art through the above description and a separate description thereof will be omitted.

FIG. 20 is a diagram illustrating a process of storing processing data by a second additional control unit in a memory dependent on a first additional control unit in a non-driven state according to another exemplary embodiment of the present invention.

Referring to FIG. 20, in operation 1910, the first additional control unit 1810 determines whether the current state is the default non-drive state or the non-drive state. For example, when the first additional control unit 1810 is a component that performs a camera function, when the user is requested to execute the camera function, the first additional control unit 1810 is switched to a driving state. In addition, the same result may be obtained when the first additional controller 1810 is not driven but does not occupy a bus for storing arbitrary data in the first additional memory 1860. same. Therefore, duplicate description thereof will be omitted.

In the driving state, the data processed by the first additional controller 1810 or the data to be processed are stored in the first additional memory 1860.

In the case of switching to the non-driven state, etc., the first additional control unit 1810 drives the bypass logic in step 1915. When the bypass logic is driven, the route of the first additional memory 1860, which is dependent on the first additional control unit 1810, is directly connected to the main control unit 1830. This is because it is not necessary to maintain the connection relationship between the first additional control unit 1810 and the first additional memory 1860 as described above. The first additional control unit 1810 may transmit state information indicating that the first additional control unit 1810 has been switched to the non-driven state (or the first additional memory 1860 is not used) to the main control unit 1830 and / or the other additional control unit. .

In operation 2010, the second additional controller 1820 determines whether an additional storage area is required to perform a uniquely allocated function and store data processed or processed in operation 2015. For example, when the second additional controller 1820 performs a function such as playing a video, an additional storage area may be needed because of the size of data to be processed or processed. Of course, when performing the function, even if the storage area is not insufficient, an additional storage area may be attempted to increase processing efficiency.

If an additional storage area is needed, the first additional control unit 1810 transmits a usable memory information request to the main control unit 1830 in step 2020.

The main controller 1830 may use the first additional memory dependent on the first additional control unit 1810 which is switched to the non-driven state in step 2025 or the first additional control unit 1810 may be driven, but the first additional memory may be used. The available memory information indicating that this is possible is transmitted to the second additional control unit 1820. In this case, the main control unit 1830 or the second additional control unit 1820 may add state information indicating that a bus for use of the first additional memory 1860 is occupied by the second additional control unit 1820. May be sent to the network. Of course, if the first additional control unit 1810 switched to the non-driven state (or without using the first additional memory) also transmits the above-described state information to the second additional control unit 1820, steps 2020 and 2025 may be performed. May be omitted.

In operation 2030, the second additional controller 1820 transmits data to be stored to the first additional memory 1860, which is dependent on the first additional controller 1810.

In operation 2035, the first additional memory 1860 stores data transmitted from the second additional control unit 1820. In this process, the first additional control unit 1810 performs a bypass logic to set the path in a form in which the first additional memory 1860 and the second additional control unit 1820 are directly connected (that is, as a bridge). As in the conventional memory sharing structure, it is not necessary to perform a series of processes for receiving arbitrary data from the first additional control unit 1810 and storing the received data in the first additional memory 1860. Therefore, it is possible to minimize processing time, power consumption, and the like, which are conventionally generated by unnecessary processing.

Up to now, referring to FIG. 20, a method of allowing another additional control unit and an additional memory dependent on the additional control unit to be directly connected in a case where an arbitrary additional control unit is switched to a non-driven state has been described. In addition, the case in which the additional control unit transmits state information to the main control unit 1830 and / or the other additional control unit has been described.

However, as described above, the main controller 1830 may directly recognize whether the connected additional controllers are driven and whether the dependent additional memories are used, so that the additional controller is switched to a non-driven state or any additional memory is used. If not, the main controller may transmit a bypass logic execution command to the corresponding additional control unit so that the bypass logic is executed by the corresponding additional control unit.

Memory interface sharing

In order for an electric / electronic device to perform a complex function, one or more storage devices for storing data and information necessary for performing a function are required. Storage devices include NAND flash memory and secure digital (SD) cards. NAND flash memory is a memory that is directly connected to a phone board of a mobile communication terminal and is not removable by a user. On the other hand, the SD card is a memory (Socket) is provided on the phone board is removable memory by the user.

An internal system of an apparatus consisting of a plurality of controllers and a plurality of memories is shown in FIGS. 21 and 22.

FIG. 21 is a diagram illustrating a configuration of a device in which a plurality of conventional memories are used, and FIG. 22 is a schematic block diagram of a conventional additional controller.

As shown in FIG. 21, an apparatus for performing a complex function is coupled between a main controller 22100 and an additional controller 2120 via a bus for transmitting and receiving arbitrary data and / or information. 2120 are each coupled with one or more memories. The bus BUS refers to a common purpose electrical passage used for transmitting and receiving information between each control unit, memory, etc. in the device.

The additional control unit 2120 may be combined with the SD card 2130 and the NAND flash memory 2140, and has an interface for combining with each of the memories 2130 and 2140. That is, the additional controller 2120 operates the plurality of memory interfaces provided as necessary to store multimedia data in an arbitrary memory or read and play the stored data.

Referring to FIG. 22, the additional control unit 2120 includes a processing unit 2210, a bus controller 2220, a first memory controller 2230, and a second memory controller 2240.

The processing unit 2210 performs a function (eg, MPEG4, 3D graphics, camera function, etc.) preset by the additional control unit 2120. In addition, the processor 2210 controls the bus controller 2220 by interpreting a command received from the main controller 22100 (which includes information on which interface to use) and transmitting the same to the bus controller. The processing unit 2210 may be a 32-bit processor.

The bus controller 2220 performs internal bus control to operate the first or second memory controllers 2230 and 2240 under the control of the processor 2210.

The first memory controller 2230 transmits and receives data and / or information with the SD card 2130 through the first memory interface. The first memory interface for coupling with the SD card 2130 provided in the additional controller is generally formed as a 9-pin interface. The 9-pin interface has four data signal pins (ie SD DAT0, SD DAT1, SD DAT2, SD DAT3) and five control signal pins (ie Clock (CLK) signal, Command signal, Card Detect) ) Signal, power control signal, and write protect signal.

The second memory controller 2240 performs a function of transmitting and receiving data and / or information with the NAND flash memory 2140 through the second memory interface. The second memory interface for coupling with the NAND flash memory 2140 included in the additional controller is generally formed as a 14-pin interface. The 14-pin interface has eight pins for data signals (ie NF Data0, NF Data1, NF Data2, NF Data3, NF Data4, NF Data5, NF Data6, NF Data7) and six pins for control signals (i.e. chip select (CS: Chip Select (CLE), Command Latch Enable (CLE), Address Latch Enable (ALE), Read Enable (REN), and Write Enable (WEN) , Write protection (WP) signal.

Thus, the conventional device must have all the memory interfaces that can be combined so that the 23 pins (i.e. 9 pins for SD card 2130 and 14 for NAND flash memory 2140) as illustrated in FIGS. 21 and 22 Dog pins) should be provided.

However, in most devices, the additional controller 2120 does not access a plurality of memories at the same time, but accesses only one memory or alternately. In addition, even if the main controller 22100 attempts to access the SD card 2130 or the NAND flash memory 2140, the two memories cannot be accessed at the same time. Considering these points, the additional control unit 2120 does not need to separately include two memory interfaces, but rather wastes resources.

In addition, this increases the physical size of the additional control unit 2120, resulting in a problem that increases the price.

FIG. 23 is a diagram schematically illustrating a configuration of an apparatus combined with a plurality of memories according to an exemplary embodiment of the present invention, and FIG. 24 is a schematic block diagram of an additional control unit according to an exemplary embodiment of the present invention. FIG. 25 is a diagram illustrating pin usage (pin muxing table) of a memory interface according to an exemplary embodiment of the present invention. FIG.

Referring to FIG. 23, in the apparatus according to the present invention for performing a complex function, the main control unit 2110 and the additional control unit 2120 are combined through a bus for transmitting and receiving arbitrary data and / or information. The additional control unit 2120 is combined with one or more memories. Bus refers to a common purpose electrical path used for transmitting and receiving information between each control unit, memory, etc. in the device.

The additional control unit 2120 may be combined with the SD card 2130 and the NAND flash memory 2140 as illustrated, and has a memory interface for combining with each of the memories 2130 and 2140. That is, the additional controller 2120 operates the plurality of memory interfaces provided as necessary to store multimedia data in an arbitrary memory or read and play the stored data. The memory interface included in the additional controller 2120 may include a first memory interface and a built-in memory (eg, NAND flash memory 2140) for transmitting and receiving signals independent of the removable memory (eg, the SD card 2130). And a second memory interface for independent signal transmission and reception, a removable memory or an internal memory, and a shared memory interface that is optionally shared for signal transmission and reception.

Removable memory that can be applied to the present invention is a removable memory through a socket (Socket) provided in the device, SD card, Compact Flash (CF) memory card, XD (eXtreme Digital Picture Card), MS (Memory Stick) This may include a Multi-Media Card (MMC). However, for convenience of explanation and understanding, it is assumed that two memories are coupled to the additional control unit, and the combined internal memory is a NAND flash memory, and the combined removable memory is an SD card.

In addition, the built-in memory that can be coupled to the additional memory means a memory which is provided inside the device like NAND flash memory and is not easily removable by a user.

Referring to FIG. 24, the additional controller 2120 according to the present invention may include a processing unit 2210, a bus controller 2220, a first memory controller 2230, a second memory controller 2240, and a path controller 2410. Include. Although not shown in FIG. 24, a memory interface is further included.

The processing unit 2210 performs a function (eg, MPEG4, 3D graphics, camera function, etc.) preset by the additional control unit 2120. In addition, the processor 2210 controls the bus controller 2220 by interpreting a command received from the main controller 2110 (which includes information on which interface to use) and transmitting the same to the bus controller. The processor 2210 may generate a path control signal for allowing the bus controller 2220 to set a path with an arbitrary memory and transmit the generated path control signal to the bus controller. The processing unit 2210 may be a 32-bit processor.

The bus controller 2220 performs internal bus control to operate the first or second memory controllers 2230 and 2240 under the control of the processor 2210. In addition, the bus controller 2220 controls the path controller 2410 such that the shared memory interface is coupled to the requested memory under the control of the processor 2210. When the bus controller 2220 receives the path control signal from the processor 2210, the bus controller 2220 activates the first or second memory controllers 2230 and 2240 to correspond to the path control signal, and transmits the path control signal to the path controller 2410. The memory interface enables the transmission and reception of information with the corresponding memory. The path control signal may be generated by the bus controller 2220 using information transmitted from the processor 2210 (that is, information interpreted from the command received from the main controller 2110). The first and second memory controllers 2230 and 2240 may be activated by default.

The first memory controller 2230 transmits a control signal to the SD card 2130 through the first memory interface. The signal transmitted to the SD card 2130 through the first memory interface may be limited to a signal that is not muxed with other signals (that is, a signal requiring an independent pin). For example, a signal transmitted to the SD card 2130 (that is, a data signal, a clock CLK signal, a command signal, a card detect signal, a power control signal, a write protection ( Since the only non-muxed signal (write protect) signal) is a clock signal, only the clock signal may be set to be transmitted through the first memory interface. Thus, the first memory interface may be configured with at least one pin for clock signal transmission. Also, for example, when the external memory is a Compact Flash (CF) memory card, the first memory interface may include at least two pins for a chip select (CS) signal and a clock (CLK) signal, which are non-muxed signals. have. For example, when the external memory is an eXtreme Digital Picture Card (XD), a Multi-Media Card (MMC), or the like, the first memory interface may include at least one pin for a clock signal that is a non-muxed signal. .

The second memory controller 2240 transmits a control signal to the NAND flash memory 2140 through the second memory interface. Signals transmitted to the NAND flash memory 2140 through the second memory interface may also be limited to signals that are not muxed with other signals. For example, a signal transmitted to the NAND flash memory 2140 (that is, a data signal, a chip select (CS) signal, a command latch (CLE) signal, an address latch enable (ALE) signal, and a read enable REN). The only non-muxed (non-pin shared) signal, the write enable (WEN) signal, or the write protect (WP) signal, is the chip select (CS) signal. However, since the number of pins required for the interface with the SD card 2130 is less than the number of pins (14) of the NAND flash memory 2140, there are additional signals that are not muxed as a result. For example, the additionally non-muxed signals may be an instruction latch (CLE) signal, an address latch enable (ALE) signal, a read enable (REN) signal, a write enable (WEN) signal, and a write protect (WP) signal. . The non-mux signals described above may be set to be transmitted to the NAND flash memory 2140 through the second memory interface. Thus, the second memory interface may be composed of six pins for transmitting each of the signals described above. Of course, if another memory requires more pins, the number of pins included in the second memory interface may be at least one (ie, pins for the chip select signal).

The path controller 2410 controls the data flow according to which memory is used by the control of the bus controller 2220. The path controller 2410 controls the shared memory interface to enable information transmission and reception between the first or second memory controllers 2230 and 2240 and the SD card 2130 or the NAND flash memory 2140. For example, the path controller 2410 may select only one of the signals provided from the first or second memory controller 2240 by the path control signal received from the bus controller 2220 and output the same through the shared memory interface. Can be. The shared memory interface includes pins for signals muxed among the signals transmitted and received with each of the memories 2130 and 2140.

As described above, although the additional control unit according to the present invention is combined with a plurality of memories, except for a few signals, each of the additional controllers may transmit / receive through the shared memory interface. The shared memory interface, that is, sharing pins, means that the circuit-shared pins are commonly connected to the respective memory 2130 and 2140. The pin usage (pin muxing table) of the memory interface according to the invention is illustrated in FIG. 25. As illustrated in FIG. 25, the number of the pins that the additional controller 2120 should include may be reduced to 15 by providing the shared memory interface. In the prior art, since each memory has an independent interface structure, a total of 23 pins were required, as described above.

Referring to FIG. 24, a process in which the main controller 2110 accesses the SD card 2130 and writes or reads data is briefly described as follows. Since the main controller 2110 accesses the NAND flash memory 2140 to write or read data, the description thereof will be omitted.

The main controller 2110 transmits a command and data to be recorded to the additional controller 2120 in order to record arbitrary data on the SD card 2130. The additional control unit 2120 activates the first memory controller 2230 with reference to the interface selection information included in the command, and also controls the path control unit 2410 to set a path to enable data transmission and reception with the SD card 2130. do. Subsequently, the additional controller 2120 stores the data received / received from the main controller 2110 in the SD card 2130 through a set path.

The main controller 2110 may also receive a method of reading arbitrary data from the SD card 2130 through a set path.

As described above, the present invention can minimize the data transfer time by allocating a dedicated area to each of the plurality of control units coupled to the shared memory, thereby optimizing the operation speed of each control unit.

In addition, the present invention also has the effect of optimal memory partitioning by allocating the storage area of the memory as a shared area and a dedicated area for each controller.

In addition, the present invention also has an effect of facilitating sharing of necessary data by sharing a single memory with a plurality of control units.

In addition, the present invention also has the effect of high-efficiency data processing by eliminating unnecessary time loss (transmission and reception) of data stored in a specific memory between each control unit.

In addition, the present invention also has the effect of minimizing the data transfer time between the controllers by dividing the storage area of the shared memory into a plurality of partitions and allowing access to a plurality of controllers in each partition.

In addition, according to the present invention, by allowing a plurality of controllers to access a storage area of a shared memory divided into a plurality of regions, each controller may be in charge of its own process, thereby optimizing the operation speed and efficiency of each controller. have.

In addition, the present invention also has an effect of easily controlling the shared memory in software by dividing the shared memory region.

In addition, the present invention also has the effect that the data is transferred immediately by the transfer of access rights only because a plurality of controllers can access the divided storage area of the shared memory cross (Access).

In addition, the present invention has the effect of simplifying the control sequence of each control unit by generating and outputting state information (that is, occupied state information) for the storage area in which the shared memory is divided.

In addition, according to the present invention, the main controller sequentially writes arbitrary data in the divided storage area of the shared memory, and the additional controller sequentially accesses the storage area recorded by the main controller to perform a read operation. By doing so, the data transfer speed can be maximized.

In addition, the present invention also has the effect that the operation of the plurality of additional control unit can be controlled by the main control unit of a simple configuration.

In addition, the present invention has the effect of optimizing the processing efficiency of the main memory by minimizing or minimizing the bus control function performed by the main memory.

In addition, the present invention can eliminate unnecessary processing operations for storing data generated or requested by the additional control unit in a memory in which the additional control unit in a non-drive state is dependent, thereby minimizing unnecessary power consumption.

In addition, the present invention has the effect of minimizing the processing time due to data storage when the data to be stored in the memory dependent on the additional control unit is omitted.

In addition, the present invention also has the effect of maximizing the available memory size that each control unit can use.

In addition, the present invention has the effect that bypass logic is applied which is much simpler than conventional bus control logic.

In addition, the present invention has the effect of simplifying the memory interface structure to be combined with a plurality of memories as possible.

In addition, the present invention has the effect of increasing the efficiency of the additional control unit by minimizing the number of pins included in the memory interface, and also reducing the operating current for driving the additional control unit.

In addition, the present invention has the effect of lowering the price of the additional control unit by simplifying the memory interface structure that can be integrated into a plurality of memories.

In addition, the present invention solves the problem of having to make pins for the functions that are not always used to the outside, and by opening only the path of the interface to use through memory interface sharing to operate only the appropriate logic There is also a possible effect.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (53)

In the digital processing device, A memory unit; Combined through the memory unit and an AP (Shared Memory) bus (BUS), the raw data stored in the memory unit accessed through the AP-SM bus is processed to correspond to a processing instruction. An additional control unit for storing the information; And A main control unit coupled to the memory unit through a Main Processor (MP) -SM bus, and coupled to the additional control unit through an MP-AP bus to transmit the processing command to the additional control unit through the MP-AP bus; But The storage area of the memory unit is divided into a first dedicated area accessible only by the additional control unit, a second dedicated area accessible only by the main control unit, a common area accessible by the additional control unit and the main control unit, and a variable area. The variable area is variably changed to be included in at least one of the first dedicated area, the second dedicated area, and the common area to correspond to area division information generated by one of the main control unit and the additional control unit. Device. The method of claim 1, The memory unit has a separate interface structure for transmitting and receiving information to and from the additional control unit through the AP-SM bus, and information to and from the main control unit through the MP-SM bus. The method of claim 1, The first control unit generates the area partitioning information and transmits the divided information to the second control unit through the MP-AP bus, wherein the first control unit is either the main control unit or the additional control unit, and the second control unit is the main control unit. Or the other of the additional control unit. The method of claim 3, The first control unit accessing the common area generates area repartitioning information when the size of data to be recorded is greater than the size of a recordable capacity of the common area, and generates the first dedicated area by the area repartitioning information. And a part or all of the variable regions included in one or more of the second dedicated regions are included as the common region so that the size of the common region is expanded. The method of claim 1, And the MP-SM bus of the AP-SM bus and the MP-SM bus has priority. The method of claim 1, And the processing instruction includes instruction information on a processing type of the raw data, and a storage location of the raw data. The method of claim 6, And the processing instruction further comprises location information for storing raw data processed to correspond to the indication information. And a memory controller, a main controller coupled to the memory unit via an MP-SM bus, and an additional controller coupled to the memory unit through an AP-SM bus and coupled to the main controller via an MP-AP bus. In the method of varying the partition size of the memory unit, Setting, by the main control unit, region division information for dividing a storage area of the memory unit into a plurality of division areas and transmitting the divided area information to the additional control unit, wherein the division area is a first dedicated access that is accessible only by the main control unit; An area, a second dedicated area accessible only by the additional control unit, a common area accessible by the main control unit and the additional main control unit, and a variable area, wherein the variable area includes the first dedicated area by the area partitioning information; Configured to be included in at least one of the second dedicated area and the shared area; Accessing the common area by the main controller to record arbitrary data; Determining, by the main controller, whether the size of data to be recorded is equal to or less than a size of a recordable area of the common area; And In the case of the above, the step of the main control unit to generate the area repartition information and transmits to the additional control unit, The variable region may include some or all of the variable regions included in at least one of the first dedicated region and the second dedicated region as the common region, thereby expanding the size of the common region. Negative partition size variable method. The method of claim 8, Accessing the common area by the additional control unit to record arbitrary data; Determining, by the additional control unit, whether a size of data to be recorded is equal to or less than a size of a recordable area of the common area; And If the above, the additional control unit further comprises the step of transmitting an area repartition request to the main control unit, And the main controller generates the area repartitioning information in response to the area repartitioning request, and the size of the common area is extended by the area repartitioning information. The method of claim 8, One of the main control unit and the additional control unit accessed to the common area transmits connection state information to the other of the main control unit and the additional control unit via the MP-AP bus. Way. In the digital processing device, A memory unit; An additional control unit coupled to the memory unit through an AP-SM bus and processing and storing raw data stored in the memory unit connected through the AP-SM bus according to a processing command; And Coupled to the memory unit via an MP-SM bus, coupled to the additional control unit via an MP-AP bus, to indicate the processing instruction including the instruction information on the processing type of the raw data and a storage location of the raw data; Including a main control unit for transmitting to the additional control unit via an MP-AP bus, The storage area of the memory unit is divided into a plurality of divided storage areas accessible by the additional controller through the AP-SM bus, and accessible by the main controller through the MP-SM bus. The memory unit includes a first port for transmitting and receiving information to and from the additional control unit through the AP-SM bus and a second port for transmitting and receiving information to and from the main control unit through the MP-SM bus. The method of claim 11, And when one of the main control unit or the additional control unit accesses any one of the divided storage areas, transmitting the access state information to the other of the main control unit or the additional control unit via the MP-AP bus. The method of claim 11, Area processing information corresponding to the size of the divided storage areas is set by either the main control unit or the additional control unit, and is digitally processed to be transmitted to the other of the main control unit or the additional control unit via the MP-AP bus. Device. The method of claim 11, And the processing instruction further comprises location information for storing raw data processed to correspond to the indication information. The method of claim 11, The plurality of divided storage areas may include a data transfer area for transferring data between the additional control unit and the main control unit. In a recording medium on which a program of instructions that can be executed by a digital processing apparatus is tangibly implemented to perform a multiple access control method of a partition of a shared memory, and in which a program can be read by the digital processing apparatus. The digital processing apparatus may include a main controller and an additional controller, wherein the main controller is coupled with a memory unit through an MP-SM bus, and the additional controller is coupled with the memory unit through an AP-SM bus. The main control unit and the additional control unit are coupled via an MP-AP bus, and the storage area of the memory unit is divided into a plurality of divided storage areas; In order for the first control unit, which is either the main control unit or the additional control unit, to access one of the divided storage areas, whether the second control unit which is the other of the main control unit or the additional control unit has already accessed the divided storage area. Determining whether or not; Accessing the partitioned storage area by the first controller when the second controller does not access the partitioned storage area; Recording, by the first control unit, arbitrary data in the accessed divided storage area; And And a program for executing the step of terminating access to the divided storage area by the first control unit. The method of claim 16, And a program for transmitting access state information to the second control unit through the MP-AP bus when the first control unit accesses any one of the divided storage areas. The method of claim 17, Area division information corresponding to the size of the divided storage areas is set by the first control unit, recording medium recording a program transmitted to the second control unit via the MP-AP bus. In the digital processing device, A memory unit divided into a plurality of divided storage regions, the memory unit including a first port and a second port; Coupled to the first port through an MP-SM bus, connected to any one of the divided storage areas through the MP-SM bus to record raw data, and then outputs a processing command of the raw data through an MP-AP bus. A main control unit; And The second port is coupled via the AP-SM bus, the MP-AP bus is coupled with the main controller, and the AP-SM bus is configured to correspond to the processing command received through the MP-AP bus. An additional control unit for reading and processing the raw data recorded in the divided storage area of the memory unit; Each of the divided storage areas may be accessed by the additional controller through the AP-SM bus, and the main controller may be accessed through the MP-SM bus. The additional control unit stores the divided data using the storage location information or the storage location information set as default depending on whether storage location information on which the raw data is recorded is received from the main control unit through the MP-AP bus. And read out the raw data recorded in the area. The method of claim 19, At least one of the plurality of divided storage areas is a data transfer area for transferring data between the additional control unit and the main control unit, And said raw data is recorded in said data transfer area. The method of claim 19, And the processing instruction includes instruction information on a processing type of the raw data and the storage location information. The method of claim 21, And the processing instruction further includes position information for storing the raw data processed to correspond to the indication information. The method of claim 19, When one of the main control unit or the additional control unit accesses any one of the divided storage areas, access state information is transmitted to the other of the main control unit or the additional control unit via the MP-AP bus. Digital processing unit. The method of claim 19, Area division information corresponding to the size of the divided storage areas is set by one of the main control unit and the additional control unit, and is transmitted to the other of the main control unit or the additional control unit through the MP-AP bus. Digital processing unit. In the digital processing device, Output device; a memory unit including m (any natural number of 2 to n (natural numbers of two or more)) divided storage areas; The output unit is coupled to the memory unit through an AP-SM bus, reads raw data recorded in an arbitrary divided storage area accessed through the AP-SM bus, processes the data corresponding to a processing instruction, and then outputs the output device. An additional control unit to be output through; And The additional control unit is coupled via the MP-AP bus to transmit the processing command to the additional control unit through the MP-AP bus, and is coupled through the memory unit and the MP-SM bus to transfer the raw data into the divided storage area. Including a main control unit for recording in, And the memory unit generates connection state information of the additional control unit or the main control unit for the divided storage area and transmits the connection state information to the additional control unit and the main control unit. The method of claim 25, And the additional control unit reads the raw data by accessing the divided storage area where the main controller releases the connection after recording the raw data with reference to the connection state information. The method of claim 25, The memory unit may include a first port for transmitting and receiving a control signal and the raw data to and from the additional controller through the AP-SM bus, and a source for transmitting and receiving the control signal and the raw data to and from the main controller through the MP-SM bus. Digital processing unit with 2 ports. The method of claim 25, And the additional control unit and the main control unit cannot be simultaneously connected to one divided storage area by the connection state information. The method of claim 25, Area division information corresponding to the size or quantity of the divided storage areas is set by a first control unit which is either the main control unit or the additional control unit, and the other of the main control unit or the additional control unit via the second bus. The digital processing device delivered to the second control unit. The method of claim 25, And the access state information is information about a writeable state and a readable state corresponding to the divided storage area. In order to perform a data transfer method between a plurality of controllers using one memory unit, programs of instructions that can be executed by a digital processing apparatus are tangibly implemented, and on a recording medium having recorded thereon a program that can be read by the digital processing apparatus. In (a) A memory unit comprising m (any natural number of 2 to n (natural numbers of 2 or more)) divided storage areas generates first connection state information of each divided storage area to generate the first bus and the second bus. Providing to the first control unit and the second control unit through; (b) the first control unit transmitting a processing instruction corresponding to any raw data to the second control unit via a third bus; (c) when the first controller accesses the first partitioned storage area through the first bus with reference to the first connection state information and starts writing the raw data, the memory unit divides the first partition. Transferring second connection state information indicating that a storage area is connected by the first control unit to the second control unit; (d) when the first control unit terminates access to the first divided storage area, the memory unit transferring third connection state information indicating that the first divided storage area is accessible to the second control unit; ; (e) when the second controller accesses the first partitioned storage area through the second bus with reference to the third connection state information and starts reading the raw data, the memory unit divides the first partition. Transmitting fourth connection state information indicating that a storage area is connected by the second control unit to the first control unit; And (f) a recording medium on which a program is executed by the second control unit for processing the read raw data to correspond to the processing instruction. The method of claim 31, wherein And the second controller is further configured to execute the step of causing the processed raw data to be output through the combined output device. The method of claim 31, wherein Determining, by the second control unit, whether reading of the raw data recorded in the first divided storage area is completed; And And when the reading is completed, the step of terminating the connection to the first divided storage area by the second control unit is executed after the step (f). The method of claim 31, wherein Step (d) is, Determining, by the first controller, whether all of the storage space of the first divided storage area is used up; When all are used, ending the connection to the first divided storage area by the first controller; The memory unit generates the third connection state information including information indicating that the first divided storage region is available and information on whether the second divided storage region is accessible, and generates the third connection state information to the first controller and the second controller. Delivering; When the second divided storage area is accessible by referring to the third connection state information, the first controller accesses the second divided storage area through the first bus to write the raw data. Performing continuously; And And generating, by the memory unit, fifth connection state information indicating that the second divided storage area is connected by the first control unit, and transferring the fifth connection state information to the second control unit. The method of claim 34, wherein Determining, by the second control unit, whether reading of the raw data recorded in the first divided storage area is completed; When the reading is completed, terminating the connection to the first divided storage area by the second controller; Transmitting, by the memory unit, sixth connection state information indicating that the first divided storage area is accessible to the first controller; Determining, by the second controller, whether the seventh connection state information indicating that the second divided storage area is in an accessible state is received from the memory unit; And When the seventh connection state information is received, the step of accessing the second divided storage area to continuously read the raw data is performed after step (f). Recording medium recording a program characterized by. In the digital processing device, An additional control unit which performs a preset additional function, wherein the additional function includes at least one of a camera function and a multimedia data reproduction function; An additional memory unit coupled or inserted to be slaved to the additional control unit; And A main control unit coupled to the additional control unit for controlling driving start or driving termination of the additional control unit, When the additional control unit does not occupy a bus corresponding to the additional memory, the main memory and the additional memory unit switch the route so that the additional memory unit is directly coupled. Digital processing device having a permissible structure. The method of claim 36, When the additional control unit does not occupy a bus corresponding to the additional memory, when the additional control unit enters a non-driven state, and when the additional control unit is in a driving state but does not use the additional memory. Digital processing apparatus having a separate memory access permission structure, characterized in that at least one of. The method of claim 36, The additional control unit includes bypass logic to switch the path, and the bypass logic is performed immediately after the additional control unit enters a non-driven state. The additional control unit has a separate memory access permission structure, characterized in that for transmitting the corresponding status information to the main control unit. The method of claim 36, The additional control unit includes bypass logic to switch the path, and the bypass logic detects that the additional control unit has entered a non-driven state by controlling the driving termination. And a separate memory access permission structure, which is performed by a command from the main controller. The method of claim 36, And the main control unit writes the processed or processed data to the additional memory unit through the path. In the digital processing apparatus including a plurality of controllers and at least one memory coupled to each controller dependently, In a method for allowing individual memory access to allow other controllers to use the memory dependent on any controller, Determining whether or not the additional control unit for performing the preset additional function occupies a bus corresponding to the combined additional memory; If it is not occupied, causing the additional control unit to perform bypass logic so that a route is switched such that the main control unit controlling the one or more additional control units and the additional memory unit are directly coupled; And And determining, by the main controller, whether an additional memory area is additionally needed, and storing data to be processed or processed in the additional memory unit coupled through the path, if necessary. The method of claim 41, wherein When the additional control unit does not occupy a bus corresponding to the additional memory, when the additional control unit enters a non-driven state, and when the additional control unit is in a driving state but does not use the additional memory. Individual memory access method, characterized in that at least one of. The method of claim 41, wherein And the additional control unit transmits corresponding state information to the main control unit after the bypass logic is executed. The method of claim 41, wherein The additional control unit determines whether the additional control unit occupies a bus corresponding to the additional memory by using whether the execution command of the bypass logic is received from the main control unit. How to grant access. In the digital processing apparatus including a plurality of controllers and at least one memory coupled to each controller dependently, In a method for allowing individual memory access to allow other controllers to use the memory dependent on any controller, Determining whether the first additional control unit for performing the preset first additional function occupies a bus corresponding to the combined first additional memory; If not occupied, a route is switched such that the first additional control unit performs bypass logic to control one or more additional control units and the first additional memory unit is directly coupled. Making it possible; Determining, by the second additional control unit for performing the second preset additional function, whether the available memory area is additionally needed; If necessary, requesting, by the second additional control unit, address information of any additional memory dependent on any additional control unit which is not driven; Receiving, by the second additional control unit, address information corresponding to the first additional memory from the main control unit; And And storing, by the second additional controller, the data to be processed or processed into the first additional memory corresponding to the address information using the path. In the additional processor of the digital processing apparatus including a main processor, an additional processor that performs a predetermined additional function set by the control of the main processor and is coupled to a plurality of memories, A processing unit to perform the preset additional function; A path controller configured to set an information transmission / reception path with any one of a first memory and a second memory coupled through a shared memory interface under the control of the processing unit; A first memory controller configured to transmit and receive information to and from the first memory through a first memory interface and the path controller; And A second memory controller configured to transmit and receive information to and from the second memory through a second memory interface and the path controller, If the total number of pins for the interface with the first memory is n (natural number), and the total number of pins for the interface with the second memory is m (natural number greater than n), The shared memory interface includes k (natural numbers) pins, any one of 1 to n-1, the first memory interface includes nk pins, and the second memory interface includes mk pins. An additional processor, characterized in that. 47. The method of claim 46 wherein Further comprising a bus controller for performing a bus control by the control of the processing unit, And the path controller sets the information transmission / reception path by a path control signal received from the bus controller. 47. The method of claim 46 wherein The first memory interface and the second memory interface include one or more pins for transmitting at least one of a clock (CLK) signal and a chip select (CS) signal. 47. The method of claim 46 wherein The first memory is any one of an internal memory and a removable memory, and the second memory is the other of the internal memory and the removable memory. The method of claim 49, The removable memory may be any one of a Secure Digital (SD) card, a Compact Flash (CF) memory card, an eXtreme Digital Picture Card (XD), a Memory Stick (MS), and a Multi-Media Card (MMC). In the memory interface sharing method performed by the additional processor of the digital processing device including a main processor, an additional processor to perform a predetermined additional function set by the control of the main processor and coupled to a plurality of memories, Receiving a request for memory access to either internal memory or removable memory from the main processor; Establishing a path for access to a memory corresponding to the request; And Delivering data received from the main processor to a corresponding memory through the set path; The path is established through a separate memory interface that is independently coupled to a memory corresponding to the request and a shared memory interface shared by a plurality of memories, The total number of pins for interface with the internal memory coupled to the additional processor is n (natural number), and the total number of pins for interface with the removable memory coupled to the additional processor is m (natural number greater than n) In the individual case, the shared memory interface includes k (natural numbers) pins, any one of one to n-1, and the separate memory interface for the internal memory includes nk pins, and the separate for the removable memory. Wherein the memory interface comprises mk pins. The method of claim 51, Each of the individual memory interfaces comprises one or more pins for transmitting at least one of a clock (CLK) signal and a chip select (CS) signal. In the recording medium on which a program of instructions that can be executed by a digital processing apparatus for performing a memory interface sharing method is tangibly implemented, and a program that can be read by the digital processing apparatus, The additional processor receiving a request for access to any memory from the main processor; Establishing a path for access to a memory corresponding to the request, wherein the path is established through a separate memory interface independently connected to a memory corresponding to the request and a shared memory interface shared to a plurality of memories -; And The step of transferring the data received from the main processor to the corresponding memory through the set path, The digital processing apparatus includes the main processor and the additional processor configured to perform an additional function preset by the control of the main processor, wherein the additional processor is simultaneously coupled to an internal memory and a removable memory, The total number of pins for interface with the internal memory coupled to the additional processor is n (natural number), and the total number of pins for interface with the removable memory coupled to the additional processor is m (natural number greater than n) In the individual case, the shared memory interface includes k (natural numbers) pins, any one of one to n-1, and the separate memory interface for the internal memory includes nk pins, and the separate for the removable memory. And a memory interface comprising mk pins.

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