KR20070118752A - The converter using digital soft start circuit - Google Patents

Abstract

A converter using a digital soft start circuit is provided to remove a capacitor from the outside of a PWM(Pulse Width Modulation) controlling unit to reduce cost and noise. A converter using a digital soft start circuit includes a main switch(M), a PWM(Pulse Width Modulation) controlling unit(2), and a soft start(1). The PWM controlling unit controls the on/off of the main switch. The soft start is applied with a clock signal(CLK) having a first cycle, generates a first digital control signal, generates soft start voltage(Vss) corresponding to the first digital control signal, transmits the soft start voltage to the PWM controlling unit, feeds back the first digital control signal, generates a control signal by using the first digital control signal and the clock signal, generates a second digital control signal according to the generated control signal, and generates soft start voltage corresponding to the second digital control signal.

Description

Converter using digital soft start circuit {THE CONVERTER USING DIGITAL SOFT START CIRCUIT}

1 is a view showing a converter according to an embodiment of the present invention.

2 illustrates a soft start according to an embodiment of the present invention.

3 illustrates a soft start voltage according to a 4-bit digital control signal according to an embodiment of the present invention.

4 illustrates waveforms of a soft start voltage, a sensing voltage, a clock signal, a pulse width modulation signal, and a gate control signal according to an exemplary embodiment of the present invention.

The present invention relates to a converter using soft start.

In the output stage of a conventional converter, a capacitive load component is generally present, which causes the output voltage to rise with a constant time constant during the initial operation of the converter. Therefore, the feedback signal becomes the maximum value at the initial operation of the converter. Also, during this time, the drain current of the transistor that is the switching element is maintained at the peak value.

In this way, when the maximum power is delivered to the secondary side for a certain period of time at the beginning of operation, severe stress is generated in the entire circuit. Thus, soft start is used to avoid this operation, and conventionally, a capacitor has been added outside the device that controls the pulse width modulate for this soft start function.

However, the use of external capacitors is weak to noise and incurs the additional cost of using external capacitors.

The present invention has been made to solve such a conventional problem, and an object thereof is to provide a converter including a digital soft start therein.

In order to achieve this technical problem, a converter including a pulse width modulate (PWM) control unit for controlling a main switch and a main switch on / off according to an aspect of the present invention, the clock signal having a first period is input Generate a first digital control signal, generate a soft start voltage corresponding to the first digital control signal, transfer the soft start voltage to the PWM controller, and feed back the first digital control signal. Generate a control signal using the first digital control signal and the clock signal, generate a second digital control signal according to the generated control signal, and generate a soft start voltage corresponding to the second digital control signal. It includes soft start.

The soft start may include a counter for generating a second digital control signal according to the control signal, wherein the counter may include the second digital control in a section in which the control signal has a second period, in a section longer than or equal to a second period. Keep the signal.

The soft start further includes a counter control unit generating the control signal using the first digital control signal and the clock signal, wherein the counter control unit performs a logical operation on a logic value of each bit of the first digital control signal. The control signal is generated using the operation result signal and the clock signal corresponding to the operation result.

In the converter comprising a main switch according to another aspect of the invention and a PWM control unit for determining the on / off of the main switch, generating a digital control signal, and generates a soft start voltage corresponding to the digital control signal, And a soft start for transmitting the soft start voltage to the PWM control unit and feeding back the digital control signal to change the digital control signal, wherein the PWM control unit includes a feedback corresponding to the output voltage of the converter. A gate control signal for controlling on / off of the main switch is generated using a signal, a sensing voltage corresponding to a current flowing through the main switch, a clock signal having a first period, and the soft start voltage.

The soft start includes a counter for generating the digital control signal in accordance with a control signal, a D / A converter for generating the soft start voltage in accordance with the digital control signal output from the counter, and the digital control signal and the clock signal. And a counter controller for generating the control signal.

The counter control unit receives the digital control signal, performs a logic operation on a logical value corresponding to each bit of the digital control signal, and generates a calculation result signal according to a calculation result, and the calculation result signal. And a second logic unit configured to receive the clock signal and generate a control signal having a different level according to the level of the operation result signal and the clock signal.

The PWM controller compares the soft start voltage and the sensed voltage, compares the first comparator, the feedback signal, and the sensed voltage to generate a first comparison result signal according to a comparison result, and compares the second voltage according to the comparison result. A second comparator for generating a comparison result signal, a third logic for receiving the first and second comparison result signals, performing a logic operation on the first and second comparison result signals, and determining an output signal level according to the operation result When the output signal of the third logic unit is input, the clock signal and the output signal of the third logic unit are respectively input. When the output signal of the third logic unit is a first level, a pulse width modulation signal of a second level is generated, and the clock signal is a third level. In this case, the pulse width modulation signal generation unit and the phase where the level of the pulse width modulation signal in the previous state is maintained and the clock signal is the fourth level, and the pulse width modulation signal becomes the fifth level. And a control signal generator configured to receive a pulse width modulation signal and the clock signal to generate an on / off control signal of the main switch.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only the "directly connected" but also the "electrically connected" between other elements in between. In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention may be easily implemented by those skilled in the art with reference to the accompanying drawings.

First, the structure of a converter according to an embodiment of the present invention will be described with reference to FIG. 1.

1 is a view showing a converter according to an embodiment of the present invention.

As shown in FIG. 1, a converter according to an exemplary embodiment of the present invention includes a soft start 1, a resistor Rsense, a main switch M, and a pulse width modulate (PWM) control unit 2. ).

The PWM controller 2 includes a clock generator 21, a first comparator 23, a second comparator 22, an OR gate 24, a flip-flop 25, and a logic calculator 26.

The soft start 1 receives the clock signal CLK from the clock generator 21 and generates a digital control signal. The soft start voltage Vss of a constant level is transmitted to the first comparator 3 according to the generated digital control signal.

The PWM controller 2 determines the duty ratio of the main switch according to the output voltage of the converter. The PWM controller 2 gradually increases the duty ratio of the main switch M by using the voltage input from the soft start 1 when the converter is started up.

The clock generator 21 generates a clock signal CLK having a predetermined period and transmits the clock signal CLK to the soft start 1, the flip-flop 25, and the logic calculator 26.

The first comparator 23 is connected to one end of the soft start 1 and the resistor Rsense, respectively, to receive the soft start voltage Vss through the inverting terminal (-), and to sense the voltage (S) by the non-inverting terminal (+). Vsense). The sensing voltage Vsense has a level corresponding to the current Idrain flowing in the drain of the main switch M. FIG. The first comparator 23 generates a comparison output signal C1 according to the comparison result of the soft start voltage Vss and the sense voltage Vsense. When the sense voltage Vsense becomes equal to or greater than the soft start voltage Vss, the first comparator 3 generates a first comparison output signal C1 having a high level, and the sense voltage Vsense becomes the soft start voltage Vss. If less, the low level comparison output signal C1 is generated.

The second comparator 22 receives the feedback signal and the sense voltage Vsense corresponding to the output power of the output terminal of the converter, and generates the second comparison output signal C2 according to the comparison result. The feedback signal according to the embodiment of the present invention is a feedback voltage Vfb corresponding to the output power. The second comparator 22 transmits the second comparison output signal C2 to the reset terminal R of the flip-flop 25. The feedback voltage Vfb and the sense voltage Vsense are transferred to the inverting terminal (-) and the non-inverting terminal (+), respectively, and when the sense voltage Vsense is equal to or greater than the feedback voltage Vfb, the second comparative output of high level is output. The signal C2 is transmitted to the reset terminal R of the flip flop 25. When the sensing voltage Vsense is less than the feedback voltage Vfb, the second comparison output signal C2 having a low level is transmitted to the reset terminal R of the flip-flop 25.

The OR gate 24 receives the first comparison output signal C1 and the second comparison output signal C2 from the first comparator 23 and the second comparator, respectively, and performs an OR operation. The output signal OS1 having the level is transferred to the reset terminal R of the flip-flop 25.

The flip-flop 25 is connected to the clock generator 21, the OR gate 24, and the logic calculator 26. The set terminal S is connected to the clock generator 21 to receive the clock signal CLK, and the reset terminal R is connected to the OR gate 24. The pulse width modulated signal Sp is generated by performing a logic operation on the signals input to the set stage S and the reset stage R. When the high level signal is input to the reset terminal R, the flip-flop 25 according to the embodiment of the present invention outputs a low level pulse width modulation signal Sp to the inverting output terminal / Q, and sets the stage. The pulse width modulation signal Sp having a high or low level is output to the inverting output terminal / Q according to the level of the signal input to (S). When the high level clock signal is input to the set stage, the low level pulse width modulation signal Sp is outputted. When the low level clock signal is inputted, the pulse level modulation signal Sp having the same level as the previous stage is output. The flip-flop 25 outputs the generated pulse width modulated signal Sp to the logic operation unit 26 through the inverted output terminal / Q.

The logic calculator 26 is connected to the flip-flop 25 and the clock generator 21 to generate a gate control signal Sg by performing a logic operation on the pulse width modulated signal Sp and the clock signal CLK. The logic calculator 26 according to an embodiment of the present invention may be a NOR gate, and the logic calculator 26 performs an NOR operation on the pulse width modulation signal Sp and the clock signal CLK to generate a gate control signal Sg. Create

The main switch M is turned on / off in accordance with the gate control signal Sg of the logic calculating section 26. The main switch M according to an exemplary embodiment of the present invention is an N-channel transistor. When the gate control signal Sg is at a high level, the main switch M is turned on.

The sensing resistor Rsense generates a sensing voltage Vsense in response to a current flowing in the drain of the main switch M. FIG.

Hereinafter, with reference to FIG. 2, the soft start 1 is demonstrated concretely.

2 shows a soft start 1 according to an embodiment of the present invention.

As shown in FIG. 2, the soft start 1 includes a counter 11, a counter control unit 12, and a D / A converter 13. The counter controller 12 includes an AND gate 121 and a NAND gate 122.

The counter 11 is connected to the AND gate 121 of the count control unit 12 and counts again from the beginning according to the reset signal Sr. The counter 11 according to the embodiment of the present invention generates the same 4-bit digital control signal for a predetermined time and outputs it to the D / A converter 13. At this time, the 4-bit digital control signal has a magnitude increasing sequentially. The counter 11 sequentially increases the size of the 4-bit digital control signal in accordance with the counter control signal CC output from the AND gate 12. The counter control signal CC according to the embodiment of the present invention has a constant period, alternately has a high level and a low level, and maintains a low level when the 4-bit digital control signal becomes '1111'. The counter 11 increases the magnitude of the 4-bit digital control signal every four periods of the counter control signal CC, and maintains the 4-bit digital control signal with a constant magnitude for four periods. In the period where the counter control signal CC is maintained at the low level, the 4-bit digital control signal is maintained as '1111'.

The counter control unit 12 generates a counter control signal using the clock signal CLK and a 4-bit digital control signal. The counter controller 12 according to the embodiment of the present invention includes an AND gate 121 and a NAND gate 122. The AND gate 121 receives the operation result signal L1 output from the clock signal CLK and the NAND gate 122, and outputs a counter control signal CC according to the AND operation result. The NAND gate 122 performs a NAND operation on the 4-bit digital control signal to generate a signal L1 according to the calculation result, and transfers the signal L1 to the AND gate 121.

The D / A converter 13 outputs a constant level of soft start voltage in accordance with the 4-bit digital control signal input. The D / A converter 14 according to the embodiment of the present invention outputs a soft start voltage of 24 (= 16) steps in response to a 4-bit digital control signal. Although the D / A converter 14 according to the embodiment of the present invention is illustrated as having a soft start voltage having the same interval according to the 4-bit digital control signal, it is possible to generate a soft start voltage having a different interval according to the setting. have. Specifically, the D / A converter 14 using a plurality of series resistors has the same resistance value when the soft start voltage increases with a constant interval proportional to the magnitude of the 4-bit digital control signal. It can be composed of a resistor having. As described above, the resistance values of the plurality of series resistors may be set differently so that the soft start voltages may be increased at different intervals.

The reset signal Sr controls the time point at which the soft start is started. When the reset signal occurs polling timing, the counter generates a 4-bit digital control signal '0000' through '1111'. Specifically, the reset signal Sr according to the embodiment of the present invention becomes a high level pulse at the start-up time of the converter, and the counter is 4-bit digitally controlled at the timing of polling the reset signal Sr. Start to generate signal '0000'. The remaining level is maintained at the low level. When the start up occurs again, the pulse is at the high level again.

3 illustrates a soft start voltage according to a 4-bit digital control signal according to an embodiment of the present invention.

As shown in FIG. 3, when a start-up occurs and a falling timing of the reset signal occurs, a soft start voltage of 0.1 V is generated by a 4-bit digital control signal of '0000'. After a constant period of time by the counter, the soft-start voltage rises due to the 4-bit digital control signal of '0001'. In this manner, the soft-start voltage rises to 0.3V by the 4-bit digital control signal '1111'. After that, the soft start voltage is maintained at a level corresponding to the 4-bit digital signal '1111' until the reset signal Sr becomes a high level pulse again, and the comparison output signal of the first comparator 23 is maintained at a low level. . When a situation such as start up occurs again, the timing of the reset signal is generated again, and the soft start voltage is sequentially raised by the 4-bit digital control signal.

Hereinafter, the operation of the converter according to the embodiment of the present invention will be described with reference to FIG. 4.

4 illustrates waveforms of a soft start voltage, a sensing voltage, a clock signal, a pulse width modulation signal, and a gate control signal according to an exemplary embodiment of the present invention.

As shown in Fig. 4, the soft start voltage rises according to the 4-bit digital control signal. The sense voltage Vsense becomes equal to the soft start voltage at the time T1, and then the first comparison output signal C1 becomes a high level. The high level output signal OS1 is generated at the OR gate 24 by the first comparison output signal C1 having a high level, and the generated output signal OS1 is transferred to the reset terminal R. When the high level output signal OS1 is input to the reset terminal R, the pulse width modulation signal Sp becomes a high level, and the logic calculating unit 26 supplies the low level gate control signal Sg to the main switch (S). To M). Then, the main switch M is turned off and the sensing voltage Vsense becomes zero. At the time point T2 input to the set end S of the flip-flop 25, when the clock signal CLK becomes high level, the pulse width modulated signal Sp becomes low level. When the polling timing of the clock signal CLK occurs at the time point T3 to reach the low level, the pulse width modulation signal Sp is maintained at the low level. The logic calculator 26 receives a low level clock signal and a pulse width modulation signal to generate a high level gate control signal Sg. The main switch M is turned on according to the high level gate control signal Sg, and the sensing voltage is generated again. This operation is repeated, and the counter control signal CC according to the embodiment of the present invention has the same waveform as the clock signal CLK until the 4-bit digital control signal becomes '1111'. Accordingly, the soft start voltage is increased by one step at the time T4 when four periods of the clock signal CLK pass and the polling timing of the clock signal CLK occurs.

As such, the converter according to the embodiment of the present invention may generate a soft start voltage that sequentially increases according to the digital signal.

The drawings and detailed description of the invention are merely exemplary of the invention, which are used for the purpose of illustrating the invention only and are not intended to limit the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the present invention provides a converter capable of sequentially increasing the soft start voltage according to a digital control signal.

In addition, since the present invention does not use a capacitor externally, it provides a cost-saving and noise-resistant converter.

Claims (18)

In the converter comprising a main switch and a pulse width modulate (PWM) control unit for controlling the on / off of the main switch, A clock signal having a first period is input, generates a first digital control signal, generates a soft start voltage corresponding to the first digital control signal, transfers the soft start voltage to the PWM controller, Feedbacking a first digital control signal, generating a control signal using the first digital control signal and the clock signal, generating a second digital control signal according to the generated control signal, and generating the second digital control signal. And a soft start for generating a soft start voltage corresponding to the signal. The method of claim 1, The soft start, A counter for generating a second digital control signal according to the control signal, The counter, And a converter for maintaining the second digital control signal in a section longer than a second period in a section in which the control signal has a second period. The method of claim 2, The soft start, And a counter controller configured to generate the control signal using the first digital control signal and the clock signal. And the counter controller performs a logic operation on a logic value of each bit of the first digital control signal, and generates the control signal using an operation result signal and a clock signal corresponding to the operation result. The method of claim 3, The soft start, And a D / A converter for generating a soft start voltage according to the first and second digital control signals. The method of claim 4, wherein The D / A converter uses a plurality of resistors connected in series, and an increase in the soft start voltage varies according to resistance values of the plurality of resistors. The method of claim 3, The counter, And a converter for generating an initial digital control signal in accordance with a reset signal for initializing the counter when the converter is started up. The method of claim 3, The control signal is fixed at a constant level when the second digital control signal has the highest logic value. And the counter keeps the second digital control signal. The method of claim 3, The PWM control unit, And a sensing voltage corresponding to a current flowing through the main switch and a soft start voltage generated at the soft start, and determining to turn off the main switch according to a comparison result. The method of claim 8, The PWM control unit, And turning off the main switch if the sensed voltage is greater than the soft start voltage. The method according to any one of claims 1 to 9, The second digital control signal has a larger logic value than the first digital control signal, and a soft start voltage corresponding to the second digital control signal is greater than a soft start voltage corresponding to the first digital control signal. Having a converter.  In the converter comprising a main switch and a PWM control unit for determining the on / off of the main switch, Generating a digital control signal, generating a soft start voltage corresponding to the digital control signal, transferring the soft start voltage to the PWM control unit, and feeding back the digital control signal to change the digital control signal. Including soft start to say, The PWM control unit, A gate control for controlling on / off of the main switch using a feedback signal corresponding to an output voltage of the converter, a sensing voltage corresponding to a current flowing through the main switch, a clock signal having a first period, and the soft start voltage Converter to generate a signal. The method of claim 11, The soft start, A counter for generating the digital control signal according to a control signal, A D / A converter generating the soft start voltage according to the digital control signal output from the counter; And a counter controller for generating the control signal according to the digital control signal and the clock signal. The method of claim 12, The counter control unit, A first logic unit configured to receive the digital control signal, perform a logical operation on a logical value corresponding to each bit of the digital control signal, and generate an operation result signal according to the operation result; And a second logic unit configured to receive the operation result signal and the clock signal and generate a control signal having a different level according to the level of the operation result signal and the clock signal. The method of claim 13, And the first logic portion is a NAND gate performing a NAND operation, and the second logic portion is an AND gain for performing an AND operation. The method of claim 13, The PWM control unit, A first comparator comparing the soft start voltage and the sensed voltage and generating a first comparison result signal according to a comparison result; A second comparator comparing the feedback signal and the sensed voltage and generating a second comparison result signal according to a comparison result; A third logic unit configured to receive the first and second comparison result signals, perform a logical operation on the first and second comparison result signals, and determine an output signal level according to the operation result; When the clock signal and the output signal of the third logic unit are respectively input, and if the output signal of the third logic unit is a first level, a pulse width modulation signal of a second level is generated, and if the clock signal is a third level, A pulse width modulated signal generator that maintains the level of the pulse width modulated signal in a previous state and the pulse width modulated signal becomes a fifth level if the clock signal is a fourth level; And a control signal generator configured to receive the pulse width modulation signal and the clock signal to generate an on / off control signal of the main switch. The method of claim 15, The first, second, and third levels are high levels, and the fourth and fifth levels are low levels. The method of claim 16, The pulse width modulated signal is, And a flip-flop converter configured to receive the clock signal through a set terminal, an output signal from the third logic unit through a reset terminal, and output the pulse width modulation signal to an inverted output terminal. The method of claim 16, And the third logic unit is an OR gate, and the control signal generator is a NOR gate.

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