KR20070116458A - Method of forming semiconductor device - Google Patents

Abstract

A method for forming a semiconductor device is provided to simplify processes and reduce a cost by forming silicide after forming a silicon pattern having the same thickness of a PMOS and an NMOS gate electrode. A first region and a second region are defined on a semiconductor substrate. Silicon patterns are formed on the first and the second regions respectively. A first metal layer is formed on the silicon patterns. A first metal silicide(130) is formed on the first and the second regions by performing a first silicide process. A second metal layer is formed on the first metal silicide within the first region. A second metal silicide(200) is formed on the first region by a second silicide process.

Description

Method of Forming Semiconductor Device {METHOD OF FORMING SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

2A through 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110: silicon pattern 115: interlayer insulating film

120: first metal film 130: first metal silicide

140: photoresist pattern 150: electroless plating metal film

200: second metal silicide

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device having an NMOS and a PMOS transistor.

When the gate electrode of the transistor is formed of polysilicon, polysilicon depletion and boron penetration occur.

When the gate electrode is formed of a metal material instead of polysilicon, the polysilicon depletion and boron penetration can be solved, but it is difficult to control the threshold voltage because it causes deterioration of the gate insulating layer due to metal ions and the work function is fixed. There is this. As a solution to this, a process of silicideing polysilicon of the gate electrode is proposed.

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

Referring to FIG. 1A, a semiconductor substrate 10 including a first region I and a second region II is prepared. The first region I and the second region II may be a PMOS region and an NMOS region. A gate insulating film 15 and a polysilicon film 20 are formed on the semiconductor substrate 10. After the polysilicon is formed on the gate insulating layer 15, a photoresist pattern (not shown) is formed on the first region (I), and the second region (II) is formed by a chemical dry etching process. Remove part of the polysilicon. A polysilicon film 20 having a difference in thickness is formed in the first region I and the second region II.

A silicon germanium film 22 is formed on the polysilicon film 20. Steps are formed in the silicon germanium film 22 due to the difference in thickness of the polysilicon film 20. A planarization process is performed on the silicon germanium layer 22. A mask layer 24 for gate patterning is formed on the silicon germanium layer 22. The mask layer 24 may be a silicon oxide layer or a silicon nitride layer.

Referring to FIG. 1B, gate patterns are formed in the first region I and the second region II, respectively. Spacers 26a and 26b are formed on sidewalls of the gate pattern, and source / drain regions 12a, 12b, 13a, and 13b are formed by an ion implantation process.

Referring to FIG. 1C, an interlayer insulating layer 30 covering the gate pattern is formed. The planarization process is performed on the interlayer insulating film 30 to expose the upper surfaces of the silicon germanium films 22a and 22b.

Referring to FIG. 1D, the silicon germanium films 22a and 22b are removed. The removal process of the silicon germanium films 22a and 22b may include a wet etching process having an etching selectivity to polysilicon. The metal film 40 is formed on the polysilicon films 20a and 20b.

Referring to FIG. 1E, when the silicide process is performed, the metal film 40 and the polysilicon films 20a and 20b react to form metal silicides 50a and 50b, respectively. The metal silicides 50a and 50b have different composition ratios of the metal material and the polysilicon due to the difference in the ratio between the metal material and the polysilicon.

Since the prior art includes a dry etching process of polysilicon, a planarization process of a silicon germanium film, and a wet etching process, the process is complicated and the cost increases.

An object of the present invention is to provide a method of forming a semiconductor device, the process is simple and the cost is reduced.

An embodiment of the present invention provides a method of forming a semiconductor device. The method of forming a semiconductor device includes preparing a semiconductor substrate including a first region and a second region; Forming silicon patterns in the first region and the second region, respectively; Forming a first metal film on the silicon patterns; Performing a first silicide process to form a first metal silicide in the first region and the second region; Forming a second metal film on an upper surface of the first metal silicide in the first region; And performing a second silicide process to form a second metal silicide in the first region.

In the method of forming the semiconductor device, the forming of the second metal film comprises: forming a photoresist pattern exposing the first region on the first metal silicide; And performing an electroless plating process on top of the first metal silicide in the first region.

The method of forming the semiconductor device may include forming an interlayer insulating film covering the silicon pattern after forming the silicon pattern; The method may further include exposing a top surface of the silicon pattern by performing a planarization process on the interlayer insulating layer.

The first metal film and the second metal film may be any one of nickel, cobalt, molybdenum, tungsten, tantalum, or titanium, or a combination thereof.

The method of forming the semiconductor device may further include removing the first metal layer that does not react with the silicon pattern after the first silicide process.

A method of forming a semiconductor device according to an embodiment of the present invention includes preparing a semiconductor substrate including a first region and a second region; Forming silicon patterns in the first region and the second region, respectively; Forming an interlayer insulating film covering sidewalls of the silicon patterns; Forming a first metal film covering the silicon pattern; Performing a first silicide process to convert the silicon patterns to a first metal silicide; Removing the first metal film that has not reacted with the silicon pattern; Forming a photoresist pattern exposing the first region in the second region; Conducting an electroless plating process on top of the first metal silicide in the first region; And performing a second silicide process to convert the first metal silicide in the first region into a second metal silicide.

Hereinafter, a method of forming a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

2A through 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a semiconductor substrate 100 including a first region I and a second region II is prepared. The first region I and the second region II may be a PMOS region and an NMOS region or vice versa. The first region I and the second region II may be defined by forming a well in an active region defined by an isolation region (not shown).

An insulating material and polysilicon are formed on the semiconductor substrate 100. The insulating material and polysilicon are patterned to form gate insulating layers 105a and 105b and a silicon pattern 110. Spacers 112 are formed on sidewalls of the silicon pattern 110.

The gate insulating layers 105a and 105b may be formed by a thermal oxidation process or a chemical vapor deposition process. The gate insulating layers 105a and 105b may be formed of a silicon oxide film, a hafnium oxide film, a zirconium oxide film, or an aluminum oxide film.

The silicon pattern 110 may be formed by patterning polysilicon formed by a low pressure chemical vapor deposition process by pyrolysis of silane (SiH ₄ ) gas at about 600 ° C. FIG. An inert gas may be mixed with the silane (SiH ₄ ) gas for uniformity of the polysilicon. The thickness of the silicon pattern 110 may be determined in consideration of the thickness of the metal film formed in a subsequent process.

The spacer 112 may be formed through an anisotropic etching process after forming an insulating film on the entire surface of the substrate. The spacer 112 may be formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

Source / drain regions 102a, 102b, 103a and 103b are formed in the semiconductor substrate 100. In the forming of the source / drain regions, a low concentration impurity region is formed through an ion implantation process before the spacer 112 is formed, and a high concentration impurity region is formed through an ion implantation process after the spacer 112 is formed. It may include doing.

Referring to FIG. 2B, an interlayer insulating layer 115 covering the silicon pattern 110 is formed. The interlayer insulating layer 115 may be formed by chemical vapor deposition or spin-on-glass method. The upper surface of the silicon pattern 110 is exposed by performing a chemical mechanical polishing process on the interlayer insulating layer 115.

The first metal layer 120 is formed to cover the silicon pattern 110 and the interlayer insulating layer 115. The first metal layer 120 may be formed of nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), tantalum (Ta), or titanium (Ti). The first metal layer 140 may be formed by physical vapor deposition, chemical vapor deposition, or electroplating. The thickness of the first metal layer 120 may be determined in consideration of the composition ratio of silicon of the metal silicide formed in a subsequent process and the first metal.

Referring to FIG. 2C, a first silicide process is performed in which the first metal silicide 130 is formed by reacting the first metal layer 120 with silicon. The first silicide process may include silicidating the entire silicon of the silicon pattern 110. The first silicide process may include a rapid heat treatment process. After the first silicide process is performed, the first metal layer 120 that does not react with the silicon pattern 110 may be removed through a wet etching process. For example, titanium that does not react with silicon is removed by ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ).

The first metal silicide 130 of the first region (I) and the second region (II) has the same ratio of silicon and the first metal, and thus the composition ratio of the metal silicides in each region is also the same. For example, in the case of nickel silicide, the first metal silicides may each be equally NiSi ₂ .

Referring to FIG. 2D, a photoresist pattern 140 exposing the first region I is formed in the second region II. Then, an electroless plating process is performed on the first metal silicide 130 in the first region (I). The electroless plating metal film 150 is formed on the upper surface of the first silicide 130 in the first region I by the electroless plating process. The electroless plating metal film 150 may be the same metal as the first metal film 120.

For example, in the case of plating nickel metal, the electroless plating process is to immerse the wafer in an aqueous solution containing nickel ions, and a reducing agent such as formaldehyde or hydride in the aqueous solution supplies electrons to reduce the nickel ions to the nickel metal. The nickel metal may be deposited on the upper surface of the first silicide 130 of the first region (I).

In general, electroless plating has a dense and uniform thickness of the plating layer. Therefore, the ratio of silicon to metal of the metal silicide may be controlled by the thickness of the electroless plating metal film 150.

Referring to FIG. 2E, the photoresist pattern 140 is removed and a second silicide process is performed. The second silicide process may be performed in the same manner as the first silicide process.

The second metal silicide 200 is formed by the second silicide process. The silicon ratio of the second metal silicide 200 is smaller than the silicon ratio of the first metal silicide 130. Accordingly, each metal gate electrode having a work function suitable for PMOS and NMOS can be formed.

For example, when the first metal and the electroless plated metal are nickel metal, the second metal silicide 200 may be Ni ₃ Si, and the first metal silicide 130 may be NiSi ₂ . The Ni ₃ Si is a metal gate electrode suitable for PMOS, and the NiSi ₂ is a metal gate electrode suitable for NMOS.

According to the exemplary embodiment of the present invention, silicide is formed after the thickness of the silicon pattern is formed in the gate electrodes of PMOS and NMOS. Therefore, the process of forming a semiconductor element is simplified and the cost is reduced.

Claims (6)

Preparing a semiconductor substrate comprising a first region and a second region; Forming silicon patterns in the first region and the second region, respectively; Forming a first metal film on the silicon patterns; Performing a first silicide process to form a first metal silicide in the first region and the second region; Forming a second metal film on an upper surface of the first metal silicide in the first region; And Forming a second metal silicide in the first region by performing a second silicide process. The method according to claim 1, Forming the second metal film is: Forming a photoresist pattern on the first metal silicide to expose the first region; And And forming an electroless plating process on the first metal silicide in the first region. The method according to claim 1, After forming the silicon pattern, Forming an interlayer insulating film covering the silicon pattern; And And forming a planarization process on the interlayer insulating film to expose an upper surface of the silicon pattern. The method according to claim 1, And the first metal film and the second metal film are any one of nickel, cobalt, molybdenum, tungsten, tantalum or titanium, or a combination thereof. The method according to claim 1, After the first silicide process, And removing the first metal film that has not reacted with the silicon pattern. Preparing a semiconductor substrate comprising a first region and a second region; Forming silicon patterns in the first region and the second region, respectively; Forming an interlayer insulating film covering sidewalls of the silicon patterns; Forming a first metal film covering the silicon pattern; Performing a first silicide process to convert the silicon patterns to a first metal silicide; Removing the first metal film that has not reacted with the silicon pattern; Forming a photoresist pattern exposing the first region in the second region; Conducting an electroless plating process on top of the first metal silicide in the first region; And And a second silicide process to convert the first metal silicide in the first region into a second metal silicide.

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