KR20070112937A - High speed-low power lvds driver using bicmos technology - Google Patents

Abstract

A high-speed low-power LVDS driver is provided to minimize an unnecessary area of an LVDS driver terminal by employing a lateral bipolar transistor in Bi-CMOS technology. A reference voltage generating circuit generates a power supply voltage and a constant reference voltage output in an output circuit in which a differential signal is formed by a first output potential and a second output potential according to an input signal applied to an input terminal. Lateral bipolar transistors(50A,50B,51A,51B) adapted to optimize a size of an LVDS(Low Voltage Differential Signaling) driver is mounted on an LVDS driver terminal. A termination resistor has a buffer for adjusting bias of an active resistor.

Description

 High Speed Low Voltage LVDS Driver Using BiCMOS Technology

 1 is a conceptual diagram illustrating an implementation of a low voltage differential signaling (LVDS) interface.

 2 is an LVDS driver using a conventional CMFB circuit according to another embodiment of the present invention.

 Circuit.

 3 shows the electrical characteristics of the output level of the LVDS driver.

 4 is a lateral bipolar transistor mounted according to another embodiment of the present invention.

 Conceptual diagram of the LVDS driver circuit.

 5 is a driver circuit consisting of two inverters, according to another embodiment of the invention.

 6 is a lateral bipolar transistor mounted according to another embodiment of the present invention.

 LVDS driver circuit.

 7 is a single output waveform and common mode voltage of the designed LVDS driver circuit.

 8 is an output signal level of a designed LVDS driver circuit.

 9 shows a lateral bipolar transistor of a new structure to be mounted in a driver stage.

 Giving drawings.

 10 shows a current-voltage (I-V) characteristic curve of a designed lateral bipolar transistor.

 Giving drawings.

 11 shows the current gain curve β of the designed lateral bipolar transistor.

 if.

 12 shows an example of a method for mounting a lateral bipolar transistor in a CMOS process.

 Giving drawings.

Explanation of symbols on the main parts of the drawings

 1,2: LVDS transmitting and receiving device

 3,4: LVDS driver, receiver circuit

 7: termination resistor

 8,9: LVDS transmission line

 10,11: I / O port

 30: CMFB (Common-Mode-Feedback) Circuit

 35: reference voltage circuit output port

 36: output port of constant current circuit

 31A, 31B, 32A, 32B: Switching Element of LVDS Driver Circuit

 33A, 33B: Resistance divider at LVDS driver stage

 40,41: Electrical specification of single output waveform of LVDS driver stage

 43: Electrical Specifications of LVDS Differential Output Waveform Levels

 64: Active resistance that can change the output level of LVDS

 69: output terminal of the buffer

 70: simulation result of the common mode voltage

 93: Designed Lateral Bipolar Transistors

 95: Distance between emitter and collector in lateral bipolar transistor

 96,97: Current Path of Designed Lateral Bipolar Transistor Devices

 100: NMOS and PMOS structure in CMOS process

 101: Redesigned Lateral Bipolar Transistor in CMOS Process

 110: current gain (β) simulation results of the designed lateral bipolar transistor

 The present invention incorporates a latent bipolar transistor of an LVDS driver at an I / O interface into a bipolar technology field of semiconductor processing technology, thereby minimizing unnecessary area of the LVDS driver stage and at the same time designing a new LVDS driver circuit. It is about.

 LVDS is a standard interface defined in ANSI / TIA / EIA-644 that can be used as an interface in areas where high speed data transfer, low power consumption and noise immunity are required. It accepts differential input signals with very small swings, i.e., swings of around 350mV, allowing for high immunity to noise and high data rates. In particular, it is a strong point that the characteristics of noise are enhanced because it operates with high common mode rejection (CMR) by accepting a differential input signal. As data band widths in communications and display are increasing, high-speed data transfer between chips, boards or systems is required, and LVDS is widely used in these fields. The LVDS interface specification does not define a protocol, a connection method, or a connector. The detailed specification varies according to an application field.

 1 is a conceptual diagram for explaining this LVDS interface.

 As shown in the figure, the driver block 1 and the receiver block 2 are connected by differential transmission lines 8 and 9. Each transmission path has the same electrical characteristics, and forms a so-called balanced transmission path, and is configured to transmit one signal through two transmission paths. The driver block 1 has a driver chip 3, a signal is input from the input terminal 10, and the receiver block 2 likewise has a receiver chip 4 constituting a differential amplifier circuit, which also has an output terminal. And outputs a signal from (11).

Both the transmitter and receiver chips are connected to the supply voltage (5), and the terminating resistor (7) R _T of the receiver chip (4) is 100? In addition, the impedance on the differential line is 50Ω.

 In the configuration as described above, the driver chip 3 generates a potential difference between two transmission paths based on the input signal from the input terminal 10 and thereby generates a differential signal. On the other hand, the receiver chip 4 converts the generated differential signal on the transmission path to the CMOS level and outputs it to the output terminal 11.

The principle of the LVDS is to generate a signal voltage at the terminating resistor portion 7 due to the loop formed by the terminating resistor 7 R _T on the receiver chip 4 side with the signal current I _S generated in the driver chip 3. The signal level is detected by switching the direction in which the signal current I _S flows.

According to the configuration as shown in the above figure, the current flowing in the driver chip 3 must be kept constant as a constant current, and the current I _S flowing in the two transmission paths must also be the same and unchanged.

 In the configuration of FIG. 1, the driver block 3 is realized as a circuit as shown in FIG.

In order to generate a constant constant current and supply it to the driver stage, a constant current is supplied to the driver stage 37 as the constant current circuit below I _REF 36 and the transistors 21, 22, 23. The switching elements 31A, 31B, 32A, and 32B for changing the direction of the current of the LVDS driver stage 37 are constituted by MOSFETs, and the transistor 31A when the input signal IN 38 of the driver stage 37 is applied. 31B is turned ON to determine the direction of the current flowing through the termination resistor 34. Similarly, when the input signal INB 39 is applied, the transistors 32A and 32B operate so that the magnitude of the above-described current is the same, but as the direction of the current flowing through the termination resistor 34 is changed, a potential difference on the two transmission lines is formed. The differential signal is output.

In addition, the need for a reference voltage of about 1.25V of V _REF 35 requires a bandgap reference circuit. This is applied to the gate of the transistor 28 in comparison with the voltage through the feedback resistors 33A and 33B of the driver stage and 1.25V, which is a reference voltage, to form a common mode feedback (CMFB) 30, thereby providing a constant value. The common mode voltage V _CM can be obtained. As a result, a stable output waveform can be obtained without a change in the level of the output signal.

As shown in FIG. 3, the single output waveforms 40 and 41 of the LVDS driver are changed in polarity of current through the switching elements of the driver stage. In addition, the common mode voltage (V _CM ) 42 ranges from 1.125 V to 1.375 V in accordance with the LVDS electrical specification, and the differential output waveform 43 through the output waveforms 40 and 41 is a single output waveform V _OD (40). And 41, as shown in FIG.

 The design of the existing LVDS driver stage uses CMOS process because of small power consumption and high speed switching characteristics. In order to design the above-described LVDS driver, the margin of the output signal level swing due to the parasitic resistance component of the device of the driver stage is reduced, which makes it difficult to detect the signal normally. Due to the characteristics of LVDS signal level, swing with sufficient margin within 1.175V ~ 1.375V signal level range, that is, common mode signal range. Therefore, for accurate and reliable driver design, it is generally designed to minimize the parasitic resistance by increasing the area of the switching element of the driver stage.

 In addition, for typical LVDS applications, a constant current of 3.5mA and termination of 100µs are used. However, this is only a general condition for maintaining the standardized signal level (250mV ~ 400mV), and considering the I / O interface environment which is gradually developed and varied, it is suitable for various I / O applications used for different constant currents. Application is limited. In particular, when using 6-12mA constant current, there is also a way to increase the device rated current allowance by designing a large size of the MOSFETs (W / L), but the parasitic capacitance is increased by the increased size of the MOSFETs. The delay of the output occurs due to the delay of the signal, and the area of the device becomes very large during layout, resulting in a large area on the chip when one-chip becomes.

 In order to solve the above problems, the present invention is designed to optimize the performance of the LVDS driver stage of a lateral bipolar transistor having a new structure that can be mounted on the driver stage prior to the LVDS driver design. In addition, by making this one-chip with bipolar transistor, LVDS driver structure and process technology with high speed / low power even in submicron class will be implemented.

 The main technical aspects of LVDS driver circuit using designed BiCMOS process are as follows.

end. Low supply voltage (2.5V) on LVDS driver circuits to minimize power consumption

I. CMFB circuit and RC Miller compensation for constant common mode signal

All. Active resister for changing output level of driver circuit and stopping signal on transmission line

la. Possible new structure of lateral bipolar transistor with LVDS driver stage without separate mask in CMOS process

 In order to achieve the above object, the present invention replaces the MOSFETs of the driver stage with the lateral bipolar transistors 50A, 50B, 51A, and 51B in the LVDS driver circuit 58 of the conventional CMOS process as shown in the conceptual diagram of FIG. Therefore, the parasitic resistance component can be minimized regardless of the device size according to the constant current 52A flowing through the driver 58 stage, thereby introducing a method of designing a miniaturized LVDS driver circuit. In addition, it is designed to implement LVDS circuit by implementing lateral bipolar transistor and deriving optimized parameter without additional mask in CMOS process. An example of the configuration of the LVDS driver circuit and the lateral bipolar transistor described above will also be described.

1. Low voltage LVDS driver circuit

 FIG. 5 is a driver circuit composed of two inverters, which is simple in structure and easy to implement, but requires a current source circuit independent of fluctuations in supply voltage, and a stable operating point because the bias value of an internal node becomes unstable. Hard to find. For this purpose, a feedback circuit is required to keep the common signal or bias voltage of the two output voltages constant.

 In the conceptual diagram of FIG. 4 described above, a more detailed circuit is configured as shown in FIG. 6.

 In the current driver circuit 61 of the present invention, a CMFB 60 having an average value using two resistors as the divider 63 is used, and a power consumption of 8.75 mW (2.5 VV 62 is used). 2.5V x 3.5mA). In the CMFB circuit 60, the voltage average value through the resistor divider 63 of the driver is connected to the input terminal of the single output differential amplifier, so that the LVDS reference voltage 1.25V and the voltage generated in the bandgap reference circuit 65 are applied. Use a car. This maintains a constant bias voltage of the unstable transistor 67 due to the high-speed switching by connecting a single output of the CMFB circuit to the gate of the transistor 67 of the driver stage, while maintaining a constant common mode voltage (Vcm) as shown in FIG. The common mode signal 70 may be implemented. A low voltage swing 80 of ± 300 mV can be obtained when the output voltage is also based on a termination resistance of 100? (Fig. 8).

 The necessary termination resistors for the interruption of the transmission signal and the input sensitivity of the receiver are replaced with an active resister 64 and mounted in the circuit so that the change is possible. This makes it easy to identify and analyze signal distortion and crosstalk problems caused by signal reflections caused by discontinuities in impedance on transmission lines. In addition, the voltage required to adjust the resistance value in the active device contributed to the improvement of the overall circuit performance by mounting a buffer (69) for a stable voltage supply. In addition, low frequency pole using miller compensation (68) through R, C combination can expect good phase margin up to 10pF due to the characteristics of load line.

2. Optimization of Lateral Bipolar Transistors

 In general, when comparing MOSFETs to bipolar devices, MOSFETs have very high input resistance and low switching power due to very high input resistance and nearly 0 mA input bias current, resulting in good switching characteristics. BJT, on the other hand, has higher transconductance (gm) than MOSFET at the same direct current, so it has excellent current driving characteristics. In addition, the device's rated current allowance increases in proportion to the ratio of device size (W / L) in the case of MOSFETs, and is relatively high because the amount of constant current (3.5mA to 12mA) flowing for each application in the LVDS driver design varies. Larger size (W / L) driver designs are required. On the other hand, because the collector current of bipolar generally increases exponentially with the voltage between the base and the emitter, the high current driving characteristics can be used to achieve a more optimized and better performance of the LVDS driver without considering the device size. Design is possible. However, in order to mount the lateral bipolar transistor in the constant current driver, it is important to obtain the same current gain (β) to minimize the fluctuation of the current flowing in the driver stage.

 Therefore, the present invention designed the lateral bipolar transistor 93 optimized to the structure as shown in Figure 9 by adjusting the base length and the doping concentration. By providing collectors on both sides of the emitter, increasing current gain through bidirectional optimized collector-emitter distance 95 and concentration control can be expected to improve current driving.

 The travel path of the currents 96,97 of the designed bipolar device is shown in FIG. 9 by the optimized surface concentration and distance control between the collector and the emitter, as well as the DNwell 91 and The current gain is further improved because the current 97 flowing into the pwell 92 and flowing into the emitter is synthesized, and the current driving characteristics are compared with the characteristics of the existing bipolar through the current between the two bidirectional collectors and the emitter. Does not fall. Also, by forming the Pwell 92 in the DNwell 91, the electrical characteristics of other elements on the circuit on the same Sub are not affected. It is possible to extract the current-voltage (I-V) characteristics and the constant current gain (β) 110 of approximately 20 of the bipolar structure of the new structure designed as shown in FIGS. 10 and 11.

 12 is a conceptual diagram incorporating a lateral bipolar transistor designed in a CMOS process.

 The designed bipolar device 101 forms a Dwell 103 on the Psub 104 to form the Pwell 102 so that it does not have the same potential as the Psub 104 of the other MOSFETs 100. It was. This allows driving of a lateral bipolar transistor independent of the potential of the Psub 104 without additional isolation. Therefore, the designed bipolar device 101 does not affect the electrical characteristics of the MOSFETs device 100 on the same Psub 104, and the device can be manufactured without any additional cost in the process. Thus, the BiCMOS process is also possible by using the same mask as the MOSFET 100 without a separate mask in the CMOS process manufacturing process.

In the present invention, the power consumption is minimized by lowering the existing LVDS supply voltage of 5V and 3.3V to 2.5V, and the transmission data speed and the EMI are minimized through the low voltage data swing. In addition, the output voltage can be adjusted by replacing the driver's termination resistor with an active resistor. It is easier to apply to various applications depending on the input sensitivity of the receiver, and at the same time, the parasitic resistance and the rated current allowance of the device can be applied even at different constant currents of the I / O interface which is diversified and developed by replacing the MOSFETs of the driver stage with lateral bipolar transistors. Regardless, a smaller LVDS chipset can be implemented.

 Given the wide bandwidth requirements of today and the widespread use of high-speed data transfers, this LVDS driver circuit incorporates a lateral bipolar transistor in an LVDS circuit with low supply voltage, making it possible to use high-speed I / O interface circuits and other telecommunication systems. It can be widely used at.

Claims (2)

 In a driver circuit device for LVDS, according to the input signal applied to the input terminal.  D) the output circuit in which the differential signal is formed by the first output potential and the second output potential;  A device that generates a constant reference voltage output with the same power supply voltage in the driver circuit.  A quasi-voltage generating circuit is included;  New Lateral Bipolar Architecture Designed to Optimize LVDS Driver Size  A transistor is mounted on the LVDS driver stage and the termination resistor is an N channel transistor.  Active resistors with buffers for use and stable bias control  LVDS driver featuring.  In the process of designing the lateral bipolar transistor,  Regardless of the potential of the Psub of MOSFETs in structural CMOS processes,  Independent transistor operation is possible;  Since it can be produced without separate isolation process on the same substrate,  Possible to implement bipolar transistor without adding additional mask in CMOS process  One feature;  A method of implementing a lateral bipolar transistor of a BiCMOS process in a CMOS process.

Images