KR20070111298A - Method for unequal error protection and apparatus using the same - Google Patents

Abstract

An unequal error protection method and a wireless communication apparatus using the same are provided to generate different error-protection effects by various combinations of a code rate and a gain to be applied to each bit stream. Error-correction coding is performed on plural bit streams, and symbol mapping is performed by applying one of plural gains to each error-correction-coded bit stream. The step of performing the symbol-mapping includes independently applying the gain to each error-correction-coded bit stream, or applying different gains to bit streams to be handled as channel I and channel Q for the error-correction-coded bit streams. The step of performing the error-correction coding in parallel includes performing error-correction coding by applying different code rates to the bit streams.

Description

Differential error prevention method and wireless communication device using same {Method for unequal error protection and apparatus using the same}

1 is a block diagram illustrating a wireless communication device according to an embodiment of the present invention.

2 is a diagram illustrating bits constituting a subpixel according to an exemplary embodiment of the present invention.

3A to 3C are diagrams illustrating a data separation scheme according to an embodiment of the present invention.

4 is a block diagram illustrating a differential error protection unit according to an embodiment of the present invention.

5 is a block diagram illustrating a sub error correcting coding unit according to an embodiment of the present invention.

6 illustrates a convolutional encoder according to an embodiment of the present invention.

7 illustrates a convolutional encoding result according to an embodiment of the present invention.

8 is a view showing a puncturing result according to an embodiment of the present invention.

9 is a block diagram illustrating a sub symbol mapper according to an embodiment of the present invention.

10 is a view showing a constellation according to an embodiment of the present invention.

11 to 17 are diagrams illustrating a differential error prevention process according to an embodiment of the present invention.

18 is a flowchart illustrating a data processing process according to an embodiment of the present invention.

19 is a block diagram illustrating a wireless communication device according to an embodiment of the present invention.

20 is a block diagram illustrating a differential error protection unit according to an embodiment of the present invention.

21 is a flowchart illustrating a data processing process according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

110: storage unit 120: bit separation unit

130: differential error protection unit 140: transmission unit

410: error correction coding unit 420: stream alignment unit

430: symbol mapper 440: multiplexer

The present invention relates to a wireless communication technology, and more particularly, to a method for providing a differential error protection effect on transmission data and a wireless communication device using the same.

Networks are becoming wireless and researches on effective transmission methods in wireless network environments have been required due to the increasing demand for large-capacity multimedia data transmission. In addition, there is a growing need to wirelessly transfer high-quality video such as digital video disk (DVD) video and high definition television (HDTV) video between various home devices.

Currently, IEEE 802.15.3c is pushing for a technical standard for transmitting a large amount of data in a wireless home network. This standard, called mmWave (Millimeter Wave), uses radio waves with a physical wavelength of millimeters (i.e., radio waves with frequencies of 30 GHz to 300 GHz) for large data transmission. In the past, such a frequency band has been used as an unlicensed band for a limited number of purposes, such as for telecommunication carriers, radio astronomy, or vehicle collision prevention.

IEEE 802.11b and IEEE 802.11g have a carrier frequency of 2.4 GHz and a channel bandwidth of about 20 MHz. In addition, IEEE 802.11a and IEEE 802.11n have a carrier frequency of 5 GHz and a channel bandwidth of about 20 MHz. In contrast, mmWave uses a carrier frequency of 60 GHz and has a channel bandwidth of approximately 0.5 to 2.5 GHz. Therefore, mmWave has a much larger carrier frequency and channel bandwidth than the existing IEEE 802.11 standard. As such, when a high frequency signal (millimeter wave) having a wavelength in millimeters is used, a very high transmission rate in the order of several gigabytes (Gbps) can be represented, and the antenna size can be 1.5 mm or less, so that a single chip including an antenna is used. Can be implemented.

In particular, recent researches have been conducted to transmit uncompressed audio or video data (hereinafter, referred to as uncompressed AV data) between wireless devices using the high bandwidth of the millimeter wave. The compressed AV data is loss-compressed in such a manner as to remove portions less sensitive to human vision and hearing through processes such as motion compensation, DCT transform, quantization, variable length coding, and the like. Therefore, the compressed AV data may suffer from deterioration in image quality due to compression loss, and there is a problem in that compression and decompression of AV data between a transmitting device and a receiving device must follow the same standard. On the contrary, since uncompressed AV data includes digital values (eg, R, G, and B components) representing pixel components as they are, there is an advantage in that clearer image quality can be provided.

The uncompressed AV data includes a combination of bits of high importance and bits of low importance. Higher importance bits have a greater effect on the receiver to restore sound and video, so if an error occurs in a higher priority bit, it is more difficult to recover the original sound or the original image than if an error occurred in a low priority bit. . However, if it is to cause a high error protection effect for all data to be transmitted, so much data processing process must be involved, and the amount of data to be transmitted is inevitably increased. Therefore, there is a need for a technology that can cause an error prevention effect according to the importance of the data.

It is an object of the present invention to transmit data more efficiently and stably.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a differential error prevention method according to an embodiment of the present invention, performing error correction coding on a plurality of bitstreams, and a plurality of gains for each of the error correction coded plurality of bitstreams. Performing symbol mapping by applying any one of the values.

In order to achieve the above object, the differential error prevention method according to an embodiment of the present invention performing error correction coding on a plurality of bitstreams, multiplexing the plurality of bitstreams into a predetermined number of integrated bitstreams And performing symbol mapping by applying any one of a plurality of gain values to the multiplexed integrated bitstreams.

In order to achieve the above object, a wireless communication apparatus according to an embodiment of the present invention is an error correction coding unit for performing error correction coding on a plurality of bitstreams, and a plurality of each of the error correction coded bitstreams It includes a symbol mapper to apply any one of the gain value of the symbol mapping.

In order to achieve the above object, a wireless communication apparatus according to an embodiment of the present invention, an error correction coding unit for performing error correction coding on a plurality of bitstreams, a stream alignment unit for multiplexing some of the plurality of bitstreams, And a symbol mapper configured to apply symbol mapping by applying any one of a plurality of gain values to the multiplexed bitstream.

In order to achieve the above object, the differential error prevention method according to an embodiment of the present invention is performed by performing a symbol demapping on symbols to which any one of a plurality of gain values are applied, and the result of the symbol demapping Performing error correction decoding on the plurality of bitstreams.

In order to achieve the above object, in the differential error prevention method according to an embodiment of the present invention, performing symbol demapping on symbols to which any one of a plurality of gain values is applied; Demultiplexing each of the number of integrated bitstreams, and performing error correction decoding on the plurality of bitstreams output as a result of the demultiplexing.

In order to achieve the above object, a wireless communication apparatus according to an embodiment of the present invention, a symbol demapper for performing symbol demapping on symbols to which any one of a plurality of gain values are applied, and the symbol demapping result of the symbol An error correction decoding unit performs error correction decoding on the plurality of bitstreams provided from the demapper.

In order to achieve the above object, a wireless communication apparatus according to an embodiment of the present invention is a symbol demapper for performing symbol demapping on symbols to which any one of a plurality of gain values is applied, and the symbol demapping result of the symbol demapping. And a stream alignment unit for demultiplexing a predetermined number of integrated bitstreams provided from the mapper, and an error correction decoding unit for performing error correction decoding on a plurality of bitstreams provided from the stream alignment unit as a result of the demultiplexing.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a wireless communication device 100 according to an embodiment of the present invention. The wireless communication device 100 includes a storage unit 110, a bit separator 120, a differential error prevention unit 130, and a transmitter 140.

The storage unit 110 stores data to be transmitted to another device. For example, the data stored in the storage unit 110 may be uncompressed A / V (Audio / Video) data. Hereinafter, the present invention will be described mainly on the uncompressed video data. In the case of video data, a subpixel value for each pixel may be configured. The subpixel values may be stored in various values according to the color space (eg, RGB color space, YCbCr color space, etc.) used, but in the present invention, each pixel may be R (Red), G (Green) according to the RGB color space. The description will be made of three subpixels. Of course, when the video data is a gray image, since only one subpixel component exists, one subpixel may form pixels as it is, and two or four subpixel components may form one pixel.

The bit separator 120 classifies the data provided from the storage 110 according to importance and provides a plurality of bit streams. For example, in the case of an 8-bit video image, as shown in FIG. 2, one subpixel component is represented by 8 bits, and the bit representing the highest order (the highest level bit) is the most significant bit (Most). Significant Bit (MSB), and the bit representing the lowest order (lowest level bit) is the least significant bit (LSB). In other words, each bit of 8-byte 1-byte data has a different importance in recovering a video signal or an audio signal.

Therefore, if the data provided from the storage unit 110 is video data, the bit separator 120 converts each subpixel value (binary value) of the video data from a high order (level) bit to a low order (level) bit. Can be separated. In the case of 8-bit video data, since orders are from 2 ⁷ to 2 ⁰ , they can be separated into a total of 8 bits. Of course, it is not necessary to separate each bit individually, but it is also possible to group and separate each bit by a predetermined number of bits. For example, as shown in FIG. 3A, a subpixel of an 8-bit video image is divided into four groups by grouping two bits for each order, or as a total of two groups by grouping four bits as shown in FIG. 3B. It is also possible to separate the embodiment. As another example, as shown in FIG. 3C, it is possible to separate the upper three bits into one group and the lower five bits into another group in an 8-bit subpixel value. The bit separation process may be performed independently for each subpixel of the video data. Therefore, the separated bits form a bitstream by the same group.

Referring back to FIG. 1, the differential error protection unit 130 performs channel coding (error correction coding) and symbol mapping on a plurality of bitstreams provided from the bit separation unit 120. In this case, the differential error protection unit 130 may cause a differential error protection (UEP) effect on each bitstream according to the importance of the plurality of bitstreams. If an error occurs in a bit of high importance during data transmission, it is desirable to increase an error prevention effect on bits of high importance because an error can be detected more easily when an error occurs in a bit that is not important. A detailed description of the differential error protection unit 130 will be described later with reference to FIGS. 4 to 17.

The transmitter 140 modulates the bitstream processed by the differential error protection unit 130 and transmits the modulated bitstream to the wireless medium using the transmission frequency. To this end, the transmitter 140 may include an orthogonal frequency-division multiplexing (OFDM) modulator (not shown) and an RF processor (not shown). The OFDM modulator classifies input data into N parallel M-ary data symbols, and modulates the classified data symbols through corresponding subcarriers. Thereafter, the OFDM modulator adds the modulated results through the subcarrier to generate one OFDM symbol. Here subcarriers are orthogonal to each other. The RF processor converts the OFDM modulated data into analog data, and processes the analog data into a predetermined RF signal (RF up-conversion) and transmits the same to a wireless medium.

4 is a block diagram illustrating a differential error protection unit 140 according to an embodiment of the present invention. The illustrated differential error protection unit 140 includes an error correction coding unit 410, a stream alignment unit 420, a symbol mapper 430, and a multiplexer 440.

The error correction coding unit 410 performs error correction coding on each bitstream provided from the classifier 120 in parallel. To this end, the error correction coding unit 410 may include a plurality of sub error correction coding units 412-1 to 412-n (hereinafter, each sub error correction coding unit is collectively referred to as an identifier 412 ′).

The sub error correction coding unit 412 may perform error correction coding on the bitstream at different code rates. Of course, if the input bitstreams all have the same importance, the same code rate may be used in error correction coding for each bitstream. However, if the importance of the input bitstreams is different from each other, it is preferable to apply a lower code rate to the higher bitstream. As a result, the higher the importance data, the higher the level of error protection. That is, each sub-error correction coding unit 142 may use the same code rate or may use different code rates. In addition, some of the sub-error correction coding unit 142 may use the same code rate.

According to an embodiment of the present invention, the sub error correction coding unit 142 may include a convolutional encoder 510 and a puncturer 520 as shown in FIG. 5.

The convolutional encoder 510 performs convolutional encoding on the input data. 6 illustrates a convolutional encoder 510 according to an embodiment of the present invention. The illustrated convolutional encoder 510 has a constraint length of 7, a delay memory of 6, a generator polynomial of g0 = 133o, g1 = 171o, g2 = 145o, and a basic code. The rate is 1/3. The convolutional encoder 510 includes a first adder 610, a second adder 620, a third adder 630, and a delay register 640. The initial value of the delay register 640 may be set to 0, and the delay register 640 may be set to an initial value every time a new data group is input. Data output by the convolutional encoder 510 illustrated in FIG. 6 has three times the number of bits compared to the input data, which is illustrated in FIG. 7.

The puncturer 520 adjusts the code rate of data output by the convolutional encoder 510. The code rate can vary depending on the level of error protection required. In the embodiment of FIG. 8, the input data 810 is encoded at the code rate 1/3 by the convolutional encoder 510 (codeword 820), and the codeword 820 is transmitted to the puncturer 520. FIG. 2 shows a result 830 punctured at a code rate of 2/3. In FIG. 8, do to d7 are bits of data to be input, and x0 to x7, y0 to y7, and z0 to z7 are bits of coded data. Bits discarded and bits outputted among the coded data may vary according to a code rate. Bits discarded in FIG. 8 are separated by X marks, and the remaining bits are output.

Meanwhile, according to an embodiment of the present invention, the sub error correction coding unit 412 may use a block coding scheme such as read solomon coding or Bose-Chaudhuri-Hocquenghem coding. . In addition, the sub-error correcting coding unit 412 may use a concatenated coding method combining a block coding method and a convolutional coding method.

Referring back to FIG. 4, the stream aligner 420 aligns the coded bitstreams according to importance. Through this, the bitstreams may be delivered to the appropriate sub-symbol mapper 432 among the sub-symbol mappers 432-1 to 432-m included in the symbol mapper 430 (hereinafter, referred to as sub-symbol mapper ＇432＇). have. That is, the bitstreams that will form the I / Q pair may be determined by the stream aligner 420. According to an embodiment, the stream aligner 420 may multiplex some bitstreams into one bitstream.

Although the differential error protection unit 130 is illustrated as including the stream alignment unit 420 in the embodiment of FIG. 4, the stream alignment unit 420 is not an essential component of the present invention. Therefore, in the following description, although the symbol mapper 430 processes the bitstream transmitted from the stream alignment unit 420, the present invention is not limited thereto, and the symbol mapper 430 may be an error correction coding unit 410. You can also receive and process bitstreams directly.

The symbol mapper 430 performs symbol mapping on the bitstream delivered from the stream aligner 420. The symbol mapper 430 may include at least one sub symbol mapper 432. If the symbol mapper 430 includes a plurality of sub-symbol mappers 432, the symbol mapper 430 may perform symbol mapping on a plurality of input bitstreams in parallel. In this case, two bitstreams of the plurality of bitstreams transmitted from the stream alignment unit 420 may be delivered to one sub-symbol mapper 432. Of course, when there is one sub symbol mapper 432, the sub symbol mapper 432 may be the symbol mapper 430.

9 illustrates a configuration of a sub symbol mapper 432 according to an embodiment of the present invention. The sub-symbol mapper 432 is a gain controller 910 for adding a gain value to an input bitstream, and an I-channel unit 920 for processing the bits of the gain-adjusted bitstream to correspond to the I-axis in the constellation. And a Q channel unit 930 for processing the bits of the gain-adjusted bitstream to correspond to the Q-axis on the constellation.

The gain controller 910 may apply different gain values to the two input bit streams. In this case, the constellation may be expressed in a form in which the I-axis and the Q-axis have different distances from each other as shown in FIG. 10. As shown, when the parameter of the I-axis is 1, the parameter of the Q-axis may be represented by r, where r is greater than 1, and the specific value of r may be predetermined according to the required differential error protection level. . Of course, according to the exemplary embodiment, the gain adjusting unit 910 may apply the same gain value to the two input bit streams, and in this case, r = 1 in FIG. 10.

Meanwhile, the sub symbol mappers 432 may use different gain values. That is, what gain values to apply to the bitstreams input to the symbol mapper 430 may be implemented in various embodiments. Preferably, the higher the bitstream having the higher importance, the higher the gain value, thereby increasing the error protection level for the bitstream having the higher importance.

Referring back to FIG. 4, the multiplexer 440 multiplexes parallel data output from the symbol mapper 430 to output serial data.

Hereinafter, various embodiments of the bitstream processing of the differential error prevention unit 130 described with reference to FIGS. 4 to 10 will be described. In the following embodiments, a process of processing eight bitstreams will be described. However, the present invention is not limited thereto, and a case in which fewer or more than eight bitstreams are processed may be understood through the following embodiments. There will be.

11 illustrates a differential error prevention process according to an embodiment of the present invention. In the embodiment of Fig. 11, the priority is high in the order of bitstream 1 to bitstream 8. First, each bitstream may be error corrected coded at a different code rate. In FIG. 11, r is a code rate applied to each bitstream, and it can be seen that a lower code rate is applied to a bitstream having a higher importance.

The error correction coded bitstreams are each adjusted to an I channel or a Q channel after gain adjustment with different gain values. In FIG. 11, g is a gain value, and it can be seen that a higher gain value is applied to a bitstream having a higher importance level. Through such a processing operation, a bitstream having a higher importance may cause a higher error prevention effect.

In the embodiment of FIG. 11, a case in which both a code rate and a gain value to be applied to each bitstream are different is described. However, although the gain values to be applied to each bitstream are different as shown in FIG. 12, an embodiment in which the same code rate is applied to all the bitstreams is also possible. Of course, embodiments in which different code rates and the same gain value are applied to each bitstream are also possible.

13 illustrates a differential error prevention process according to another embodiment of the present invention. In the embodiment of FIG. 13, different code rates are applied to two bitstreams. That is, the same code rate is applied between bitstreams that will form an I / Q pair, and different code rates are applied between bitstreams that will form an I / Q pair. Even in this case, it is preferable that a higher code rate is applied to a bitstream pair having a high importance.

Meanwhile, in the symbol mapping process of FIG. 13, regardless of the I / Q pair, it can be seen that different gain values are applied for each bitstream to be processed as an I channel and a bitstream to be processed as a Q channel.

14 illustrates a differential error prevention process according to another embodiment of the present invention. In the embodiment of FIG. 14, the error correction coding process is the same as the embodiment of FIG. 13. However, in the present embodiment, the same gain value is applied between bitstreams forming an I / Q pair, and different gain values are applied between bitstreams forming another I / Q pair.

As described above, it is possible to cause different error protection effects for each bitstream through various combinations of the code rate r and the gain value g to be applied to each bitstream. If the error protection effect induced in the bitstream is expressed as P (r, g), a relationship between error protection effects such as Equation 1 can be established, and one error protection effect is applied to each bitstream. can do.

[Equation 1]

P (r1, g1)> P (r1, g2)> P (r2, g2)> ...> P (rN, gN)

Of course, different error protection effects do not have to occur for each of all bitstreams, and in some embodiments, the same error protection effect may occur between some bitstreams.

11 to 14 illustrate a case where gain adjustment is performed in parallel with respect to error correction coded bitstreams. However, the present invention is not limited thereto, and an embodiment of multiplexing some of the error correction coded bitstreams and performing symbol mapping on the multiplexed bitstream may be possible.

For example, as shown in FIG. 15, two integrated bitstreams are created by multiplexing the upper four bitstreams and the lower four bitstreams according to the order of high importance among the error correction coded bitstreams. For example, an embodiment of symbol mapping by applying different gain values to two integrated bitstreams may be possible.

As another embodiment of the present invention, as shown in FIG. 16, two integrated bits are multiplexed by respectively multiplexing the upper three bitstreams and the lower three bitstreams according to the order of importance among the error correction coded bitstreams. You can create streams and treat them as I / Q pairs. In this case, symbol mapping may be performed by applying different gain values to the integrated bitstreams. In this case, the two remaining error-coded bitstreams may be processed as another I / Q pair, and symbol mapping may be performed by applying the same gain to each of them.

Meanwhile, in the above description, each of the input bitstreams has the same number of bits. However, when different code rates are applied for each bitstream during error correction coding, the number of bits between the error correction coded bitstreams is different. For example, if an error correction coding operation is performed at a code rate 1/3, six coded bits are output for two input bits. However, when an error correction coding operation is performed at a code rate of 2/3, three coded bits are output for two input bits.

Alternatively, it is also possible to adjust the number of bits of the input bitstream and the code rate applied to each bitstream so that the bitstreams output as a result of the error correction coding have the same number of bits. For example, in the embodiment illustrated in FIG. 17, a code rate of 1/2 is applied to a bitstream including the upper three bits of the 8-bit subpixel value, and a code is applied to the bitstream including the lower five bits. When the rate 5/6 is applied, the number of bits of the two bitstreams input for error correction coding are different, but the number of bits between the bitstreams output as the result of the error correction coding is the same. As a result, since the number of bits processed by the I channel and the Q channel is the same in symbol mapping, symbol mapping may be smoothly performed.

18 is a flowchart illustrating a data processing process according to an embodiment of the present invention. The illustrated process is performed by the wireless communication device 100 of FIG. 1.

When data is transferred from the storage unit 110 (S1810), the bit classifier 120 classifies the bits constituting the transferred data according to importance. The classified bits may form one bitstream for one or more importance levels.

Thereafter, the differential error protection unit 130 performs differential error protection on the plurality of bitstreams provided from the bit classification unit 120 according to importance. Here, the differential error protection operation includes an error correction coding operation and a symbol mapping operation. A detailed description thereof will be understood through the embodiments of FIGS. 4 to 17.

Thereafter, the transmitter 140 transmits the data output by the differential error prevention unit 130 through the wireless medium (S1840).

19 is a block diagram illustrating a wireless communication device 1900 according to an embodiment of the present invention. The wireless communication device 1900 is a device that receives data transmitted from the wireless communication device 100 of FIG. 1 and processes the received data. The configuration of the wireless communication device 1900 is the configuration of the wireless communication device 100. Corresponds to

The wireless communication device 1900 includes a receiver 1910, a differential error preventer 1920, a bit synthesizer 1930, and a storage 1940.

The receiver 1910 receives data transmitted from another device through a wireless medium. The receiver 1910 may include an RF demodulator (not shown) for RF down-conversion of the received data, an RF processor (not shown), and an OFDM demodulator for RF processed data.

The differential error prevention unit 1920 performs differential error prevention on the data transmitted from the receiver 1910. To this end, as shown in FIG. 20, the differential error prevention unit 1920 classifies input data into a plurality of bitstreams and decodes the plurality of bitstreams from the demultiplexer 2010 and the demultiplexer 2010. A symbol demapper 2020 that performs a symbol demapping operation for the symbol stream, a stream sorter 2030 that sorts or demultiplexes bitstreams transmitted from the symbol demapper 2020, and a plurality of streams delivered from the stream sorter 2030. And an error correction decoding unit 2040 that performs an error correction decoding operation on the bitstream of the.

Among these, the symbol demapper 2020 may include at least one subsymbol demapper 2022-1 to 2022-m (hereinafter, each subsymbol demapper is collectively referred to as an identifier “2022”) and error correction decoding. The unit 2040 may include a plurality of sub error correction decoding units 2032-1 to 2032-n, hereinafter, each sub symbol demapper is collectively referred to as an identifier "2032". The sub symbol demapper 2022 and the sub error correction decoding unit 2042 respectively perform structures and operations corresponding to the sub symbol mapper 432 and the sub error correction coding unit 412 described with reference to FIG. 4. A detailed description of the differential error prevention operation performed by the differential error prevention unit 1920 will be omitted. However, those skilled in the art will be able to perform the operation corresponding to the differential error prevention operation described with reference to FIGS. 11 to 17. The error protection unit 1920 may be implemented.

21 is a flowchart illustrating a data processing process according to an embodiment of the present invention. The illustrated process is performed by the wireless communication device 1900 of FIG. 19.

When the receiver 1910 receives data through the wireless medium (S2110), the differential error prevention unit 1920 performs a differential error prevention operation on the received data (S2120). At this time, since important data is processed to maintain a high error protection level, even if an error occurs in the received data, the finally restored data is hardly affected by the error.

Thereafter, the bit combiner 1930 synthesizes a plurality of bitstreams transmitted from the differential error prevention unit 1920 (S2130), and the storage unit 1940 stores the synthesized bitstream (S2140).

Of course, not only storing the synthesized bitstream is applicable to the present invention, but an embodiment using the synthesized bitstream is also possible. For example, if the received data is uncompressed video data, the wireless communication device 1900 may display an image composed of a bitstream synthesized by the bit combiner 1930.

In the above description, each component constituting the wireless communication device 100 of FIG. 1 and the wireless communication device 1900 of FIG. 19 may be implemented as a module. Herein, the term 'module' refers to a hardware component such as software or a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and a module plays a role. However, modules are not meant to be limited to software or hardware. The module may be configured to be in an addressable storage medium and may be configured to execute one or more processors. Thus, as an example, a module may include components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, subroutines. , Segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided by the components and modules may be combined into a smaller number of components and modules or further separated into additional components and modules.

On the other hand, those skilled in the art will be able to write a program that can perform the processes described with reference to FIGS. 11 to 18 and 21. By recording such a program in a computer-readable recording medium and connecting the storage medium computer, the embodiments described herein and other equivalent embodiments may be implemented. It should be construed as being included in the scope of the invention.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You can understand that there is. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the differential error prevention method and the wireless communication apparatus using the same of the present invention as described above, there is an advantage in that data can be transmitted more efficiently and stably.

Claims (48)

Performing error correction coding on the plurality of bitstreams; And And performing symbol mapping by applying any one of a plurality of gain values to each of the plurality of error correcting coded bitstreams. The method of claim 1, wherein performing symbol mapping comprises: And independently applying a gain value for each of said error correction coded plurality of bitstreams. The method of claim 1, wherein performing the symbol mapping comprises: And applying different gain values to the bitstream to be processed to the I channel and the bitstream to be processed to the Q channel among the plurality of error correction coded bitstreams. The method of claim 3, wherein performing symbol mapping comprises: Applying the same gain value between bitstreams to be processed as I channels among the plurality of error correction coded bitstreams, and applying the same gain value between bitstreams to be processed as Q channels. . The method of claim 1, wherein performing the symbol mapping comprises: And applying the same gain values between bitstreams of the same I / Q pair among the plurality of error correcting coded bitstreams. The method of claim 5, wherein performing the symbol mapping comprises: And applying different gain values between bitstreams forming different I / Q pairs among the plurality of error correction coded bitstreams. The method of claim 1, wherein performing the symbol mapping comprises: And applying a lower gain value to a bitstream of higher importance among the plurality of error correction coded bitstreams. The method of claim 1, wherein performing error correction coding in parallel comprises: Performing error correction coding on the plurality of bitstreams by applying different code rates, respectively. The method of claim 1, wherein performing error correction coding in parallel comprises: And performing error correction coding by applying the same code rate among the bitstreams forming the same I / Q pair among the plurality of bitstreams. 10. The method of claim 9, wherein performing error correction coding in parallel comprises: And performing error correcting coding by applying different code rates among bitstreams that form different I / Q pairs among the plurality of bitstreams. The method of claim 1, wherein performing error correction coding in parallel comprises: And performing error correction coding by applying a higher code rate to a bitstream of higher importance among the plurality of bitstreams. The method of claim 1, And the number of bits between the plurality of bitstreams is different from each other, and the number of bits between bitstreams output as a result of the error correction coding is the same. The method of claim 1, The plurality of bitstreams may include a first bitstream including three bits of higher order and a second bitstream including five bits of lower order among each subpixel value constituting uncompressed 8-bit video data. and, Performing error correction coding in parallel may include performing error correction coding by applying a code rate of 1/2 to the first bitstream and applying a code rate of 5/6 to the second bitstream. Including, differential error prevention method. Performing error correction coding on the plurality of bitstreams; Multiplexing the plurality of bitstreams into a predetermined number of unified bitstreams; And And performing symbol mapping by applying any one of a plurality of gain values to the multiplexed unified bitstreams. The method of claim 14, wherein the multiplexing comprises: Multiplexing the upper half into a first integrated bitstream and the lower half into a second integrated bitstream in the order of high importance among the plurality of bitstreams. The method of claim 14, wherein the multiplexing comprises: Among the plurality of bitstreams, the upper critical number of bitstreams are multiplexed into a first integrated bitstream, the lower critical number of bitstreams are multiplexed into a second integrated bitstream, and the remaining bitstreams Multiplexing half by half into a third integrated bitstream and a fourth integrated bitstream. The method of claim 16, wherein performing the symbol mapping comprises: Perform symbol mapping using the first integrated bitstream and the second integrated bitstream as I / Q pairs, and perform symbol mapping using the third integrated bitstream and the fourth integrated bitstream as I / Q pairs. Differential error prevention method comprising the step of. The method of claim 17, A gain value applied to the first integrated bitstream and the second integrated bitstream are different from each other, and a gain value applied to the third integrated bitstream and the fourth integrated bitstream are the same. . 15. The method of claim 14, wherein performing error correction coding in parallel comprises: Performing error correction coding on the plurality of bitstreams by applying different code rates, respectively. 15. The method of claim 14, wherein performing error correction coding in parallel comprises: And performing error correction coding by applying a higher code rate as a bitstream having a higher importance among the plurality of bitstreams. An error correction coding unit for performing error correction coding on the plurality of bitstreams; And And a symbol mapper for applying symbol one to each of the plurality of error correction coded bitstreams to perform symbol mapping. The method of claim 21, And the symbol mapper independently applies a gain value for each of the plurality of error correction coded bitstreams. The method of claim 21, And the symbol mapper applies different gain values to a bitstream to be processed as an I channel and a bitstream to be processed into a Q channel among the plurality of error correction coded bitstreams. The method of claim 23, wherein And the symbol mapper applies the same gain value between bitstreams to be processed as I channels among the plurality of error correction coded bitstreams, and applies the same gain value between bitstreams to be processed into Q channels. The method of claim 21, And the symbol mapper applies equal gain values between bitstreams forming the same I / Q pair among the plurality of error correction coded bitstreams. The method of claim 25, And the symbol mapper applies different gain values between bitstreams forming different I / Q pairs among the plurality of error correction coded bitstreams. The method of claim 21, And the symbol mapper applies a lower gain value to a bitstream having a higher importance among the plurality of error correction coded bitstreams. The method of claim 21, The error correction coding unit performs error correction coding by applying different code rates to the plurality of bitstreams, respectively. The method of claim 1, And performing error correcting coding by applying the same code rate between bitstreams that form the same I / Q pair among the plurality of bitstreams. The method of claim 29, And the error correction coding unit performs error correction coding by applying different code rates between bitstreams forming different I / Q pairs among the plurality of bitstreams. The method of claim 21, The error correction coding unit performs error correction coding by applying a higher code rate as a bitstream having a higher importance among the plurality of bitstreams. The method of claim 21, And the number of bits between the plurality of bitstreams is different from each other, and the number of bits between bitstreams output as a result of the error correction coding is the same. The method of claim 21, The plurality of bitstreams may include a first bitstream including three bits of higher order and a second bitstream including five bits of lower order among each subpixel value constituting uncompressed 8-bit video data. and, And the error correction coding unit applies code rate 1/2 to the first bitstream and applies code rate 5/6 to the second bitstream to perform error correction coding. An error correction coding unit for performing error correction coding on the plurality of bitstreams; A stream aligner which multiplexes some of the plurality of bitstreams; And And a symbol mapper which applies symbol one or more of a plurality of gain values to the multiplexed bitstream. The method of claim 34, And the stream aligner multiplexes the upper half into the first integrated bitstream in the order of high importance among the plurality of bitstreams, and the lower half into the second integrated bitstream. The method of claim 34, The stream alignment unit multiplexes the upper threshold number of bitstreams into the first integrated bitstream in the order of high importance among the plurality of bitstreams, and multiplexes the lower threshold number of bitstreams into the second integrated bitstream. And multiplexing the bit streams in half into a third integrated bitstream and a fourth integrated bitstream. The method of claim 36, The symbol mapper performs symbol mapping using the first integrated bitstream and the second integrated bitstream as I / Q pairs, and uses the third integrated bitstream and the fourth integrated bitstream as I / Q pairs. A wireless communication device, performing symbol mapping. The method of claim 37, wherein And the gain values applied to the first integrated bitstream and the second integrated bitstream are different from each other, and the gain values applied to the third integrated bitstream and the fourth integrated bitstream are the same. The method of claim 34, The error correction coding unit performs error correction coding by applying different code rates to the plurality of bitstreams, respectively. The method of claim 34, The error correction coding unit performs error correction coding by applying a higher code rate as a bitstream having a higher importance among the plurality of bitstreams. A recording medium having recorded thereon a computer readable program for executing the method according to any one of claims 1 to 13. 21. A recording medium having recorded thereon a computer readable program for executing the method according to any one of claims 14-20. Performing symbol demapping on symbols to which any one of the plurality of gain values is applied; And Performing error correction decoding on a plurality of bitstreams provided as a result of the symbol demapping. Performing symbol demapping on symbols to which any one of the plurality of gain values is applied; Demultiplexing each of the predetermined number of integrated bitstreams provided as a result of the symbol demapping; And And performing error correction decoding on the plurality of bitstreams output as the result of the demultiplexing. A symbol demapper for performing symbol demapping on symbols to which any one of a plurality of gain values is applied; And And an error correction decoding unit configured to perform error correction decoding on a plurality of bitstreams provided from the symbol demapper as a result of the symbol demapping. A symbol demapper for performing symbol demapping on symbols to which any one of a plurality of gain values is applied; A stream aligner which demultiplexes a predetermined number of integrated bitstreams provided from the symbol demapper as a result of the symbol demapping; And And an error correction decoding unit configured to perform error correction decoding on a plurality of bitstreams provided from the stream alignment unit as a result of the demultiplexing. A recording medium having recorded thereon a computer readable program for executing the method according to claim 43. A recording medium having recorded thereon a computer readable program for executing the method according to claim 44.

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