KR20070103255A - Step up circuit and method for generating negative high voltage - Google Patents

Abstract

A step up circuit and a method for generating a negative high voltage are provided to reduce a size of an overall system by integrating a DC/DC(Direct Current) converter in an internal drive IC(Integrated Circuit) without using an external DC/DC converter. A step up circuit includes voltage charging units(110,120,130), bridge transistors(210,220), a transistor switch unit(300) and first and second transistors(500,400). The voltage charging units charge input reference voltages. The bridge transistors store the input reference voltages charged in the voltage charging units. The transistor switch unit selects the input reference voltages according to external selection pin values. The first transistor, which is connected to the transistor switch unit, is switched according to the external selection pin values. The second transistor, which is parallel-connected to the first transistor, controls to output a negative high voltage according to a clock phase.

Description

Step Up Circuit and Method for Generating Negative High Voltage {STEP UP CIRCUIT AND METHOD FOR GENERATING NEGATIVE HIGH VOLTAGE}

1 is a block diagram of an active organic light emitting diode (AM-OLED) display panel according to the prior art.

2 is an overall internal block diagram of a mobile display driver integrated circuit according to the prior art.

3 is a block diagram showing the configuration of a step-up circuit for generating a negative high voltage of the display panel according to an embodiment of the present invention.

4 is a flowchart illustrating a step-up method for generating a negative high voltage of a display panel according to an exemplary embodiment of the present invention.

5 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [00] according to an embodiment of the present invention.

6 is a block diagram illustrating an operation of a step-up circuit having an external selection pin value set to [01] according to an embodiment of the present invention.

7 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [10] according to an embodiment of the present invention.

8 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [11] according to an embodiment of the present invention.

9 is a waveform diagram illustrating a simulation result of a step-up circuit in which an external selection pin value is set to [00] and an input reference voltage is set to 2.8V according to an embodiment of the present invention.

FIG. 10 is a waveform diagram illustrating a simulation result of an output voltage of a step-up circuit having an external selection pin value set to [00], [01], and [10] according to an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

110: first voltage charging unit 120: second voltage charging unit

130: third voltage charging unit 111: first PMOS transistor

112: first NMOS transistor 113: first capacitor

121: second PMOS transistor 122: second NMOS transistor

123: second capacitor 131: third PMOS transistor

132: third NMOS transistor 133: third capacitor

210: first bridge transistor unit 220: second bridge transistor unit

211: fourth PMOS transistor 212: fourth NMOS transistor

221: fifth PMOS transistor 222: fifth NMOS transistor

300: transistor switch unit 301: sixth NMOS transistor

302: seventh NMOS transistor 303: eighth NMOS transistor

500: first transistor 400: second transistor

600: input reference voltage (VREF) 700: ground (GND)

800: output voltage (VOUT) 901: first junction

902: second junction 903: third junction

The present invention relates to a step up circuit and a method thereof.

Generally, a step-up circuit is a circuit which outputs a reference input in predetermined multiples of a reference input through each step.

A flat panel display panel to which a step-up circuit is applied is a device in which cells of a display element are arranged in a matrix form of rows and columns, and each cell emits light due to a current or voltage difference flowing. .

In general, in the flat panel display market, a liquid crystal display (LCD) and a plasma display panel (PDP) have an exclusive advantage. However, in recent years, OLEDs, which have low production costs, high-definition images containing nature, and are thin and portable compared to liquid crystal display devices and plasma display devices, have attracted attention as next-generation flat panel display devices. And the demand is increasing.

1 is a block diagram of an active organic light emitting display (AM-OLED) display panel according to the prior art.

As shown in FIG. 1, an active organic light emitting diode display panel according to the prior art includes a glass substrate 10; An organic light emitting display pixel area 20 positioned on the glass substrate 10; A scan line driver (30) for controlling an image signal in a row of the organic light emitting display pixel region (20); The data line driver 40 is configured to control an image signal in a column of the pixel area 20 of the organic light emitting diode display.

The scan line driver 30 includes a gate driver block to drive the scan line driver 30.

The data line driver 40 includes a source driver block to drive the data line driver 40.

2 is an overall internal block diagram of a mobile display driver integrated circuit according to the prior art.

As shown in FIG. 2, an internal structure of a mobile display driver integrated circuit for driving the organic light emitting diode display pixel area 20 according to the related art includes a memory and a controller block 101 for storing and controlling a control signal. )and; The gate driver block (102) for driving the scan line driver (30); The source driver block (103) for driving the data line driver (40); A gamma block 104 for controlling Gamma; An oscillator block 105 for supplying a system frequency; A voltage regulator block 106 for supplying a stable internal voltage; A step-up circuit one block (107) for supplying power to the gate driver block (102); And a step up circuit 2 block 108 for supplying power to the source driver block 103.

The memory and controller block 101 corresponds to a digital block.

The gate driver block 102, the source driver block 103, the gamma block 104, the oscillator block 105, the voltage regulator block 106, the step-up circuit 1 block 107, The step-up circuit 2 block 108 corresponds to an analog block.

In general, the active organic light emitting diode display panel is widely used for movement.

In addition, the panel of the mobile display element requires a high voltage battery so that the panel of the mobile display element can be driven.

Therefore, the panel of the said mobile display element uses a DC-DC converter.

The use of the DC-DC converter may cause a problem that the production cost increases as the DC-DC converter is added to the panel of the mobile display device.

In addition, the use of the DC-DC converter may cause a problem that the size of the panel increases as the DC-DC converter is added to the panel of the mobile display device.

Accordingly, an object of the present invention is to provide a step-up circuit and a method for improving the capability of a flat panel display panel, which are created to solve the above-described conventional problems.

Another object of the present invention is to provide a step-up circuit and a method for generating a negative high voltage in a driver internal integrated circuit.

According to an aspect of the present invention, a step-up circuit includes: a voltage charger configured to charge an input reference voltage; A bridge transistor unit which accumulates the input reference voltage charged by the voltage charger unit; A transistor switch unit configured to select the input reference voltages accumulated in the bridge transistor unit according to an external selection pin value; A first transistor coupled to the transistor switch and configured to control shutdown according to the external selection pin value; A second transistor is connected in parallel with the first transistor and controls a negative high voltage output according to a clock phase.

The voltage charging unit may include: a first PMOS transistor having the input reference voltage connected to a drain of the PMOS transistor; A first capacitor connected to a source of the first PMOS transistor and an anode of the capacitor; A cathode of the first capacitor and a source of the NMOS transistor are connected to each other, and a drain of the NMOS transistor and a ground (GND: Gound) are connected to each other.

The first PMOS transistor, the first capacitor, and the first NMOS transistor are configured in series with each other between the input reference voltage and the ground.

The bridge transistor unit may include a second PMOS transistor and a second NMOS transistor connected in parallel.

In addition, the transistor switch unit includes a plurality of NMOS transistors connected in parallel with each other.

In addition, the first transistor may be connected to the ground of the first transistor and the drain of the transistor switch unit and the drain of the first NMOS transistor in parallel with each other and connected to the drain of the first transistor, and the source of the first transistor and the second transistor. The sources of the transistors are connected in parallel to form the output voltage.

In addition, the second transistor, the source of the first NMOS transistor and the cathode of the first capacitor is connected in parallel to the drain of the second transistor, the source of the second transistor and the source of the first transistor Are connected in parallel to form the output voltage.

In addition, the first transistor and the second transistor may be composed of a switch element such as a PMOS, an NMOS, or a diode.

The voltage charging section and the bridge transistor section of the step-up circuit according to the present invention for achieving the above objects, the plurality of voltage charging section and the same function as the voltage charging section and the bridge transistor section according to the output voltage desired by the user; A plurality of the bridge transistor units may be connected in series with each other alternately.

The voltage charging parts and the bridge transistor parts connected in series with a plurality of step-up circuits according to the present invention for achieving the above objects may be configured to output an output voltage desired by the user according to an output voltage desired by the user. It is configured in connection with the transistor switch unit.

A step up method according to the present invention for achieving the above objects comprises: a voltage charging step of charging a voltage according to a clock phase; And a voltage accumulation step of accumulating the voltage charged in the voltage charging step and outputting the accumulated voltage.

In addition, the voltage charging step may include: charging the voltage by the input reference voltage when the clock phase is 1; Checking the clock phase to control the output voltage.

The charging of the voltage may include charging the capacitor by the input reference voltage to the capacitor constituting the voltage charger.

The charging of the voltage may include a plurality of voltage charging units having the same function connected to each other.

Therefore, when the clock phase is 1, the plurality of voltage chargers are each charged with the input reference voltage.

The controlling of the output voltage may include turning off the ninth NMOS transistor when the clock phase is 1, and maintaining the output voltage in a floating state insulated from the ground. to be.

The voltage accumulating step may further include: accumulating voltages charged in the respective voltage charging parts in the voltage charging step when the clock phase is 2; Selecting one of the accumulated voltages according to the accumulated voltages; And outputting the selected accumulated voltage to the output voltage according to the external selection pin value.

The accumulating of the charged voltages may include accumulating the input reference voltages charged in each of the voltage chargers by connecting voltages charged by the input reference voltage in series with each of the voltage chargers. .

The selecting one of the accumulated voltages may include selecting one of the accumulated voltages according to the external selection pin value.

The outputting of the output voltage may include checking the external selection pin value when the clock phase is two.

In addition, the first transistor is turned off when the external selection pin value test result is a shutdown value, and the output voltage is connected to the ground.

The first transistor is turned on when the external selection pin value test result is not a shutdown value, and the accumulated voltage is output to the output voltage.

Hereinafter, a preferred embodiment of a step-up circuit and a method for generating a negative high voltage of the display panel in the display driver internal integrated circuit will be described in detail with reference to FIGS. 3 to 10.

3 is a block diagram showing the configuration of a step-up circuit for generating a negative high voltage of the display panel according to an embodiment of the present invention.

As shown in FIG. 3, the step-up circuit includes: a first voltage charger 110, a second voltage charger 120, and a third voltage charger 130 for charging the input reference voltage 600; A first bridge transistor unit 210 and a second bridge transistor unit 220 accumulating the input reference voltage 600 charged by the first, second, and third voltage chargers 110, 120, and 130; A transistor switch unit 300 for selecting the input reference voltages 600 accumulated in the first and second bridge transistor units 210 and 220 according to an external selection pin value; A first transistor (500) connected in series with the transistor switch unit (300) and controlling shutdown according to the external selection pin value; The second transistor 400 is connected in parallel with the first transistor 500 and controls a negative high voltage output according to a clock phase.

The first voltage charging unit 110 includes a first PMOS transistor 111, a first NMOS transistor 112, and a first capacitor 113.

In the first PMOS transistor 111, the input reference voltage 600 is connected to the drain of the first PMOS transistor 111, and a first junction 901 is connected to a source of the first PMOS transistor 111. It is connected and configured.

The first junction 901 may include a source of the first PMOS transistor 111, a source of the first bridge transistor unit 210, a source of a sixth NMOS transistor 301, and a source of the first capacitor 113. The anodes are connected to each other.

In the first NMOS transistor 112, the ground 700 is connected to the drain of the first NMOS transistor 112, and the cathode of the first capacitor 113 and the drain of the second transistor 400 are parallel to each other. Is connected to the source of the first NMOS transistor 112 is configured.

The first capacitor 113 has the first junction 901 connected to the anode of the first capacitor 113, the source of the first NMOS transistor 112 and the second transistor 400. The drain of the first capacitor 113 is connected in parallel is configured to be connected.

The second voltage charger 120 includes a second PMOS transistor 121, a second NMOS transistor 122, and a second capacitor 123.

In the second PMOS transistor 121, the input reference voltage 600 is connected to the drain of the second PMOS transistor 121, and the second junction 902 is connected to a source of the second PMOS transistor 121. It is connected and configured.

The second junction 902 may include a source of the second PMOS transistor 121, a source of the second bridge transistor 220, a source of a seventh NMOS transistor 302, and a second capacitor 123. The anodes are connected to each other.

The second NMOS transistor 122 has the ground 700 connected to the drain of the second NMOS transistor 122, and has a cathode of the second capacitor 123 and a portion of the first bridge transistor unit 210. A drain is connected in parallel and is connected to the source of the second NMOS transistor 122.

The second capacitor 123 has the second junction 902 connected to the anode of the second capacitor 123, the source of the second NMOS transistor 122, and the first bridge transistor unit 210. A drain of the second capacitor 123 is connected in parallel and is configured to be connected to the cathode of the second capacitor 123.

The third voltage charger 130 includes a third PMOS transistor 131, a third NMOS transistor 132, and a third capacitor 133.

The third PMOS transistor 131 has the input reference voltage 600 connected to the drain of the third PMOS transistor 131, and has an anode of the third capacitor 133 and an eighth NMOS transistor 303 of the third PMOS transistor 131. A source is connected in parallel and is connected to the source of the third PMOS transistor 131.

In the third NMOS transistor 132, the ground 700 is connected to the drain of the third NMOS transistor 132, and the cathode of the third capacitor 133 and the second bridge transistor unit 220 are connected to each other. A drain is connected in parallel and is connected to the source of the third NMOS transistor 132.

The third capacitor 133 is connected to a source of the third PMOS transistor 131 and a source of the eighth NMOS transistor 303 in parallel to be connected to an anode of the third capacitor 133. A source of the 3 NMOS transistor 132 and a drain of the second bridge transistor unit 220 are connected in parallel to each other and connected to a cathode of the third capacitor 133.

The first bridge transistor unit 210 includes a fourth PMOS transistor 211 and a fourth NMOS transistor 212.

The fourth PMOS transistor 211 is connected in parallel with the fourth NMOS transistor 212.

In addition, the fourth PMOS transistor 211 is connected to the source of the second NMOS transistor 122 and the cathode of the second capacitor 123 in parallel to be connected to the drain of the fourth PMOS transistor 211. The first junction 901 is connected to the source of the fourth PMOS transistor 211.

In addition, the fourth NMOS transistor 212 is connected to the source of the second NMOS transistor 122 and the cathode of the second capacitor 123 in parallel to be connected to the drain of the fourth NMOS transistor 212. The first junction 901 is connected to the source of the fourth NMOS transistor 212.

The second bridge transistor unit 220 includes a fifth PMOS transistor 221 and a fifth NMOS transistor 222.

The fifth PMOS transistor 221 is connected in parallel with the fifth NMOS transistor 222.

In addition, the fifth PMOS transistor 221 is connected to the source of the third NMOS transistor 132 and the cathode of the third capacitor 133 in parallel to be connected to the drain of the fifth PMOS transistor 221. The second junction 902 is connected to the source of the fifth PMOS transistor 221.

In addition, the fifth NMOS transistor 222 is connected to the source of the third NMOS transistor 132 and the cathode of the third capacitor 133 in parallel to be connected to the drain of the fifth NMOS transistor 222. The second junction 902 is connected to the source of the fifth NMOS transistor 222.

The transistor switch unit 300 includes the sixth NMOS transistor 301, the seventh NMOS transistor 302, and the eighth NMOS transistor 303.

In addition, the sixth NMOS transistor 301 may include a third coupling part 903, a drain of the seventh NMOS transistor 302, and a drain of the eighth NMOS transistor 303 in parallel with each other. It is connected to the drain of the NMOS transistor 301, the first junction 901 is connected to the source of the sixth NMOS transistor 301 is configured.

The third junction 903 may include a drain of the ground 700, the first transistor 500, a drain of the first NMOS transistor 112, a drain of the second NMOS transistor 122, and A drain of the third NMOS transistor 132 and a drain of the transistor switch 300 are connected to each other.

In addition, in the seventh NMOS transistor 302, the drain of the third junction 903, the sixth NMOS transistor 301, and the drain of the eighth NMOS transistor 303 are connected in parallel with each other to form the seventh NMOS transistor 302. The second junction 902 is connected to the source of the seventh NMOS transistor 302 and connected to the drain of the NMOS transistor 302.

In addition, the eighth NMOS transistor 303 has the drain of the third junction 903, the sixth NMOS transistor 301, and the drain of the seventh NMOS transistor 302 connected in parallel to each other. It is connected to the drain of the NMOS transistor 303, the source of the third PMOS transistor 131 and the anode of the third capacitor 133 is connected in parallel to the source of the eighth NMOS transistor 303 is configured do.

The first transistor 500 includes the drain of the transistor switch unit 300, the drain of the first NMOS transistor 112, the drain of the second NMOS transistor 113, and the third NMOS transistor 114. A drain and the ground 700 are connected in parallel to each other and connected to a drain of the first transistor 500, and a source of the first transistor 500 and a source of the second transistor 400 are connected in parallel. Configure output voltage 800.

In the second transistor 400, a source of the first NMOS transistor 112 and a cathode of the first capacitor 113 are connected in parallel to each other, and the second transistor 400 is connected to a drain of the second transistor 400. The source of the transistor 400 and the source of the first transistor 500 are connected in parallel to form the output voltage 800.

In addition, the first transistor 500 and the second transistor 400 may be composed of a switch element such as a PMOS, an NMOS, a diode.

The input reference voltage 600 is connected to the drain of the first PMOS transistor 111, the drain of the second PMOS transistor 112, and the drain of the third PMOS transistor 113.

The ground 700 may include a drain of the first NMOS transistor 112, a drain of the second NMOS transistor 122, a drain of the third NMOS transistor 132, and a drain of the sixth NMOS transistor 301. And a drain of the seventh NMOS transistor 302, a drain of the eighth NMOS transistor 303, and a drain of the first transistor 500.

The output voltage 800 is configured by the source of the tenth NMOS transistor 500 and the source of the second transistor 400 connected in parallel.

The first voltage charger 110, the second voltage charger 120, the third voltage charger 130, the first bridge transistor 210, and the second bridge transistor 220 are provided by a user. A plurality of voltage chargers having the same function as the first voltage charger 110, the second voltage charger 120, and the third voltage charger 130 according to the desired output voltage 800, and the first voltage charger A plurality of bridge transistor units having the same function as the bridge transistor unit 210 and the second bridge transistor unit 220 may be connected in series with each other.

In addition, the plurality of voltage charging units and the bridge transistor units connected in series may be configured to output the output voltage 800 desired by the user according to the output voltage 800 desired by the user. It is configured in connection with.

The step-up circuit reduces the size and overall cost of the entire system by designing a circuit for generating a negative high voltage to an internal driver integrated circuit without using an external DC-DC converter.

The step up method includes a voltage charging step of charging a voltage in accordance with a clock phase; And a voltage accumulation step of accumulating the voltage charged in the voltage charging step and outputting the accumulated voltage.

The voltage charging step includes charging the voltage by the input reference voltage (600) when the clock phase is 1; Checking the clock phase to control the output voltage 800.

In the charging of the voltage, when the external selection pin value is set, the first PMOS transistor 111, the first NMOS transistor 112, the second PMOS transistor 121, and the second NMOS transistor. An operation 122, the third PMOS transistor 131, and the third NMOS transistor 132 are turned on.

Subsequently, in the charging of the voltage, the first capacitor 113 of the first voltage charger 110 and the second capacitor 123 and the third voltage charger of the second voltage charger 120 ( The third capacitor 133 of 130 is charged with a voltage by the input reference voltage 600, respectively.

In the controlling of the output voltage 800 having the clock phase of 1, the second transistor 400 is turned off and the output voltage 800 is maintained in a floating state.

The voltage accumulating step may include accumulating voltages charged in the voltage charging units 110, 120, and 130 in the voltage charging step when the clock phase is 2; Selecting one of the accumulated voltages according to the accumulated voltages; And outputting the selected accumulated voltage to the output voltage 800 according to the external selection pin value.

In the accumulating the charged voltages, when the external selection pin value is set, the fourth PMOS transistor 211, the fourth NMOS transistor 212, and the second of the first bridge transistor unit 210 are set. The fifth PMOS transistor 221 and the fifth NMOS transistor 222 of the bridge transistor unit 220, the sixth NMOS transistor 301 and the seventh NMOS transistor 302 of the transistor switch unit 300. And the eighth NMOS transistor 303 are turned on or off according to the external selection pin value, respectively.

Thereafter, in the accumulating of the charged voltages, the first voltage charging unit 110, the second voltage charging unit 120, and the third voltage charging unit 130 are respectively charged by the input reference voltage 600. Voltage is accumulated one, two, and three times the input reference voltage 600.

In the selecting of one of the accumulated voltages, one of voltages accumulated by one, two, and three times the input reference voltage 600 is selected according to the external selection pin value.

In the outputting of the output voltage 800, the external selection pin value is checked.

In addition, in the outputting the output voltage 800 having the clock phase 2, the second transistor 400 is turned on.

In addition, the first transistor 500 is turned off when the external selection pin value test result is a shutdown value, and the output voltage 800 is connected to the ground 700.

In addition, the first transistor 500 is turned on when the external selection pin value test result is not a shutdown value, and the accumulated voltage is output to the output voltage 800.

The step-up method may selectively generate a negative high voltage at one, two, and three times the input reference voltage 600, thereby outputting the output voltage 800 desired by the user according to the external selection pin value. have.

In addition, the step-up circuit and the method is configured to stack a negative high voltage by one multiple of the input reference voltage 600, thereby reducing the size of the entire system, the input reference desired by the user according to the user's request The output voltage 800 may be output in multiples of the voltage 600.

Hereinafter, a step-up method for generating a negative high voltage of a display panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

4 is a flowchart illustrating a step-up method for generating a negative high voltage of a display panel according to an exemplary embodiment of the present invention.

As shown in Fig. 4, the step-up method includes: a voltage charging step of charging a voltage in accordance with a clock phase; And a voltage accumulation step of accumulating the voltage charged in the voltage charging step and outputting the accumulated voltage. In the voltage charging step, when the clock phase is 1, the voltage is charged by the input reference voltage 600. The voltage accumulating step may include accumulating voltages charged by the input reference voltage 600 when the clock phase is 2, selecting the accumulated voltages according to the external selection pin value, and then selecting the selected accumulated voltage. Is output to the output voltage 800 according to the external selection pin value.

The plurality of voltage chargers 110, 120, and 130 may charge the capacitors 113, 123, and 133 included in the plurality of voltage chargers 110, 120, and 130 as much as the input reference voltage 600, respectively (S11).

Thereafter, the output voltage 800 checks the clock phase to determine whether to output the charged voltage (S12). In this case, when the clock phase test result is 1, the second transistor 400 is turned off, and the output voltage 800 is in a floating state (S17). In addition, the second transistor 400 is turned on when the clock phase test result is not one.

The bridge transistor parts 210 and 220 may be connected in series to voltages charged by the input reference voltage 600 in the capacitors 113, 123, and 133 of the voltage charging parts 110, 120, and 130, respectively, to be multiples of the input reference voltage 600. The voltages are accumulated (S13).

The transistor switch unit 300 selects one of the accumulated voltages according to the external selection pin value (S14).

Thereafter, the first transistor 500 checks whether the external selection pin value is in the shutdown mode (S15). In this case, when the external selection pin value is in the shutdown mode, the first transistor 500 is turned off, and the output voltage 800 is connected to the ground (S18). In addition, the first transistor 500 is turned on when the external selection pin value is not in the shutdown mode, and the selected accumulated voltage is output to the output voltage 800 (S16).

Hereinafter, the operation of the step-up circuit having the external selection pin value set to [00] according to an embodiment of the present invention will be described in detail with reference to FIG.

5 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [00] according to an embodiment of the present invention.

As shown in Fig. 5, the step-up circuit having the external selection pin value set to [00] is the voltage charging step when the clock phase is 1, and the voltage accumulation step when the clock phase is 2. Becomes

In the voltage charging step, the first capacitor 113 of the first voltage charging unit 110 and the second capacitor 123 and the third voltage charging unit 130 of the second voltage charging unit 120. Each of the third capacitors 133 charges the voltage by the input reference voltage 600.

In the voltage charging step, since the clock phase is 1, the second transistor is turned off, and the output voltage 800 maintains a floating state.

In the voltage accumulating step, since the external selection pin value is [00], the fourth PMOS transistor 211, the fourth NMOS transistor 212, and the second bridge transistor unit (of the first bridge transistor unit 210). The fifth PMOS transistor 221 and the fifth NMOS transistor 222 of 220 are turned on, respectively.

Accordingly, the first capacitor 113, the second capacitor 123, and the third capacitor 133 are connected in series.

In addition, in the voltage accumulation step, voltages charged by the input reference voltage 600 are accumulated in the first capacitor 113, the second capacitor 123, and the third capacitor 133, respectively.

In the voltage accumulation step, the sixth NMOS transistor 301 and the seventh NMOS transistor 302 are turned off, and the eighth NMOS transistor 303 is turned on because the external selection pin value is 00.

Subsequently, in the voltage accumulation step, the first transistor 500 is turned on because the external selection pin value is the first capacitor 113, the second capacitor 123, and the third capacitor 133. ) -3 times of the input reference voltage 600 accumulated in () is output to the output voltage 800.

Hereinafter, the operation of the step-up circuit in which the external selection pin value is set to [01] according to an embodiment of the present invention will be described in detail with reference to FIG.

6 is a block diagram illustrating an operation of a step-up circuit having an external selection pin value set to [01] according to an embodiment of the present invention.

As shown in Fig. 6, the step-up circuit having the external selection pin value set to [01] becomes the voltage charging step when the clock phase is 1, and the voltage accumulation step when the clock phase is 2. Becomes

In the voltage charging step, the first capacitor 113 of the first voltage charging unit 110 and the second capacitor 123 and the third voltage charging unit 130 of the second voltage charging unit 120. Each of the third capacitors 133 charges the voltage by the input reference voltage 600.

In the voltage charging step, since the clock phase is 1, the second transistor is turned off, and the output voltage 800 maintains a floating state.

In the voltage accumulation step, since the external selection pin value is [01], the fourth PMOS transistor 211 and the fourth NMOS transistor 212 of the first bridge transistor unit 210 are turned on, respectively, and the second The fifth PMOS transistor 221 and the fifth NMOS transistor 222 of the bridge transistor unit 220 are turned off, respectively.

Therefore, the first capacitor 113 and the second capacitor 123 are connected in series.

In the voltage accumulation step, voltages charged by the input reference voltage 600 are accumulated in the first capacitor 113 and the second capacitor 123, respectively.

In the voltage accumulation step, since the external selection pin value is [01], the sixth NMOS transistor 301 and the eighth NMOS transistor 303 are turned off, and the seventh NMOS transistor 302 is turned on.

Subsequently, in the voltage accumulation step, since the external selection pin value is [01], the first transistor 500 is turned on, and the input reference voltage accumulated in the first capacitor 113 and the second capacitor 123 is increased. -2 times 600 is output to the output voltage 800.

Hereinafter, the operation of the step-up circuit in which the external selection pin value is set to [10] according to an embodiment of the present invention will be described in detail with reference to FIG.

7 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [10] according to an embodiment of the present invention.

As shown in Fig. 7, the step-up circuit having the external select pin value set to [10] becomes the voltage charging step when the clock phase is 1, and the voltage accumulation step when the clock phase is 2. Becomes

In the voltage charging step, the first capacitor 113 of the first voltage charging unit 110 and the second capacitor 123 and the third voltage charging unit 130 of the second voltage charging unit 120. Each of the third capacitors 133 charges the voltage by the input reference voltage 600.

In the voltage charging step, since the clock phase is 1, the second transistor is turned off, and the output voltage 800 maintains a floating state.

In the voltage accumulating step, since the external selection pin value is [10], the fourth PMOS transistor 211, the fourth NMOS transistor 212, and the second bridge transistor unit () of the first bridge transistor unit 210 ( The fifth PMOS transistor 221 and the fifth NMOS transistor 222 of 220 are turned off, respectively.

Thus, only the first capacitor 113 is connected.

In the voltage accumulating step, a voltage charged by the input reference voltage 600 is accumulated in the first capacitor 113.

In the voltage accumulation step, since the external selection pin value is [10], the seventh NMOS transistor 302 and the eighth NMOS transistor 303 are turned off, and the sixth NMOS transistor 301 is turned on.

Subsequently, in the voltage accumulating step, since the external selection pin value is [10], the first transistor 500 is turned on, and −1 times the input reference voltage 600 accumulated in the first capacitor 113 is greater than or equal to the value. The output voltage 800 is output.

Hereinafter, the operation of the step-up circuit in which the external selection pin value is set to [11] according to an embodiment of the present invention will be described in detail with reference to FIG.

8 is a configuration diagram illustrating an operation of a step-up circuit in which an external selection pin value is set to [11] according to an embodiment of the present invention.

As shown in Fig. 8, the step-up circuit having the external selection pin value set to [11] becomes the voltage charging step when the clock phase is 1, and the voltage accumulation step when the clock phase is 2. Becomes

In the voltage charging step, the first capacitor 113 of the first voltage charging unit 110 and the second capacitor 123 and the third voltage charging unit 130 of the second voltage charging unit 120. Each of the third capacitors 133 charges the voltage by the input reference voltage 600.

In the voltage charging step, since the clock phase is 1, the second transistor is turned off, and the output voltage 800 maintains a floating state.

In the voltage accumulation step, since the external selection pin value is [11], the first transistor 500 is in a shutdown state.

Thus, all current paths are broken such that the output voltage 600 maintains the ground 700 value.

Hereinafter, an operation of the step-up circuit in which the external selection pin value is set to [00] and the input reference voltage is set to 2.8 V according to an embodiment of the present invention will be described in detail with reference to FIG.

9 is a waveform diagram illustrating a simulation result of a step-up circuit in which an external selection pin value is set to [00] and an input reference voltage is set to 2.8V according to an embodiment of the present invention.

As shown in Fig. 9, the simulation result of the step-up circuit is composed of the voltage charging step in which the clock phase is 1 and the voltage accumulation step in which the clock phase is 2.

In the voltage charging step in which the clock phase is 1, the first capacitor 113, the second capacitor 123, and the third capacitor 133 are charged with 2.8 V, which is the input reference voltage 600, respectively. .

In the voltage accumulation step in which the clock phase is 2, the first capacitor 113, the second capacitor 123, and the third capacitor 133 are connected in series, and the first capacitor 113 and the A voltage charged by 2.8 V, the input reference voltage 600, is accumulated in the second capacitor 123 and the third capacitor 133, respectively.

Thereafter, the output voltage 800 in the voltage accumulation step of which the clock phase is 2 is accumulated at -8.4 V, which is -3 times the input reference voltage 600, and is output as the output voltage 800.

Hereinafter, a simulation result of an output voltage of a step-up circuit having an external selection pin value set to [00], [01], and [10] according to an embodiment of the present invention will be described in detail with reference to FIG.

FIG. 10 is a waveform diagram illustrating a simulation result of an output voltage of a step-up circuit having an external selection pin value set to [00], [01], and [10] according to an embodiment of the present invention.

10, the simulation result of the output voltage 800 according to the external selection pin value, when the input reference voltage 600 is 2.8V, when the external selection pin value is [00] When the output voltage 800 outputs -8.4V, which is -3 times the input reference voltage 600, and the external selection pin value is [01], the output voltage 800 is the input reference voltage 600. -5.6V, which is -2 times of the value, and the external selection pin value of [10], indicates that the output voltage 800 outputs -2.8V, which is -1 times the input reference voltage 600.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the spirit and scope of the present invention should not be construed as being limited to the above embodiments, and various modifications may be made within the scope of the present invention as defined by the claims. It will be apparent to those skilled in the art that it is possible.

As described in detail above, the step-up circuit and method thereof according to the present invention are designed by integrating the internal driver integrated circuit without using an external DC-DC converter, thereby reducing the size of the entire system and reducing the cost. There is a saving effect.

In addition, the step-up circuit and the method according to the present invention, by configuring the plurality of voltage charging section and the bridge transistor section alternately connected in series, to add or remove the circuit of the voltage charging section and the bridge transistor section according to the user's request Therefore, there is an effect that can utilize the entire system efficiently.

In addition, the step-up circuit and the method according to the present invention, by selectively generating a negative high voltage of 1, 2, 3 times the input reference voltage, the user can use the desired output voltage according to the external selection pin value There is.

In addition, the step-up circuit and the method according to the present invention is configured to stack the negative high voltage by a multiple of the input reference voltage, there is an effect that the user can output the negative high voltage in a desired multiple according to the user's request .

Claims (29)

A voltage charger configured to charge an input reference voltage; A bridge transistor unit which accumulates the input reference voltage charged by the voltage charger unit; A transistor switch unit configured to select the input reference voltages accumulated in the bridge transistor unit according to an external selection pin value; A first transistor coupled to the transistor switch and configured to control shutdown according to the external selection pin value; And a second transistor connected in parallel with the first transistor and controlling a negative high voltage output according to a clock phase. The method of claim 1, wherein the voltage charging unit, A step up circuit comprising a combination of a first PMOS transistor, a first capacitor, and a first NMOS transistor. The method of claim 2, wherein the first PMOS transistor, And the input reference voltage is connected to the drain of the first PMOS transistor, and an anode of the first capacitor is connected to a source of the first PMOS transistor. The method of claim 2, wherein the first capacitor, And a source of the first PMOS transistor is connected to an anode of the first capacitor and a cathode of the first capacitor is connected to a source of the first NMOS transistor. The method of claim 2, wherein the first NMOS transistor, And a cathode of the first capacitor is connected to the source of the first NMOS transistor and a drain of the first NMOS transistor is connected to ground. The method of claim 1, wherein the bridge transistor unit, And a second PMOS transistor and a second NMOS transistor in parallel with each other. The method of claim 6, wherein the bridge transistor unit, The drain of the bridge transistor portion is configured such that the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected in parallel to each other, the source of the bridge transistor portion of the source of the second PMOS transistor and the second NMOS transistor Step up circuit, characterized in that the source is configured in parallel with each other. The method of claim 6, wherein the bridge transistor unit, Step-up circuit is located between the plurality of voltage charging, characterized in that connected in series with the plurality of voltage charging. The method of claim 8, wherein the bridge transistor unit, A source of the NMOS transistor in the voltage charging part connected to the upper end of the bridge transistor part and a cathode of the capacitor are connected in parallel to the drain of the bridge transistor part, and to the source of the PMOS transistor in the other voltage charging part connected to the lower end of the bridge transistor part; And a positive pole of the capacitor is connected in parallel to the source of the bridge transistor unit. The method of claim 1, wherein the transistor switch unit, Step-up circuit, characterized in that a plurality of NMOS transistors are connected in parallel with each other. The method of claim 10, wherein the plurality of NMOS transistors, And said ground is connected to the drain of said plurality of NMOS transistors, and junctions to which said voltage charging section and said bridge transistor section are connected are respectively connected to the sources of said plurality of NMOS transistors. The method of claim 1, wherein the first transistor, The ground and the drain of the transistor switch unit and the drain of the first NMOS transistor in the voltage charging unit are connected in parallel to each other and connected to the drain of the first transistor, and the source of the first transistor and the source of the second transistor are Step-up circuit characterized in that the output voltage is connected in parallel. The method of claim 1, wherein the second transistor, The source of the first NMOS transistor and the cathode of the first capacitor are connected in parallel to the drain of the second transistor, and the source of the second transistor and the source of the first transistor are connected in parallel to the output voltage. Step-up circuit, characterized in that the configuration. The method of claim 12 or 13, wherein the first transistor and the second transistor, Step-up circuit featuring switch elements such as PMOS, NMOS, diodes. The method of claim 1, wherein the voltage charging unit and the bridge transistor unit, And a plurality of the voltage charging units and the plurality of bridge transistor units alternately connected in series with each other according to a desired output voltage. The method of claim 15, wherein the plurality of the voltage charging unit and the bridge transistor unit connected in series alternately with each other, And a transistor switch unit configured to select the output voltage according to the external selection pin value. A voltage charging step of charging an input reference voltage according to a clock phase; And accumulating the input reference voltage charged in the voltage charging step and outputting the accumulated voltage. The method of claim 17, wherein the voltage charging step and the voltage accumulation step, Step-up method characterized in that configured according to the clock phase. The method of claim 17, wherein the voltage charging step, And when the clock phase is 1, charging the voltage by the input reference voltage. The method of claim 17, wherein the voltage charging step, Charging a voltage by the input reference voltage; Checking the clock phase to control the output voltage. The method of claim 20, wherein charging the voltage comprises: Charging a capacitor by the input reference voltage to one capacitor. The method of claim 21, wherein charging the voltage comprises: Charging a plurality of capacitors according to the input reference voltage. The method of claim 20, wherein controlling the output voltage comprises: When the clock phase is one, causing the output voltage to remain in a floating state. The method of claim 17, wherein the voltage accumulation step, When the clock phase is 2, accumulating voltages charged by the input reference voltage, selecting the accumulated voltages according to an external signal, and outputting the selected accumulated voltage to the output voltage according to the external signal. The step up method characterized by the above-mentioned. The method of claim 17, wherein the voltage accumulation step, Accumulating a voltage by the input reference voltage in the voltage charging step; Selecting one of the accumulated voltages according to an external signal from the accumulated voltage; Outputting the selected accumulated voltage to the output voltage according to the external signal. The method of claim 25, wherein accumulating the charged voltages comprises: Connecting the charged voltages in series in the plurality of capacitors and accumulating the voltage in the respective capacitors. The method of claim 25, wherein selecting one of the accumulated voltages comprises: Selecting one of the accumulated voltages according to the external signal. The method of claim 25, wherein outputting the selected accumulated voltage comprises: Connecting the output voltage to ground in accordance with information provided by the external signal. 27. The method of claim 26, wherein outputting the selected accumulated voltage comprises: And outputting the selected accumulated voltage as the output voltage according to the information provided by the external signal.

Images