KR20070099743A - Wafer level package and fabricating method therefore - Google Patents

Abstract

A wafer level package and a fabricating method thereof are provided to reduce the volume of the package without an additional connecting layer or a via-hole by using an interconnection pad. A fabricating method of a wafer level package includes the steps of: laminating a first insulating layer(23) on an outermost circuit(19) of a semiconductor chip(21), and planarizing the surface of the first insulating layer(23); removing a part of the first insulating layer(23), and exposing a chip pad(12) outside; laminating a metal layer which is directly contacted to the chip pad(12), on the chip pad(12) and the first insulating layer(23), removing a part of the metal layer, and preparing a bumping metal(13) having a bumping pad electrically connected to the chip pad(12); and sequentially laminating a second insulating layer(27) and a coating layer(29) on the bumping metal(13), removing a part of the bumping metal(23), and exposing the bumping pad outside.

Description

Wafer level package and its manufacturing method {WAFER LEVEL PACKAGE AND FABRICATING METHOD THEREFORE}

1 is a plan view illustrating a state in which bumping pads, signal lines and power lines connected thereto are arranged.

2 is a cross-sectional view illustrating a state in which a first insulating layer is stacked on a semiconductor chip in a method of manufacturing a wafer level package according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a planarized state of one surface of the first insulating layer illustrated in FIG. 2.

4 is a cross-sectional view illustrating a state in which a chip pad is exposed by removing a portion of the first insulating layer illustrated in FIG. 3.

FIG. 5 is a cross-sectional view illustrating a state in which bumping metals are stacked in FIG. 4.

FIG. 6 is a cross-sectional view illustrating a state in which the bumping pads are exposed by sequentially removing oxides and nitrides of FIG. 5 and partially removing the oxides and nitrides.

7 is a cross-sectional view of an interconnection pad according to one embodiment of the invention.

<Description of Drawing>

11: bumping pad 12: chip pad

13: Bumping Metal 15: Powerline

17: signal line 19: outermost circuit

21: wafer 23: first oxide layer

25: pad 27: second oxide layer

29: coating layer

The present invention relates to a wafer level package and a method of manufacturing the same.

The trend in the electronics industry today is to manufacture products with light weight, small size, multifunction, high performance and high reliability at low cost. One of the key technologies that enables these product design goals is package assembly technology. The semiconductor chip in which the integrated circuit is formed through the wafer assembly process has a package shape by the package assembly technology, which can protect the semiconductor chip from the external environment, facilitate mounting, and ensure operation reliability.

According to the package assembly technology, various types of package types have been introduced until recently, but among them, chip scale packages have attracted attention. A chip scale package is a package at a chip level, and generally refers to a package having a size within 1.2 times the chip size. Such a chip scale package has many advantages over a typical plastic package, and in particular, the size of the package is small. Because of these advantages, chip-scale packages are mainly used in products requiring miniaturization and mobility, such as digital camcorders, mobile phones, notebook computers, memory cards, and so on.These include DSP (Digital Signal Processor), Application Specific Integrated Circuit (ASIC) Semiconductor devices such as microcontrollers are mounted in chip-scale packages. In addition, the use of chip scale packages in which memory devices such as DRAM (Dynamic Random Access Memory), flash memory, etc. are mounted is gradually increasing.

However, while chip-scale packages have absolute advantages in terms of size, they still have several drawbacks over traditional plastic packages. One of them is that it is difficult to secure reliability, and the other is that there is a lot of manufacturing equipment and raw materials required for the manufacture of chip scale packages, and the manufacturing cost is low and the price competitiveness is low.

Wafer level chip scale packages (hereinafter referred to as "wafer level packages") have emerged as a way to solve this problem. The wafer level package is manufactured by rewiring, forming external connection terminals in the form of balls, and separating individual semiconductor chips in the state of semiconductor wafers manufactured by the wafer assembly process without the assembly being performed in the state of being separated into individual semiconductor chips. Form. Wafer-level packages have the advantages of thermal and electrical characteristics of the package, miniaturization of the package, and significant cost reduction and ripple effects from wafer-level test applications. Furthermore, existing wafer assembly facilities and processes can be used for the manufacturing equipment or manufacturing process used to manufacture the package, minimizing the additional raw materials required to manufacture the package.

Conventional wafer level packages cover and insulate using polyamide-based materials on semiconductor chips on which semiconductor fabrication (FAB) has been completed. At this time, the wafer level package process used was a metal wet etching apparatus and a pattern apparatus. However, such metal wet etching equipment and pattern equipment is impossible to form a more precise pattern because the limit of the pattern is a micrometer (μm) level. In addition, the limitation of the mass production process currently in use is that many pin-outs are saved by using two benzocyclobutene (BCB) layers and up to two redistribution layers for interconnection. It has limit to be difficult.

The present invention provides a wafer level package and a method of manufacturing the same, which can form a more precise pattern using a semiconductor manufacturing process (FAB) device.

The present invention provides a wafer level package and a method for manufacturing the same, which can reduce the volume since it is not necessary to form the rearrangement layer by forming the interconnection pad.

In a wafer level package according to an aspect of the present invention, after stacking a first insulating layer on an outermost layer circuit of a semiconductor chip, planarizing a surface of the first insulating layer, and removing a portion of the first insulating layer to form a chip pad. Exposing to the outside, a metal layer directly contacting the chip pad is deposited on the chip pad and the first insulating layer, and then partially removed to form a bumping metal having a bumping pad electrically connected to the chip pad; Sequentially depositing a second insulating layer and a coating layer on the metal, and then removing a portion of the second insulating layer and the coating layer to expose the bumping pads to the outside, all of which are performed by a semiconductor manufacturing process (FAB) device.

Embodiments of a method for manufacturing a wafer level semiconductor package according to the present invention may have one or more of the following features. For example, the metal layer may be an under bump metallurgy, and after forming the coating layer, the bottom bump metal may be further stacked on the bumping pad. The coating layer may be made of nitride and the first insulating layer and the second insulating layer may be oxide layers. The planarization of the first oxide layer may be performed by chemical mechanical polishing or by an etch back process of spin on glass.

Both ends of the outermost layer circuit may form interconnection pads electrically connected to each other. Solder balls may be formed on the bumping pads, and the size of the bumping pads exposed to the outside may be 50 to 85% of the solder ball diameter.

According to another aspect of the present invention, another wafer-level package includes a semiconductor chip having an outermost layer circuit and a chip pad formed thereon, a first insulating layer having a hole stacked on the semiconductor chip and exposing the chip pad to the outside; A second insulation layer comprising: a bumping metal stacked on an insulating layer, one end of which is electrically connected to the chip pad, and the other end of which is formed of a bumping pad; and a second insulating layer and a coating layer sequentially stacked on the bumping metal. The layer and the covering layer have holes for exposing the bumping pads to the outside.

The bumping metal may be made of under bump metallurgy,

The wafer level package may include a bottom bump metal stacked on the bumping pads. In addition, the coating layer may be made of nitride, and the first coating layer and the second coating layer may be oxide layers. The wafer level package includes an interconnection pad made of a pair of bumping metals electrically connected to both ends of the outermost layer circuit, one of the bumping metals may be connected to the chip pad and the other to the bumping pads.

Hereinafter, an embodiment of a wafer level package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or corresponding components are given the same reference numerals. Duplicate description thereof will be omitted. In addition, the dotted lines shown on the substrate 21 in FIGS. 2 to 6 mean that other layers including a circuit layer may be formed between the substrate 21 and the outermost layer circuit 19.

Referring to FIG. 1, an edge pad type semiconductor chip 21 in which a plurality of chip pads (not shown) are formed around an edge is illustrated. A plurality of bumping pads 11 are formed on the semiconductor chip 21, and the bumping pads 11 are electrically connected to the chip pads 12 by the power line 15 or the signal line 17, respectively. . Although not shown in FIG. 1, a solder ball (not shown) is attached to the bumping pad 11. All bumping pads 11 are connected to the chip pads 12 by a power line 15 or a signal line 17. When there is no space to connect the chip pad 12 and the bumping pad 11, as shown in FIG. 7, an interconnection pad 31 is formed to connect the two. The interconnection pad 31 will be described below.

The power line 15 is a line for supplying power to the semiconductor chip 21, and the signal line 17 is a line for inputting a control signal or the like to the semiconductor chip 21. In general, the power line 15 is wider than the signal line 17.

A cross-sectional view along the line II of FIG. 1 is shown in FIG. 6. Referring to FIG. 6, a bumping metal 13 is formed on the chip pad 12 of the semiconductor chip 21. One end of the bumping metal 13 is in direct contact with the chip pad 12 and the other end is formed of the bumping pad 11 by an etching process or the like. After the coating layer 29 and the second insulating layer 27 are stacked on the bumping metal 13, a part of the coating layer 29 and the second insulating layer 27 are removed to expose the bumping pad 11 to the outside.

Hereinafter, a method of manufacturing a wafer level package according to an embodiment of the present invention will be described with reference to FIGS. 2 to 6. The wafer level package manufacturing method described below is currently made by a semiconductor manufacturing process (FAB) equipment capable of precise processing up to several tens of nanometers (nm).

Referring to FIG. 2, a circuit layer composed of a plurality of layers is formed on the semiconductor chip 21, and the outermost layer circuit 19 includes a layer formed on the outermost layer on one or both surfaces of the semiconductor chip 21. it means. The first insulating layer 23 is stacked on the outermost layer circuit 19, and the first insulating layer 23 may be an oxide layer. The first insulating layer 23 may have a thickness of at least 5 μm by a planarization process to be performed later, and may be reduced to 10 μm in consideration of resistance and current driving capability of the first insulating layer 23. It can be formed in thickness. The larger the thickness of the first insulating layer 23 is, the lower the resistance is, while the current driving capability is improved.

Since the wafer level package manufacturing process according to the present embodiment is performed by a semiconductor manufacturing process (FAB) device, an oxide layer may be formed as the first insulating layer 23.

Referring to FIG. 3, one surface of the first insulating layer 23 is processed into a substantially flat surface by a planarization process. The planarization process is performed by chemical mechanical polishing or spin on glass, depending on the thickness of the bumping metal (13 of FIG. 5) to be formed later and the pitch size of the power line 15 or the signal line 17. The etch back process can be selected from. By the planarization process, the thickness of the first insulating layer 23 may be formed to be at least 5 μm or more or 10 μm or more.

Referring to FIG. 4, a portion of the first insulating layer 23 is removed to expose a portion of the chip pad 12 to the outside. A method of removing the first insulating layer 23 is to remove a portion of the first insulating layer 23 by a wet etching process after exposure using a photo mask. The chip pad 12 is directly connected to the bumping metal 13 by a later process.

Referring to FIG. 5, a bumping metal 13 is formed on the chip pad 12 and the first insulating layer 23. The bumping metal 13 is formed by processing a metal layer laminated on the chip pad 12 and the first insulating layer 23 by an etching process or the like, and directly contacting the chip pad 12, the bumping pad 11, and power. It consists of a line 15 or a signal line 17.

The bumping pad 11 has an octagonal shape as shown in FIG. 1, and a solder ball is attached to one surface thereof by a later process. The size of the bumping pad 11 exposed to the outside may be about 50 to 85% of the diameter of the solder ball. As such, the bumping pad 11 may provide a space in which the solder balls may be attached while electrically connected to the chip pads 12, and the solder pads may be attached by drawing the chip pads 12 toward the center of the semiconductor chip 21. It has a role to secure space for

The bumping metal 13 may be made of an under ball metallurgy. The lower ball metal is excellent in bonding strength with a solder ball made of tin (Sb) or the like. The bumping metal 13 may be made of general aluminum (Al) or copper (Cu). As such, when the bumping metal 13 is formed of a metal other than the lower ball metal, the lower ball metal may be additionally stacked on the bumping metal 13 by a later process.

As shown in FIG. 6, after the second insulating layer 27 and the coating layer 29 are stacked on the bumping metal 13, a portion of the bumping pad 11 is removed to expose the bumping pad 11 to the outside. As a method of removing the second insulating layer 27 and the coating layer 29, there is an etching using a photo mask. The second insulating layer 27 may include an oxide and the coating layer 29 may be nitride. Nitride is not only resistant to moisture, but also has a low dielectric constant.

When the bumping metal 13 is not formed by the under bump metallurgy, the lower bump metal is laminated on the coating layer 29 and the bumping pad 11 and the bonding force of the solder ball is etched by using a pattern. It can increase.

As described above, the wafer level package and the fabrication method thereof according to the present embodiment use semiconductor manufacturing process (FAB) equipment, and thus, the power line 15 and the signal line 17 can be precisely processed up to several tens of nanometers (nm). have. In addition, because of the use of semiconductor fabrication process (FAB) equipment, not only chemical mechanical polishing can be used but also oxide layers and nitrides can be laminated.

Referring to FIG. 7, one embodiment of the interconnection pad 31 of the wafer level package consists of a pair of bumping metals 13 electrically connected to both ends of the outermost layer circuit 19 and spaced apart from each other. When the chip pad and the bumping pad cannot be connected by the other bumping metal 13, the bumping metal 13 connected with the chip pad and the bumping metal 13 connected with the bumping pad 11 may be formed by the outermost layer circuit 19. Electrically connected. As such, the wafer-level package according to the present embodiment can reduce the volume of the package by using the interconnection pad, since it is not necessary to form a separate connection layer or via hole.

Although the embodiments of the present invention have been described above, various changes and modifications of the present invention should also be construed as falling within the scope of the present invention as long as the technical idea of the present invention is realized.

The present invention can provide a wafer level package and a method of manufacturing the same, which can form a more precise pattern using semiconductor manufacturing process (FAB) equipment.

The present invention can provide a wafer level package and a method of manufacturing the same that can reduce the volume.

Claims (16)

(a) stacking a first insulating layer on the outermost circuit of the semiconductor chip and then planarizing the surface of the first insulating layer; (b) exposing a chip pad to the outside by removing a portion of the first insulating layer; (c) forming a bumping metal having a bumping pad electrically connected to the chip pad by stacking a metal layer directly contacting the chip pad on the chip pad and the first insulating layer, and then removing a part of the metal layer; (d) sequentially stacking a second insulating layer and a coating layer on the bumping metal, and then removing a portion thereof to expose the bumping pad to the outside;  The above steps are all performed by a semiconductor manufacturing process (FAB) equipment. The method of claim 1, And the metal layer is under bump metallurgy. The method of claim 1, And (b) a lower bump metal is further stacked on the bumping pad. The method of claim 1, And the coating layer is made of nitride. The method of claim 1, The planarization of the first oxide layer in step (a) is performed by chemical mechanical polishing (Chemical Mechanical Polishing). The method of claim 1, The planarization of the first oxide layer in the step (a) is a wafer level package manufacturing method performed by an etch back process of spin on glass (Spin On Glass). The method of claim 1, And the first insulating layer and the second insulating layer are oxide layers. The method of claim 1, Forming interconnection pads electrically connected to the bumping metals at both ends of the outermost layer circuit. The method of claim 1, After the step (d) is completed, the bumping pad is a wafer level package manufacturing method for forming a solder ball. The method of claim 9, The bumping pad exposed to the outside is a size of 50 ~ 85% of the solder ball diameter wafer level package manufacturing method. A semiconductor chip on which an outermost layer circuit and a chip pad are formed; A first insulating layer stacked on the semiconductor chip and having a hole for exposing the chip pad to the outside; A bumping metal stacked on the chip pad and the first insulating layer, one end of which is electrically connected to the chip pad and the other end of which a bumping pad is formed; And a second insulating layer and a coating layer sequentially stacked on the bumping metal, wherein the second insulating layer and the coating layer have holes for exposing the bumping pad to the outside. The method of claim 11, And the bumping metal is formed of an under bump metallurgy. The method of claim 11, The wafer level package includes a lower bump metal stacked on the bumping pad. The method of claim 11, The coating layer is a wafer level package made of nitride (nitrade). The method of claim 11, And the first coating layer and the second coating layer are oxide layers. The method of claim 11, The wafer level package includes an interconnection pad made of a pair of bumping metals electrically connected to both ends of the outermost layer circuit, One of the bumping metals connected to the chip pad and the other connected to the bumping pad.

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