KR20070098352A - Apparatus for bus arbitration - Google Patents

Abstract

A device for arbitrating a memory is provided to control a memory access request for a memory device which can be accessed by a plurality of memory access units at the same time. A bandwidth setting storage device sets and stores the reference bandwidth of a memory access request of more than one unit of the memory access units(11-15). A bandwidth counter measures a bandwidth for the memory access request of more than one memory access unit. A bandwidth storing device stores a counter value. A first controller controls a system memory bus request of the memory access unit by comparing values stored in the bandwidth counter and the bandwidth storage device with values stored in the bandwidth setting storing device. If a value stored in the bandwidth counter and the bandwidth storing device is over a value stored in the bandwidth setting storage device, the first controller masks the access of the memory access unit by controlling the system memory buys request during a variable interval.

Description

Apparatus for bus arbitration

1 is a diagram illustrating an interface through which a plurality of memory access units (MAUs) are connected to a single memory device to input and output data.

2 is a view illustrating an example of storage devices included in a memory arbitration apparatus for measuring and recording a global bandwidth according to the present invention;

3 is a timing diagram illustrating operation according to clock cycles of the global bandwidth counter (GBC) and the global bandwidth register (GBR).

4 is a timing diagram illustrating a process of transitioning a value stored in a global bandwidth counter (GBC) and a global bandwidth register (GBR) in a memory arbitration apparatus in accordance with the present invention.

5 illustrates a memory access latency counter (MALC) and a maximum memory access latency register (MMALR) included in a memory arbitration apparatus in accordance with the present invention.

6 is an operation timing diagram of a memory access latency counter (MALC) in a memory arbitration apparatus in accordance with the present invention.

7A to 7B are diagrams illustrating an example of a storage device for storing a stabilization period value and a priority value of a memory arbitration device in accordance with the present invention.

8 is a timing diagram illustrating an example of control for a system memory bus request by any memory access unit (MAU) in accordance with the present invention.

9 is a timing diagram illustrating another example of control for a system memory bus request by any memory access unit (MAU) in accordance with the present invention.

* Explanation of symbols for the main parts of the figure

11, 12, 13, 14, 15: memory access unit

20: memory arbitration device

50: memory device

The present invention relates to memory arbitration, and more particularly, to a memory arbitration device capable of controlling in real time the use of a bus for accessing a memory device.

A data processing system, such as a digital video processor, includes a plurality of function blocks and a plurality of memory access units for accessing the memory device by the function block. unit: MAU).

In a data processing system such as a digital television system on a chip (SOC), the embedded central processing unit and multiple functional blocks use a single memory device as a system memory device.

FIG. 1 is a diagram illustrating an interface in which a plurality of memory access units (MAUs) are connected to a single memory device to input and output data in a data processing system such as an SOC of a digital television. Referring to FIG. 1, a process in which an arbiter, which is a memory arbitration apparatus, controls an interface when a plurality of memory access units (MAUs) access a memory device will be described.

In FIG. 1, a number of memory access units (MAUs) are included in the SOC of a digital television, and the access units MAU A 11, MAU B 12, MAU C 13, MAU D 14, and Assume that there is a MAU E (15) and the like. The access units may be anything that connects to a memory device, such as a transport, a video decoder, a format converter, an audio decoder, a host interface, and the like.

 The memory access units (MAUs) 11 to 15 may transmit information MCMD requesting access to the memory device 50 to the memory arbitration device 20 to access the single memory device 50. . The information that the memory access units (MAUs) 11 to 15 transmit to the memory arbitration device 20 includes row / column addresses, read / writes of banks in the memory device. Information, data masking, bank number to access, addressing mode, and the like. The memory arbitration apparatus 20 then permits the use of a shared write data bus / shared read data bus for reading and writing to the memory access units (MAUs) 11 to 15.

If a particular memory access unit (MAU) (for example, 11) uses the system memory bus excessively for a certain period of time, the variable workload of the memory access unit (MAU) 11 may reach the memory device 50 at a certain point in time. Are concentrated. In such a case, the memory access latency time is increased in other functional blocks in which a certain amount of data transfer from the memory device 50 is to be guaranteed. If the functional blocks fail to access the memory device 50 within the maximum latency time, an internal buffer may be underflowed or overflowed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory arbitration apparatus for controlling a memory access request for a memory device that can be accessed simultaneously by a plurality of memory access units (memory access unit) do.

In order to achieve the above object, an example of a memory arbitration apparatus for controlling a memory access request for a memory device that can be accessed simultaneously by a plurality of memory access units (MAU) according to the present invention, the memory access unit A bandwidth setting storage device for setting and storing a reference bandwidth of a memory access request for one or more units of the MAU; A bandwidth counter that measures a bandwidth for a memory access request for one or more units of the memory access unit (MAU); A bandwidth storage device for storing the counter value; And controlling a system memory bus request of the corresponding memory access unit by comparing the measured value of the bandwidth counter and the value stored in the bandwidth storage device with a preset value of the bandwidth setting storage device. Characterized in that it comprises a control device.

In this case, when the measured value of the bandwidth counter and the value stored in the bandwidth storage device are equal to or greater than a value preset in the bandwidth setting storage device, the first controller may vary the system memory bus request of the memory access unit (MAU). It is preferable to mask the access of the corresponding memory access unit (MAU) by controlling during the in period.

And the variable interval may include (1) none or (2) a period in which the bandwidth counter value of a particular memory access unit (MAU) is equal to or greater than the value of the bandwidth setting storage of the memory access unit (MAU), (3 A period in which a periodically generated system signal is active and stores a previous bandwidth counter value in a bandwidth storage device until the system signal following the system signal is activated, (4) the (2) and ( 3) It is preferable that it is any one of the sections which added the section.

Preferably, the second control device further comprises a second control device that can turn on / off the first control device.

Another example of a memory arbitration apparatus for controlling a memory access request for a memory device to which a plurality of memory access units (MAUs) according to the present invention can access simultaneously is a minimum for one or more units of the memory access units (MAUs). A minimum memory access interval storage device for setting and storing a memory access interval; A memory access interval counter for measuring a memory cycle for one or more units of the memory access unit (MAU); And a first controller configured to control a system memory bus request of a corresponding memory access unit (MAU) by comparing a value measured by the memory access interval counter with a value preset in a minimum memory access interval storage device. It is done.

In this case, if the value measured by the memory access interval counter is smaller than the value preset in the minimum memory access interval storage device as a result of the comparison, masking the memory access of the corresponding memory access unit (MAU) Is preferred.

Preferably, the control signal masks an access to at least a predetermined value in the minimum memory access interval storage device.

In addition, the first control device is preferably configured to further comprise a second control device that can be turned on (on / off).

Another example of a memory arbitration device for controlling a memory access request for a memory device to which a plurality of memory access units (MAUs) according to the present invention can access at the same time is for one or more units of the memory access units (MAUs). A bandwidth setting storage device for setting and storing a reference bandwidth of the memory access request; A bandwidth counter that measures a bandwidth for a memory access request for one or more units of the memory access unit (MAU); A bandwidth storage device for storing the counter value; A first control device for controlling a system memory bus request of a corresponding memory access unit (MAU) by comparing the measured value of the bandwidth counter and the value stored in the bandwidth storage device with a preset value of the bandwidth setting storage device; A minimum memory access interval storage device for setting and storing a minimum memory access interval for at least one of the memory access units (MAU); A memory access interval counter for measuring a memory cycle for one or more units of the memory access unit (MAU); And a second controller configured to control a system memory bus request of a corresponding memory access unit (MAU) by comparing a value measured by the memory access interval counter with a value preset in a minimum memory access interval storage device. It is done.

In this case, the first control device and the second control device preferably further comprises a third control device that can be turned on (on / off).

And the third control device is configured to (1) turn on only the first control device, (2) turn on only the second control device, or (3) both the first control device and the second control device. It is preferable to control so as to select either the case of turning on or (4) turning off both the first control device and the second control device.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings. In addition, the terminology used in the present invention was selected as a general term widely used as possible now. However, in certain cases, the applicant arbitrarily selected a term, and in this case, the meaning is described in detail in the corresponding part. Therefore, the terms used in the present invention should be understood as meanings of the terms rather than simply names of the terms.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

The memory arbitration apparatus according to the present invention controls the global bandwidth that the memory access unit (MAU) accesses and uses the memory device, or the latency time (MAU) waits to access the memory device. By controlling latency time, you can distribute and restrict usage rights for the bus in two ways.

First, a process of controlling a global bandwidth used by a plurality of memory access units (MAUs) to access and use a memory device according to the present invention will be described below.

The memory arbitration unit measures the global bandwidth used by each memory access unit (MAU) to monitor and limit in real time the global bandwidth that the memory access units (MAUs) access and use the memory device. And a counter for recording and a storage device.

In the present specification, a device for measuring a global bandwidth used by each memory access unit (MAU) is a global bandwidth counter (GBC), a storage device for recording the measured global bandwidth (global bandwidth) Is named a global bandwidth register (GBR) by using a register as an example. The memory arbitration device also includes a global bandwidth setting register (GBSR), which is a storage device for setting the amount of global bandwidth that each memory access unit (MAU) may basically require. can do.

2 is an example of a counter and a storage device for measuring and recording a global bandwidth included in a memory arbitration apparatus in accordance with the present invention. FIG. 2 is a global bandwidth counter (GBC), a global bandwidth register (GBR), and a global bandwidth. Each setting register (GBSR) is shown.

The memory arbitration apparatus may set the global bandwidth counter (GBC), the global bandwidth register (GBR), and the global bandwidth setting register (GBSR) for each memory access unit (MAU). In FIG. 2, a register storing 32 bits is assumed, and MAU A and MAU B are taken as examples of each memory access unit (MAU).

The Global Bandwidth Counter (GBC) reads or writes data to a memory device after each corresponding memory access unit (MAU) requests a memory data bus from the memory arbitration device to obtain a license for the bus. Each memory access unit (MAU) stores a value that counts the memory global bandwidth used while the system synchronization signal (hereinafter, system_sync) is active.

The memory arbitration apparatus according to the present invention includes a system sync (system_sync) signal that is active at regular intervals, the global for each memory access unit (MAU) at the time when the system sync (system_sync) signal is active (active) The value of the bandwidth counter (GBC) may be stored in the global bandwidth register (GBR) for the memory access unit (MAU).

The memory arbitration device then initializes the global bandwidth counter (GBC) of each memory access unit (MAU) simultaneously with the storage. The memory arbitration apparatus transmits an interrupt signal to a host by using a system interrupt signal (hereinafter, system initial) which is activated at a predetermined period such as the system_sync signal. The host can be read out of the value stored in the global bandwidth register (GBR) of every memory access unit (MAU). Thus, the host can monitor in real time the bus demands required by each memory access unit (MAU).

The global bandwidth register (GBR) may store a value stored in the global bandwidth counter (GBC) when a system sink signal (system_sync) is active, the system sink (system_sync) to occur next to the stored value It can remain until the signal is active.

The global bandwidth setting register (GBSR) may set the amount of memory global bandwidth at a level that each memory access unit (MAU) may basically require.

Therefore, the memory arbitration apparatus according to the present invention measures the memory global bandwidth used by each memory access unit (MAU) in real time using a global bandwidth counter (GBC), and the measured value is measured in global bandwidth. Store in register (GBR). The memory arbitration apparatus compares the value stored in the global bandwidth register (GBR) with the value stored in the global bandwidth setting register (GBSR) to control the bus usage for each memory access unit (MAU) in real time.

Referring to FIG. 3, the operation of the memory arbitration apparatus including the global bandwidth counter (GBC) and the global bandwidth register (GBR) will be described below.

The signal represented by MAU_X_win (where X is A or B in FIG. 3) is a signal indicating that the memory access unit (MAU) X uses the data bus for the memory device. MAU_X_done represents a signal generated when the bus usage for the memory device of the memory access unit (MAU) X ends.

The MEM_State signal is a signal output from a state machine of a memory arbitration apparatus. In FIG. 3, a multi-bank access for accessing two banks to a synchronous dynamic RAM having four banks of the memory apparatus is shown. The case of (multi bank access) is shown as an example.

Hereinafter, a process of accessing the memory device by the memory access unit (MAU) will be described according to a cycle.

When the memory access unit (MAU) A approaches the memory device, the state machine outputs an idle signal (home) in FIG. 3, and then an active signal for the first row of bank 0. Output (act 1 in FIG. 3).

The state machine outputs a wait signal (a2w in FIG. 3) approaching the row, and outputs an active signal for the second row of bank 1 (act 2 in FIG. 3). do.

The state machine outputs an active signal c_b for the second column when the memory access unit MAU A approaches data (c_a of FIG. 3) for the first column. Access the data for the column (c_b in Figure 3). When the state machine outputs a precharge signal for the data (pal in FIG. 3), a time delay (p2h in FIG. 3) occurs.

MEM_DATA in FIG. 3 represents data transmitted on the data bus from the memory device to the memory access unit (MAU), and represents a section in which valid data is transmitted in black.

The global bandwidth counter (GBC) for the memory access unit (MAU) A and the global bandwidth counter (GBC) for the memory access unit (MAU) B are each the global bandwidth (MAU) used by each memory access unit (MAU) from the MEM_State signal. The global bandwidth) is stored in real time. The example of FIG. 3 illustrates a clock cycle when a memory access unit (MAU) A accesses one data in the first bank and three data in the second bank after the memory access bus (MAU) A acquires the right to use the memory data bus. clock cylce).

At this time, the value of the global bandwidth counter (GBC) of the memory access unit (MAU) A is the interval (B, the black interval + dummy in which data is actually transmitted) in which the memory access unit (MAU) A actually occupies the data bus on MEM_DATA. It is not a count value of one (dummy) section, but a count value of a state section on the MEM_STATE. However, in FIG. 3, section A and section B correspond to the same cycle.

In the event of a request for data read or write, the global bandwidth counter (GBC) for each memory access unit (MAU) in the memory arbitration unit is not limited to the data interval being transmitted on the data bus. Dummy section between data in command period and one read or write cycle required for transmission and between read or write cycle A dummy section is counted as a global bandwidth used by each memory access unit (MAU).

Thus, the global bandwidth counter GBC may cause a read / write cycle for a memory device executed by a memory access unit (MAU) to cause the other memory access unit (MAU) to actually see the data bus. Measurements can be made for the unusable intervals, allowing for more practical measurement of memory global bandwidth.

The lower part of FIG. 3 stores a value (GBC value) counted for the memory global bandwidth by each memory access unit (MAU) by the memory arbitration apparatus using the global bandwidth counter (GBC), and stores the stored value in the system. The process of storing in the global bandwidth register (GBR) by the signal of is expressed according to the system clock. Since the count value of the global bandwidth is stored in the global bandwidth register (GBR) only when a system sync signal is generated, the value stored in the global bandwidth register (GBR) for the memory access units (MAU) A and B in FIG. '0' unless signal is generated.

4 is a view illustrating a process of transitioning values stored in a global bandwidth counter (GBC) and a global bandwidth register (GBR) to monitor a global bandwidth for use of a memory device in a memory arbitration device according to the present invention. to be.

For example, when a system_sync signal, which is periodically active at intervals of 1/60 second, such as a display field synchronization signal, is active, the memory arbitration apparatus may perform each memory access unit (MAU). Stores the value of the Global Bandwidth Counter (GBC) in the Global Bandwidth Register (GBR) for the memory access unit (MAU). The memory arbitration device then initializes the global bandwidth counter (GBC). In this case, the value stored in the global bandwidth register (GBR) may be maintained until the next system_sync signal is active.

 The memory arbitration device activates a system interrupt signal after the system_sync signal to cause the host to read global bandwidth register (GBR) values for all memory access units (MAUs). Let's go. Thus, the host can ascertain the use of the memory global bandwidth of all memory access units (MAUs) in real time in the manner described above.

In FIG. 4, the interval 'A' indicates that the real time measurement of the global bandwidth counter (GBC) for any memory access unit (MAU) is equal to the value of the global bandwidth setting register (GBSR) of the corresponding memory access unit (MAU). Assume a large period. Nevertheless, the Global Bandwidth Counter (GBC) value (xxx or yyy in FIG. 4) is not stored in the Global Bandwidth Register (GBR) until the system_sync signal is active (xxx or yyy in FIG. 4). .

Next, in accordance with the present invention, a maximum memory, which is a time for which each memory access unit (MAU) waits to access the memory device in a storage device in which the memory arbitration device stores a maximum memory access latency for each memory access unit (MAU). The process of controlling bus usage by setting access memory (Max Memory Access Latency) is as follows.

FIG. 5 illustrates a storage device and a memory access unit (MAU) for counting a memory access latency counter (MALC) measured for each memory access unit (MAU) that can be set in the memory arbitration apparatus according to the present invention. For example, a maximum memory access latency register (MMALR) for storing a maximum memory access latency is shown. 6 is an operation timing diagram of a memory access latency counter (MALC) of a memory arbitration apparatus in accordance with the present invention. 5 and 6 show registers in the case where 32 bits can be stored. A description with reference to FIGS. 5 and 6 is as follows.

The memory arbitration apparatus sets a predetermined maximum memory access latency (MMAL) value for each memory access unit (MAU) in the maximum memory access latency register (MMLAR) of all the memory access units (MAU).

In this case, the maximum memory access latency register MMARL generates a signal req_x that the memory access unit MAU requests to access the memory device, and then the memory access unit MAU generates a predetermined time from the memory arbitration device. The storage device stores a time until an underflow or an overflow occurs in a buffer in the memory access unit (MAU) when the service for the access request is not provided.

Therefore, the maximum memory access latency is the shortest time that underflow or overflow occurs because access to the memory device is denied for every memory access unit (MAU), and thus every memory access unit (MAU). Can be set differently.

When each memory access unit (MAU) transmits a memory request signal (req_x) to access the memory device, the memory arbitration apparatus may perform a cycle in which all of the request signals req_x are active or It may include a memory access latency counter (MALC) for counting the pending period for each memory access unit (MAU) to store the memory access latency of each memory access unit (MAU) in real time.

The memory arbitration apparatus compares the value of the memory access latency counter (MALC) corresponding to each memory access unit (MAU) with the value of the maximum memory access latency register (MMLAR) of each memory access unit (MAU). The memory arbitration apparatus determines that the access priority and the stabilization of the memory access unit MAU when the value of the memory access latency counter MALC is equal to or greater than the value of the maximum memory access latency register MMLAR. The bus usage can be dynamically adjusted by resetting the starvation interval.

One bit of the maximum memory access latency register (MMLAR), e.g., the most significant bit, of the memory arbitration device according to the present invention may be used to turn on / off the function operation. If the memory arbitration apparatus regards a value stored in the bit as a function enable flag, when a value specific to the function setting flag, for example, "1" is stored, the memory access unit described above MAU) can be adjusted to adjust the access priority (priority) or the starvation interval (starvation interval). In contrast, the memory arbitration apparatus may disable the above-described function when another specific value, for example, "0" is stored in the function setting flag.

The above-described memory arbitration function can be used for the functional blocks where the memory access unit (MAU) should guarantee a certain amount of data transfer from the memory device. However, the memory arbitration device may not be used for a block for performing a variable amount of non real time characteristics such as an embedded CPU.

In addition, the memory arbitration apparatus may set a value smaller than the maximum memory access latency required for the corresponding function block in the maximum memory access latency register MMLAR corresponding to each memory access unit (MAU).

The bus arbitrator compares the value of the memory access latency counter (MALC) of the memory access unit (MAU) with the value of the maximum memory access latency register (MMLAR) of the memory access unit (MAU). Is greater than or equal to the value of the maximum memory access latency register MMLAR, the memory access unit is adjusted by adjusting an access priority and a starvation interval of the corresponding memory access unit MAU. Increase the priority for (MAU).

However, even if a memory arbitration device raises the priority for the memory access unit (MAU), if access to the memory device is already provided by another memory access unit (MAU) at that moment, access to that memory device is Since the memory access unit (MAU) cannot access the memory device until it is terminated, it is necessary to set the value of the maximum memory access latency register (MMALR) of each memory access unit (MAU) in consideration of the time of these elements. desirable.

The embodiment may be implemented in various forms, and the position where the flag is stored in the register or the stored value may be changed, but it is merely an example provided to complete the present disclosure.

7A and 7B show an example of a storage device included in a memory arbitration device according to the present invention. The example of FIG. 7A illustrates a starvation interval register (SIR) in which the storage device is configured as a register. The STATION Interval Register (SIR) is a FC Starvation Interval for bus access of a format converter, a VDEC Starvation Interval for bus access of a video decoder, and an audio decoder. The waiting period for bus access can be stored.

FIG. 7A illustrates an example in which a waiting period for each memory access unit (MAU) is stored as a 4-bit value. When a specific value, for example, “1111” is stored in the register, the value corresponds to a portion where the value is stored. The stabilization function of the memory access unit (MAU) may be disabled. Therefore, the memory arbitration device does not refer to the bus arbitration process for the results of the stabilization of the corresponding memory access unit (MAU).

FIG. 7B illustrates an example in which a priority for each memory access unit (MAU) is allocated by 4 bits for each memory access unit (MAU). The priority may be considered before the starvation data of FIG. 7A. For example, if the priority of a memory access unit (MAU) is set to "1111", it means that the memory access unit (MAU) has the highest priority value.

In addition, the memory arbitration apparatus according to the present invention may directly control a request signal for using a system memory bus of an arbitrary memory access unit (MAU) to limit the memory access that a plurality of memory access units (MAU) intend to use. .

8-9 illustrate the control of the request signal to control a system memory bus request by an arbitrary memory access unit (MAU) in accordance with the present invention, and FIG. 8 is an optional according to the present invention. 9 is a timing diagram illustrating an example of controlling a system memory bus request by a memory access unit (MAU), and FIG. 9 illustrates another example of controlling a system memory bus request by an arbitrary memory access unit (MAU) according to the present invention. Timing diagram.

As described above, the memory arbitration apparatus according to the present invention is characterized in that each memory access unit (MAU) controls the signal (req_x) requesting access to the memory device. Hereinafter, a method of controlling using the signal req_x according to the present invention will be described.

In FIG. 8, the memory arbitration apparatus according to the present invention sets the amount of memory global bandwidth basically required in a global bandwidth setting register (GBSR) for a certain period for each memory access unit (MAU). The memory arbitration apparatus compares a value of the global bandwidth setting register (GBSR) with the global bandwidth counter (GBC), which measures in real time the memory global bandwidth used by each memory access unit (MAU).

As a result of the comparison, if the specific memory access unit (MAU_X) uses more than the predetermined memory global bandwidth for a predetermined period, the memory arbitration apparatus according to the above-described priority and starvation value ) Was used. In this case, the priority and starvation values are not adjusted, but each memory access unit MAU controls the signal req_x requested for memory access.

To this end, the memory arbitration apparatus according to the present invention may have a control register for each memory access unit (MAU) in addition to the apparatus provided in the above-described method. In addition, the memory arbitration apparatus directly controls the request signal during a variable period (nothing or A or B or K) in real time according to the characteristics of each memory access unit (MAU) using the control register to directly control the corresponding memory access unit. The memory access of the MAU may be prohibited (that is, masking the memory access of the corresponding memory access unit MAU). Therefore, the memory arbitration apparatus can control the system memory bus request in real time.

In this case, the interval of 'A' is a real-time measurement value of the global bandwidth counter (GBC) for any memory access unit (MAU_X) is equal to the value of the global bandwidth setting register (GBSR) for the memory access unit (MAU_X). Interval of 'B' until the system synchronization signal (system_sync) is active until the value of the previous global bandwidth counter (GBC) is active until the next system synchronization signal (system_sync) is active. A section stored in the global bandwidth register (GBR) is represented, and a section of 'K' represents a section obtained by adding the sections of A and B.

In the present invention, the control of the system memory bus request using the control register in the memory arbitration apparatus will be described in detail as follows. First, the memory arbitration apparatus globalizes the amount of memory global bandwidth basically required for a certain period by each memory access unit (MAU_X in FIG. 8) for each memory access unit (MAU_X in FIG. 8). It is set in the bandwidth setting register (GBSR).

And stores the value of the global bandwidth counter (GBC) for each memory access unit (MAU) in the global bandwidth register (GBR) for the memory access unit (MAU). At this time, when storing in the global bandwidth register, as described above in FIG. 4, for example, when the system_sync signal, which is periodically active at intervals of 1/60 second, is activated. The storage is made. That is, when the system synchronization signal System_sync is active, the memory arbitration apparatus sets the global bandwidth counter (MAU_X GBC) value (xxx in FIG. 8) for the memory access unit MAU_X until then to the global bandwidth register (MAU_X GBR). Control to save).

The memory arbitration apparatus initializes the global bandwidth counter (GBC), and the value stored in the global bandwidth register (GBR) may be maintained until the next system synchronization signal (System_sync) is active.

Also, when the global bandwidth counter (GBC) value is stored in the global bandwidth register (GBR) as described above, the memory arbitration apparatus activates the "system_int" signal to activate all the memory access units (MAU) in the host. Read the Global Bandwidth Register (GBR) value for. Accordingly, the host may check the use of the memory global bandwidth of all the memory access units (MAUs) in real time.

Each memory access unit (MAU) then makes a request to the memory arbitration device according to the invention to access the memory device. As described above, when each memory access unit MAU requests a memory device access, a signal req_x is generated.

In this situation, the memory arbitration apparatus according to the present invention is characterized by controlling the memory access by appropriately controlling the access requests of the respective memory access units (MAU).

8 is a timing diagram for explaining a feature of the present invention according to the request signal of each memory access unit (MAU) and the control signal of the memory arbitration apparatus accordingly. In the lower part of FIG. 8, the first memory access request signal req_x indicates a basic request signal of the memory access unit MAU_X. The present invention provides a memory device by appropriately controlling a request signal of the memory access unit MAU_X. It is intended to provide a memory arbitration device that arbitrates to access a.

That is, when the memory arbitration apparatus according to the present invention receives the memory access request signal req_x of each of the memory access units MAU, it may determine this and generate the corresponding control signal req_x_ctl. In the above determination, the global bandwidth of each memory access unit may be compared in the case of FIG. 8. That is, the global bandwidth counter (GBC) value and the global bandwidth register (GBR) value for each memory access unit (MAU) may be compared with the global bandwidth setting register (GBSR) value of the corresponding memory access unit (MAU). The memory arbitration apparatus may control the memory access of the memory access unit MAU by generating a control signal to directly control the request.

In this case, the control signal is expressed assuming four cases, for example in FIG. When the memory arbitration device generates '00' as the control signal req_x_ctl to control the memory access, the same signal as the request signal is generated so that the memory can be accessed according to the request signal req_x of each memory access unit MAU. It means to happen. However, all of the control signals req_x_ctl may be signals for masking the request of the memory access unit MAU except when the control signal req_x_ctl is '00'.

That is, when the memory arbitration apparatus generates '01' as the control signal req_x_ctl, the memory arbitration apparatus may cause the request signal to be masked during the 'A' period. When '10' is generated as the control signal req_x_ctl, the memory arbitration apparatus may perform memory access during the 'A' period and mask the request signal during the 'B' period. When '11' is generated by the control signal req_x_ctl, the memory arbitration apparatus accesses the memory of the memory access unit MAU during the period 'K', which is the sum of the period 'A' and 'B'. The request signal req_x may be masked.

As shown in FIG. 8, by directly controlling a system memory bus request by an arbitrary memory access unit MAU_X in the memory arbitration apparatus according to the present invention, memory access between a plurality of memory access units MAU may be efficiently controlled. In contrast, in FIG. 9, the access intervals of each memory access unit (MAU) are compared, rather than the global bandwidth of FIG. 8.

Hereinafter, referring to FIG. 9, the memory arbitration apparatus according to the present invention may set and store its own minimum memory access interval for each memory access unit (MAU), and may include a minimum memory access interval register (MMAIR). And a memory access interval counter (MAIC) that counts memory cycles immediately after each memory access unit (MAU) receives a 'ack_x' signal for memory access from the memory arbitration device.

The memory arbitration apparatus according to the present invention compares the interval counted by the memory access interval counter (MAIC) with the interval set in the minimum memory access interval register (MMAIR) to prohibit the memory access of the corresponding memory access unit (MAU). It is done.

In this case, the memory arbitration apparatus compares the memory request unit again within a time shorter than an interval of a predetermined minimum memory access interval register (MMAIR). Disables memory access of the memory access unit (MAU) until at least a cycle set in the memory access interval register (MAIR) (masking a memory request of the memory access unit (MAU)). (Masking).

This will be described in detail with reference to FIG. 9, in which the memory arbitration apparatus firstly checks the minimum memory access interval of each memory access unit (MAU) in the minimum memory access interval register (MMAIR) of each memory access unit (MAU). 500 cycles). In addition, any memory access unit (MAU) that receives a 'ack_x' signal, which is a memory access permission signal, from the memory arbitration device, immediately after receiving the 'ack_x' signal to its memory access interval counter (MAIC), each memory access unit (MAU). Count the cycle of.

Accordingly, the memory arbitration apparatus according to the present invention compares the interval counted in the memory access interval counter (MAIC) with a preset interval in the minimum memory access interval register (MMAIR). The memory arbitration apparatus receives a memory access request from the corresponding memory access unit (MAU) within a time when the interval counted in the memory access interval counter (MAIC) is shorter than the interval preset in the minimum memory access interval register (MMAIR). If so, the memory access unit (MAU) prohibits the memory access request. In this case, the memory arbitration apparatus may prohibit a memory access request of the corresponding memory access unit (MAU) for a predetermined period, and the prohibition period may prohibit at least an interval set in the minimum memory access interval register (MMAIR). .

To do so, the memory arbitration apparatus according to the present invention prohibits the request for a predetermined period by directly controlling the 'ack_x' signal, which is a signal acknowledging a memory access request of the corresponding memory access unit (MAU), for the prohibition. King)

Accordingly, the system memory bus request of each of the memory access units MAU substantially activates the memory access request signal req_x after an interval (500 cycles in FIG. 9) preset in the minimum memory access interval register MMAIR. active)

For example, in FIG. 9, the memory arbitration apparatus receives a memory access request from a memory access unit (MAU) at a moment when the count value of the memory access interval counter (MAIC) is 402 cycles. However, the preset interval in the minimum memory access interval register (MMAIR) is 500 cycles greater than the 402 cycles.

Accordingly, the memory arbitration apparatus according to the present invention is the interval counted in the memory access interval counter (MAIC) as a result of the comparison is shorter than the interval set in the minimum memory access interval register (MMAIR), so that the corresponding memory access unit (MAU) Prohibit memory access requests. That is, the memory arbitration apparatus performs memory arbitration by prohibiting a memory access request of the corresponding memory access unit (MAU) for at least 500 cycles. Accordingly, the memory access request of the corresponding memory access unit (MAU) is masked in at least 403 to 500 cycle intervals, thereby preventing the access request.

In addition, as shown in FIGS. 8 and 9, a MAU_X_CNT control register is provided for each memory access unit (MAU), so that a memory bus request control arbitration algorithm is most suitable for the characteristics of each memory access unit (MAU). Arbitration Algorithm) can be selected and used. The memory bus request control arbitration algorithm according to the present invention described with reference to FIGS. 8 and 9 may not be used.

For example, when the memory bus request control arbitration algorithm of FIGS. 8 and 9 is not used, '00' may be set in the MAU_X_CNT register. In addition, if a memory bus request control arbitration algorithm corresponding to the case of FIG. 8 is desired, '01' is set in the MAU_X_CNT register, and a memory bus request control arbitration algorithm corresponding to the case of FIG. 9 is used, '10' may be set in the MAU_X_CNT register. If it is desired to use all of the memory bus request control arbitration algorithms corresponding to the cases of FIGS. 8 and 9, '11' may be set in the MAU_X_CNT register.

One bit of the maximum memory access latency register (MMLAR), e.g., the most significant bit, of the memory arbitration device according to the present invention can be used to turn the function on / off. If the value stored in the bit is referred to as a function enable flag, when a value, for example, "1" is stored as a specific value for the function enable flag, the memory arbitration apparatus may determine a memory access unit (MAU) as described above. It may be able to adjust the access priority (priority) or the starvation interval (starvation interval).

On the contrary, if "0" is stored in the function setting flag, the memory arbitration apparatus may disable the above-described function. The embodiment may be implemented in various forms, and the position where the flag is stored in the register or the stored value may be changed, but it is merely an example provided to complete the present disclosure.

According to the memory arbitration apparatus according to the present invention as described above,

First, each memory access unit monitors the memory global bandwidth currently used in real time to mask memory access of a specific function block for a variable period in real time. You can.

Second, the memory request cycle of all functional blocks can be monitored in real time to control the memory request cycle of a specific functional block.

Third, memory bus requests of all memory access units (MAUs) may be variably masked in real time.

Fourth, the performance and stability of the system can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (17)

A memory arbitration apparatus for controlling a memory access request for a memory device to which a plurality of memory access units can simultaneously access, A bandwidth setting storage device for setting and storing a reference bandwidth of a memory access request for at least one of the memory access units; A bandwidth counter that measures a bandwidth for a memory access request for one or more of the memory access units; A bandwidth storage device for storing the counter value; And And a first controller for controlling a system memory bus request of a corresponding memory access unit by comparing the values stored in the bandwidth counter and the bandwidth storage with a preset value of the bandwidth setting storage. The method of claim 1, The first control device, As a result of the comparison, when the value stored in the bandwidth counter and the bandwidth storage device is greater than or equal to the value set in the bandwidth setting storage device, the system memory bus request of the memory access unit is controlled for a variable period to mask the access of the corresponding memory access unit ( masking). The method of claim 2, The variable section, (1) none at all, (2) a period in which the bandwidth counter value of a particular memory access unit is equal to or greater than the value of the bandwidth setting storage device of that memory access unit, (3) a period in which the system signal is active and stores the previous bandwidth counter value in the bandwidth storage device until the system signal following the system signal is activated, (4) The apparatus characterized in that any one of the (2) and the (3) interval plus the interval. The method of claim 1, And a second control device capable of turning on / off the first control device. A memory arbitration apparatus for controlling a memory access request for a memory device to which a plurality of memory access units can simultaneously access, A minimum memory access interval storage device for setting and storing a minimum memory access interval for at least one of the memory access units; A memory access interval counter that measures memory cycles for one or more of the memory access units; And And a first controller configured to control the system memory bus request of the corresponding memory access unit by comparing the value measured by the memory access interval counter with a value preset in the minimum memory access interval storage device. The method of claim 5, The first control device, And if the value measured by the memory access interval counter is smaller than the value preset in the minimum memory access interval storage device, masking the memory access of the corresponding memory access unit. The method of claim 6, And the first control device masks the access to at least the predetermined value in the minimum memory access interval storage device. The method of claim 5, And a second control device capable of turning on / off the first control device. A memory arbitration apparatus for controlling a memory access request for a memory device to which a plurality of memory access units can simultaneously access, A bandwidth setting storage device for setting and storing a reference bandwidth of a memory access request for at least one of the memory access units; A bandwidth counter that measures a bandwidth for a memory access request for one or more of the memory access units; A bandwidth storage device for storing the counter value; A first control device for controlling a system memory bus request of a corresponding memory access unit by comparing the value stored in the bandwidth counter and the bandwidth storage device with a preset value of a bandwidth setting storage device; A minimum memory access interval storage device for setting and storing a minimum memory access interval for at least one of the memory access units; A memory access interval counter that measures memory cycles for one or more of the memory access units; And And a second controller configured to control a system memory bus request of the corresponding memory access unit by comparing the value measured by the memory access interval counter with a value preset in the minimum memory access interval storage device. The method of claim 9, The first control device, As a result of the comparison, when the value stored in the bandwidth storage device is greater than or equal to the value set in the bandwidth setting storage device, the system memory bus request of the memory access unit is controlled for a variable period to mask the access of the memory access unit. Device characterized in that. The method of claim 10, The variable section, (1) none at all, (2) a period in which the bandwidth counter value of a particular memory access unit is equal to or greater than the value of the bandwidth setting storage device of that memory access unit, (3) a period in which the system signal is active and stores the previous bandwidth counter value in the bandwidth storage device until the system signal following the system signal is activated, (4) The apparatus characterized in that any one of the (2) and the (3) interval plus the interval. The method of claim 9, The second control device, And if the value measured by the memory access interval counter is smaller than the preset value in the minimum memory access interval storage device, masking the memory access of the corresponding memory access unit. The method of claim 12, And the second control device masks the access to at least the predetermined value in the minimum memory access interval storage device. The method of claim 9, And a third control device capable of turning on / off the first control device. The method of claim 9, And a third control device capable of turning on / off the second control device. The method of claim 9, And a third control device capable of turning on / off the first control device and the second control device. The method of claim 16, The third control device, (1) turn on only the first control device, or (2) turn on only the second control device, (3) both the first control device and the second control device are on; (4) An apparatus characterized by controlling to select one of the cases in which both the first control device and the second control device are turned off.

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