KR20070096195A - Transcation processing method using a ram transaction buffer - Google Patents

Abstract

A transaction processing method using an RAM(Random Access Memory) transaction buffer is provided to shorten a processing time by reducing the frequency of EEPROM(Electrically Erasable and Programmable Read Only Memory) writing for processing transaction, thereby improving the performance of a smart card. A transaction processing method using an RAM(Random Access Memory) transaction buffer comprises the following steps of: starting a transaction process according to a transaction start signal(ST-2); storing data inputted or requested by a transaction processing routine in the RAM transaction buffer(ST-4); determining whether there is commit transaction and performing internal transaction if the commit transaction is generated(ST-6); and performing automatic roll back of the transaction if the commit transaction is not generated(ST-7).

Description

Transaction processing method using a RAM transaction buffer}

FIG. 1 is a diagram illustrating a data information structure expressed for EEPROM writing in an EEPROM Transaction Buffer according to the prior art.

2 through 6 are diagrams illustrating an EEPROM transaction buffer, an actual storage location, and a data information structure that occur during transaction processing.

7 is a diagram illustrating a data information structure in a transaction processing process using one RAM transaction buffer according to the present invention.

8 to 12 are diagrams illustrating a RAM transaction buffer, an actual storage location, and a data information structure that occur during a transaction process using a RAM transaction buffer according to the present invention.

13 is a flowchart illustrating a transaction processing process using a RAM transaction buffer according to the present invention.

Explanation of symbols on the main parts of the drawings

5a: RAM transaction buffer

6a: Ypyrom

61,62,63: storage area

21,211,212,213: data information structure

411: transaction start flag

412: transaction tail pointer

A, B, C: Real storage of EEPROM

The present invention relates to a transaction processing method using a RAM transaction buffer, and more particularly, to a transaction processing method using a RAM transaction buffer which guarantees the integrity of data while increasing the data processing speed using the RAM buffer.

When performing a data transaction on a smart card, the integrity of the data is compromised when the smart card is powered off or the card is removed from the card accepting device (CAD).

In order to prevent this problem, the existing smart card uses EEPROM as a transaction buffer to ensure data integrity.

However, using this EPROM transaction buffer takes more transaction processing time than RAM transaction buffer. This is because the data write time of Ipyrom is 1000 times later than the data write time of RAM.

However, the use of a RAM buffer can destroy data during power down, and thus cannot guarantee data integrity. In addition, the RAM buffer is used to implement a new method to ensure data integrity while increasing data throughput.

Transaction Definition

The general meaning of a transaction in a computer program is a series of contiguous tasks, such as exchanging information or updating a database, which are the basic units of work for accomplishing the requested task while ensuring the integrity of the database or stored data. Updates to the database or stored data that occur when a transaction completes successfully are called "commits", and modifications to the database or stored data when a transaction fails are called "rollbacks." In order to guarantee the integrity of a smart card, it is necessary to perform a transaction processing that guarantees integrity on almost all EPI data stored in a worse environment than a general PC.

1 is a view showing a data information structure expressed for EEPROM Writing in an EEPROM Transaction Buffer according to the prior art, Figures 2 to 6 is an EEPROM transaction buffer that occurs during transaction processing And a diagram showing the actual storage location and data information structure.

A transaction operation using an EPROM transaction buffer will be described with reference to FIGS. 1 to 6.

In general, an information structure 2 for one EEPROM writing may be represented as shown in FIG. 1. The address and length fields have a fixed length and are represented by 2-4 bytes. The stored data has the length of the length field value. In the end, a transaction can be represented as a sequence of the above data types. The reason why the previous data is expressed is that the above information has rollback information in order to process writing that is duplicated at the same address. The actual data is written immediately, and the data stored in the transaction buffer has rollback information. This has a processing advantage, considering what happens when rollback is abnormal. In addition, since the pointer to indicate the position in the transaction buffer must be changed to refer to the modified data in the transaction, the actual unit change data must have two EEPROM writings.

int A = 0;

int B = 0;

int C = 0;

Begin_Transaction (); ---------- Figure 2

A = 10; ---------- Figure 3

B = 20; ---------- Figure 4

C = A * B; ---------- Figure 5

Commit_Trasaction (); ---------- Figure 6

That is, each transaction is represented as shown in FIGS. 2 to 6.

At the start of a transaction, a transaction start flag 41 is set (FIG. 2). When A = 10; is performed, the first rollback information is stored and stored in the actual storage location 4b of Y. pyrom (FIG. 3). The following execution statement is similarly performed (FIGS. 4 and 5). That is, A, B, and C are stored in the storage areas 31, 32, and 33 of the actual storage place 4b. After the Commit is performed, the Transaction Start Flag 41 is reset (FIG. 6). You can see that Commit works normally, if A = 10; Assuming that the power is interrupted after execution, if it is set by checking the Transaction Start Flag (41) during the Boot Up routine, it can be known that the transaction was abnormally terminated. Turn. Reference numeral 42 denotes a transaction tail pointer of the EPROM transaction buffer 4a. Reference numerals 21, 22, and 23 denote EPIROM transaction buffer areas for the data structure.

Currently, smart cards that process transactions as described above are increasingly complex and burdensome to handle many tasks, and one transaction is increasing.

Therefore, according to the conventional method of performing a transaction using EPIROM transaction buffer, since EPIROM writing must be performed, there is a problem in that data processing time is long and performance is degraded.

An object of the present invention is to provide a transaction processing method using a RAM transaction buffer to ensure the integrity of the data while increasing the data processing speed using the RAM transaction buffer.

According to a preferred embodiment of the present invention for achieving the above object, a RAM for processing a transaction of a smart card comprising a CPU, a ROM, a RAM, EEPROM A transaction processing method using a transaction buffer, comprising: starting a transaction processing according to a transaction start signal; Storing the input or requested data in a RAM transaction buffer according to a transaction processing routine; Determining whether or not a commit transaction is performed and performing an internal transaction when a commit occurs; And automatic rollback processing when a commit does not occur in the commit transaction determination step. The transaction processing method using the RAM transaction buffer is provided.

Advantageously, performing said internal transaction comprises: retrieving a RAM transaction buffer; And storing data in the EPIROM if data exists in the RAM transaction buffer.

Also, preferably, the data information structure stored in the RAM transaction buffer may include fixed data, stored data having a length of an address, a length field, and a length field represented by 2-4 bytes.

Also preferably, the performing of the internal transaction may include searching for a RAM transaction buffer; Determining whether data exists in the same page when data exists in the RAM transaction buffer; And if the data exists in the same page, merging the data and storing the data in YPIROM.

Hereinafter, a transaction processing method using a RAM transaction buffer according to the present invention will be described in detail with reference to the accompanying drawings.

7 is a diagram illustrating a data information structure in a transaction processing process using one RAM transaction buffer according to the present invention, and FIGS. 8 to 12 illustrate a RAM transaction buffer occurring during a transaction process using a RAM transaction buffer according to the present invention. And a diagram showing the actual storage location and data information structure.

How to Use RAM Transaction Buffer Together

According to the present invention, similar to the EEPROM Transaction Buffer, the data information structure 210 stored in the RAM Transaction Buffer 5a is also represented in the form as shown in FIG. 7. The difference from the EEPROM Transaction Buffer will be explained later, but the data to be committed will be saved and will not be changed until it is committed.

int A = 0;

int B = 0;

int C = 0;

Begin_Transaction (); ---------- Figure 8

A = 10; ---------- Figure 9

B = 20; ---------- Figure 10

C = A * B; ---------- Figure 11

Commit_Trasaction (); ---------- Figure 12

That is, each transaction is represented as shown in FIGS. 8 to 12.

Here, the Transaction Buffer 5a, Transaction Start Flag 411 and Transaction Tail Pointer 412 are RAM areas. At the start of a transaction, a Transaction Start Flag 411 is set (FIG. 8). When A = 10; is performed, the first change data is stored in the Ram Transaction Buffer 5a, and the actual storage location of the Y pyrom 6a is not changed (FIG. 9). The following execution statement is similarly performed (FIGS. 10 and 11). That is, A, B and C are stored in the storage areas 61, 62 and 63 of the actual storage place of the Y pyrom 6a. After the Commit is performed, the Transaction Start Flag 411 is reset, and all the contents in the Ram Transaction Buffer 5a are written to the actual storage place of the YPIROM 6a (FIG. 12). However, the integrity of the writing that occurs at the time of commit should be guaranteed. For this, internal transaction processing is performed using EEPROM Buffer. Internal transaction processing uses the EEPROM Transaction Buffer method mentioned in the prior art. The actual final change ensures integrity by using the EEPROM Buffer. In other words, it uses the RAM Buffer until Commit and uses EEPROM Buffer again in Commit to ensure integrity. Now let's look at Rollback, if A = 10; Assuming that the power is cut off after execution, all changes are saved in the RAM Transaction Buffer, so they are automatically rolled back even if no action is taken. Reference numerals 211, 212 and 213 denote RAM transaction buffer areas for data structures.

Unlike the EEPROM Transaction Buffer, the reference to the changed contents in the Transaction is a problem. In the following case

int A = 0;

int B = 0;

int C = 0;

Begin_Transaction (); ---------- Figure 8

A = 10; ---------- Figure 9

B = 20; ---------- Figure 10

C = A * B; ---------- Figure 11

A = A + C; ---------- Process similar to FIG. 11 (S-1)

B = B + C; ---------- Process similar to that of FIG. 11 (S-2)

Commit_Trasaction (); ---------- Process similar to FIG. 12 (S-3)

In the case of the above steps S-1 and S-2, the cache algorithm (not shown) is applied to handle the case where A and B are changed again. RAM Transaction Buffer (5a) is searched first, and if a corresponding storage location exists in RAM Transaction Buffer, this value is referred to.

Performance comparison

In addition, transaction processing using Ram Buffer shows almost the same performance when only one EEPROM Buffer is modified once for one storage location. However, if the same storage location is changed many times in a transaction, a significant performance improvement is obtained. In other words, as described above

int A = 0;

int B = 0;

int C = 0;

Begin_Transaction (); ---------- Figure 8

A = 10; ---------- Figure 9

B = 20; ---------- Figure 10

C = A * B; ---------- Figure 11

A = A + C; ---------- Process similar to FIG. 11 (S-1)

B = B + C; ---------- Process similar to that of FIG. 11 (S-2)

Commit_Trasaction (); ---------- Process similar to FIG. 12 (S-3)

In the case of the above process S-1, S-2, A = A + C, B = B + C; EEPROM Writing occurs to process the change data of two sentences, but if RAM Buffer is added, it can be processed without EEPROM Writing. In general, as smart cards are dealing with more and more complex tasks, a transaction grows and the performance improvement due to the use of Ram Buffer together will greatly affect the overall performance.

13 is a flowchart illustrating a transaction processing process using a RAM transaction buffer according to the present invention.

First, the CPI of the smart card (not shown) determines whether to start a transaction (this process is a general card reader process, so a detailed description thereof will be omitted) (ST-2). If it is determined in step ST-2 that the transaction has been started, the result of execution is stored in the RAM transaction buffer area of the RAM (ST-4). This process may continue according to the transaction processing process defined by the user. Thereafter, the CPI of the smart card determines whether or not a commit transaction (ST-6). If the commit transaction is not executed, an automatic rollback process is performed (st-7).

On the other hand, when the commit transaction is performed as a result of the determination of step ST-6, an internal transaction is performed by applying a cache algorithm (a detailed description thereof is omitted) (ST-8). After step ST-8, a process of searching for a RAM transaction buffer is performed (ST-10). Thereafter, if data exists in the RAM transaction buffer, the data is stored in YPIROM (ST-14). This completes transaction processing.

Meanwhile, in the internal transaction execution step (ST-8), when data exists in the RAM transaction buffer, a step of determining whether the data exists in the same page may be additionally performed, and the data may be the same page. If present, the method further includes merging the data and storing the data in YPyrom. Such a process is called a merge process, which uses the characteristics of Y. pyrom. That is, YPIROM has a characteristic of being stored in units of pages. It takes the same time to write 1 byte for an address within such a page or to write the whole page, for example, 64 bytes or 128 bytes (not limited to each company). Using this feature, the RAM transaction buffer is merged to the nearest address, that is, the same page content, before the commit is completed. In the example of FIG. 10, if the actual storage locations A, B, and C are in the same page, the actual writing is to merge the RAM transaction buffer so that it occurs only once. Because of the merge process for the same page before the commit is completed, the storage for the same page is also significantly reduced. In general, as smart cards are dealing with more and more complex tasks, and one transaction is growing, the performance improvement from using RAM buffer will greatly affect the overall performance.

According to the transaction processing method using the RAM transaction buffer according to the present invention as described above, the processing time can be shortened by reducing the number of EPYROM writing for transaction processing as compared to the conventional transaction processing method using EPIROM transaction buffer. Due to this, there is an effect that can improve the performance of the smart card.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but by the claims and equivalents of the claims.

Claims (4)

In the transaction processing method using a RAM transaction buffer for processing a smart card transaction including CPU, ROM, RAM, EEPROM, Starting transaction processing according to the transaction start signal; Storing the input or requested data in a RAM transaction buffer according to a transaction processing routine; Determining whether or not a commit transaction is performed and performing an internal transaction when a commit occurs; And Automatic rollback processing when a commit does not occur in the step of determining whether or not the commit transaction. Transaction processing method using a RAM transaction buffer, characterized in that made. The method of claim 1, wherein performing the internal transaction   Retrieving a RAM transaction buffer;   And storing the data in EPIROM if data exists in the RAM transaction buffer. The data information structure stored in the RAM transaction buffer has a fixed length and is composed of stored data having an address represented by 2-4 bytes, a length field, and a length field value. Transaction processing method using RAM transaction buffer. The method of claim 1, wherein performing the internal transaction Retrieving a RAM transaction buffer; Determining whether data exists in the same page when data exists in the RAM transaction buffer; And merging the data when the data exists in the same page, and storing the data in EPIH. 2.

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