KR20070094646A - Method for operating a passive matrix-addressable ferroelectric or electret memory device - Google Patents

Abstract

In a method for operating a passive matrix--addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Description

METHOD FOR OPERATING A PASSIVE MATRIX-ADDRESSABLE FERROELECTRIC OR ELECTRET MEMORY DEVICE}

The present invention relates to a method for operating a passive matrix addressable ferroelectric or electret memory device, wherein the memory device is in the form of a ferroelectric or electret thin film polarizable material exhibiting hysteresis, in particular in the form of a ferroelectric or electret polymer thin film One or more arrays or matrices of cells, and a first set and a second set of parallel electrodes, respectively, wherein the first set of electrodes forming word lines WL in the device are bitlines BL in the device. Are provided in a substantially orthogonal relationship with the second set of electrodes forming the electrodes, wherein the first and second sets of electrodes are provided in direct or indirect contact with the thin film material of the memory cells, thus providing separate memory The polarization state of the cells is characterized in that the first and first of each of the electrodes Can be read, erased, or written by applying an appropriate voltage to an individual electrode in two sets, wherein the method implements a voltage pulse protocol based on a 1/3 voltage selection rule to switch to unaddressed cells not to exceed about one-third of the voltage (V _S) to the discharge ends thereof Tubingless (disturbing) voltage is applied, the voltage pulse protocol a predetermined amplitude, each consisting of a read to the time sequence of the voltage pulse having a polarity and cycle length And a write / erase cycle, wherein the read cycle includes applying a set of voltage differences to the first and second set of electrodes of each of the electrodes when data is read from the memory cells, and write / erase The cycle includes applying another set of voltage differences to the electrodes of the first and second set of electrodes respectively.

The construction of a suitable device as described above is well known in the art and is generally referred to as a passive matrix-addressable memory. As shown in FIG . 1 , two sets of parallel electrodes intersecting with each other (m _k) , in order to create a matrix of electrically separate accessible cross points by selectively excitation of the appropriate electrodes at the edge of the matrix. It is generally implemented by placing (k = 1 → x), n ₁ (l = 1 → y) in a conventional orthogonal manner. A functional (eg, storage) media layer S made of ferroelectric or electret material is provided between or over the electrode sets, so that capacitor-like structures 2 _kl are electrodes (functioning like memory cells). Between m and n or in the material in which they intersect. This is shown in detail in FIG . 2 , where the cells 2 _kl are formed in overlapping regions 3 and 4, respectively, between the electrodes m _k and n _l . The selection of individual cells in the matrix is shown in FIG. 3 . According to standard usage, each horizontal electrode will now be referred to as a word line WL, and each vertical electrode will be referred to as a bit line BL. In addition, the electrodes used to electrically select one cell or a set of cells in the matrix will be referred to as the active word line AWL and the active bit line ABL. Applying a potential difference between AWL and ABL places an electric field on the ferroelectric or electret material of the selected cell, which produces a polarization response that typically represents a hysteresis curve or part of it. By manipulating the direction and magnitude of the electric field, the memory cells can be present in the desired polarization state corresponding to any logic value. Passive addressing with this type of arrangement allows for easy manufacturing and high density intersections.

When ferroelectrics or electrets are used as memory materials, the memory device becomes nonvolatile by using a characteristic that maintains a logic state even when no voltage or current is applied to the memory device. In particular, such properties of ferroelectrics are known, and attempts have been made in the prior art for memory devices. These electrically polarizable materials are based on the fact that they have at least two equilibrium orientations of spontaneous polarization vectors in the absence of external electric fields. Natural polarization vectors can be switched between these two directions via an electric field. One polarization state is considered a logic "1" and the other state is considered a logic "0". 4, the material having shown a hysteresis curve, the coercive force field (coercive field: E _C) for applying an electric field greater than changes the polarization direction of the material (on the hysteresis curve the horizontal axis is the cell across the non-convenience field Shown in voltage). Saturation polarization P _S is obtained when a nominal switching voltage V _S is applied to a memory cell. As the applied voltage decreases to zero, the polarization will end at the remanence value (P _R ) along the hysteresis curve. Depending on the polarity of the applied voltage, this zero field point may be one of the polarization states labeled "1" or "0" in the figures, and may represent a cell with two accessible logic states. Can be.

It should be noted that the shape of the hysteresis curve can be determined depending on the rate at which ferroelectric and electret materials circulate, the characteristics of the electrodes used to create the ferroelectric cell, and other factors (eg, temperature). In particular, when cycled at low speeds, while many materials exhibit a hysteresis curve as shown in FIG. 4, as the voltage slew rate increases, the apparent coercive field may increase, The apparent residual polarization can be reduced. Conversely, at very low rotational speeds, the apparent coercive field can be drastically reduced or approach zero, especially in pure electrets without ferroelectrics that affect polarization. In addition, if a low dielectric constant layer is present on or generated on the electrode (eg, due to chemical reactions at the electrode interface in contact with the electret or ferroelectric material), the apparent coercive field will be increased. It should be understood that the terms "Coercive field" or "Coercive voltage" and "Remanent polarization" are used to refer to the corresponding amounts in FIG. 4 when used next, These mean that they will appear dominant while applying the teachings in this document under certain operating conditions.

There are some problems with polarizing materials that must be addressed to make commercially viable devices, such as fatigue, imprint and disturb.

Fatigue occurs due to repeated switching in the polarization direction in a given memory cell, whereby the switchable polarization gradually decreases, eventually becoming too small to prevent proper operation of the memory. This phenomenon is well known and there are certain solutions in the prior art. However, these solutions are generally limited to specific materials and are inadequate to provide fatigue resistance to commercially viable devices.

Imprint affects memory cells that are allowed to maintain a given logic state for a period of time. This is manifested as a change in switching properties, ie the hysteresis curve shifts, increasing the coercive field detected when the material switches the polarization direction in the opposite direction to where it was during the imprinting period. In other words, polarization tends to prevent movement in the direction in which it has existed for some time.

Disturbance is a given polarization state when the cell is exposed to a disturbing voltage pulse with a polarity in the opposite direction (i.e., the direction in which it tends to polarize the cell in a sense against the intended direction). It relates to the polarization loss in the ferroelectric or electret memory cells that have been prepared. Even when the disturbing voltage is completely below the voltage corresponding to the coercive field, repeated exposures can cause the memory material to undergo partial switching causing polarization loss. The partial switching range depends on the material properties, but may eventually be reduced to the extent that results in misreading of the residual polarization states (P _R and -P _R ).

In the three problem areas mentioned above, fatigue and imprint include all types of devices, including both devices using one or more transistors per memory cell (hereinafter referred to as active matrix devices) and passive matrix devices as mentioned above. Related to ferroelectric or electret memory structures. Solutions known in the art are methods for delaying or reducing the occurrence of fatigue and imprint, and for restoring the memory material of fatigued and imprinted cells to their original or less affected state. And devices. Typically collectively, the latter process is referred to as a "leaf lash (refresh)".

Before proceeding, it should be emphasized that the present invention relates to a different type of reflash than that used in the prior art for volatile memory, such as DRAM of different types, wherein memory cells are generally refreshed every 64 msec. This type of "traditional" memory refresh is typically performed to compensate for the loss of charge stored in the capacitor, including the linear high-epsilon dielectric, thus allowing the logic value stored in each memory cell to be maintained. In general, refreshing entire memory at once will cause large surges in terms of power and stalls in terms of data requests. Do not. To solve this, the refresh is divided into one row / block of memory at each time, so the refresh period is equal to, for example, 64 msec / row.

Contrary to the passive matrix form, the active matrix form of the ferroelectric memory has more prominent problems such as fatigue and imprint, and requires a relash to maintain volatile polarization at an appropriate level and to restore the properties of the ferroelectric memory material. .

In US Pat. No. 5,550,770 (Kuroda), the memory device consists of arrays of ferroelectric memory cells, exclusively illustrated as including a ceramic ferroelectric, such as BaTiO or PZT, in an active-matrix block addressing configuration of 1T-NC type. do. In order to allow a simple Vs / 2 selection scheme, N is a low number, for example N = 8. Since write operations are considered to require a refresh, there is one counter per memory block that is used to store the number of write operations completed before a forced refresh is performed. This is done by first performing a destructive read on all cells of the memory block and temporarily storing this data elsewhere. And every cell of the memory block is exposed to a voltage higher than the write voltage in order to achieve a retrace by re-polling. Eventually, the temporarily stored data is written back, so that the polarization is switched only for those cells except those that are already at the desired polarization at that time. In addition to the above, Kuroda also recommends that the retrace voltage be higher than the voltage used in the standard read / write access, as well as the pulse shape, duration, degree of overvoltage, polarity shift, if necessary, number or standby periods. It does not provide any examples or content regarding the proper selection of voltage pulse parameters.

In US Pat. No. 5777921 (Takata et al.), An apparatus having two counters for each memory block or memory cell is disclosed, one for write / read one type of logical data, and the other for read / write. Is for other forms of logical data, where the refresh is initialized when one of these counters reaches a predetermined value. Depending on the counter that initiates the leaflash, the applied leaflash voltages will look different, so the ferroelectric material is claimed to be a known method for recovering from the deterioration of the naturally occurring electric field, i.e. eliminating the imprint effect. You will experience a complete hysteresis curve. By paying attention to the data content, the refresh can be more efficient in terms of time for one type of logical data, and there is no need to temporarily store the data elsewhere during the refresh. In the case of a refresh based on memory-cells or small memory blocks, redundancy in which cells are allocated for unnecessary refreshes can be avoided, but at the cost of more counters.

In European Patent No. 0495572 (Moazzami et al.), The "higher than normal" voltage is periodically "refreshed or re-established, the polarization state" in order to "refresh or re-establish the polarization state." Used to operate the ferroelectric components ", and the refresh is further initialized after a predefined number of memory access cycles and / or a predefined period of time.

In the prior art found, no particular attention is paid to the problem of imprint at power up , ie the memory has not been used actively for a period of time. Since the period may be arbitrarily long, there is substantially a risk of imprint, and if the inactive period is not known, the state of maximum imprint should be assumed and should be dealt with accordingly.

In a passive matrix type ferroelectric memory, the absence of active elements in each cell allows for higher integration density, lower power consumption and lower complexity than based on an active matrix. However, the issues of fatigue and imprint must be addressed, as are the phenomena which cause further damage of the above-mentioned " disturb ". Passive matrix memories do not have active elements such as transistors that can connect / disconnect each memory cell with the rest of the matrix network during write / read / erase operations, and any operation involving one cell access In the meantime, it is inevitable to apply a distorting voltage to unaddressed memory cells. Of the force applied to the non-addressed cells display Tubingless voltage size, which depends on the addressed cells, as well as associated with the non-addressed cells, a word line and the timing and magnitude of the voltage applied to the bit lines in the matrix, the prior art document voltage Avoiding these complications by the use of pulsed protocols -that is, precisely defined time and amplitude relationships between electrical potentials applied to all bitlines and wordlines during operation of passive matrix addressed memory arrays. Include instructions on how to reduce or reduce it. Examples of pulse protocols that include coordinated sequences of operations, such as applying several sets of voltage pulses, connecting a sense amplifier, ground, and the like, are described in US Patent No. 3002182 (Andersson), US Patent No. 4169258 (Tannas Jr.) and published international patent application WO 02/05287 (Thompson et al.).

Unfortunately, even the best designed pulse protocols are subject to fundamental limitations, and the fundamental problem of disturb can generally not be eliminated by these means alone. As disclosed in above-cited WO 02/05287, random access to the single cells associated with the read or write via the voltage _{(V S) (random access to} single cells) are, in the non-addressed cells approximately V _S / 3, and It will always imply that similar or higher disturbing voltages are applied. In the following, V the non-addressed cells _S / 2 or V _S / 3 protocol for exposing a maximum disturbing voltage will be referred to as respectively V _S / 2 and V _S / 3 protocol. Although V _S / 3 is generally fine because it is less than the voltage needed to exceed the coercive field in the memory material of the cells, repeated exposure will result in a gradual loss of polarity and hence loss of content information. The disturb problem is particularly fatal in highly memory devices, which generally seek to take full advantage of the passive matrix addressing concept by using large matrices with thousands of wordline and bitline crossings. This can result in a very large number of disturbing voltage pulses between each time an unaddressed cell in the matrix is accessed for a write, read or erase operation. It may be the end result that any cell suffers a polarization loss until the magnitude of the polarization switching during the read operation falls below the identification threshold between logic "0" and logic "1".

One possibility to minimize disturb in a large passive matrix based memory is to divide each large matrix into multiple segments physically or electrically, where each said segment or "sub-matrix" is its own passive. It may look like a matrix. A proper definition of a passive sub-matrix is that a memory cell that is addressed within any sub-matrix, for example, during a read or write operation, may have a disturb voltage on other memory cells of the same sub-matrix rather than another sub-matrix in memory. Will only cause it. Segmentation has been described to a limited extent in the prior art, and the main concern has been to reduce parasitic capacitance effects and sneak / relaxation current effects, which delay and worsen the electrical response of large passive matrix structures. . Examples of divisions / divisions are disclosed in the ongoing patent application NO 20035225 herein.

Exacerbating the disturb problem of passive matrix addressed devices is that, after a cell is in a polarized state, on a very short timescale-for example, during a single pulse sequence under a protocol for normal write / read / erase operations. Imprint is starting to develop. Thus, memory cells that have recently experienced operation involving polarization reversal at one point with the voltage pulse protocol will maintain significant imprint in the pre-reversal direction in the next step with the same voltage pulse protocol. Can therefore be further disturbed. Since both imprints and disturbs are generally affected by fatigue, it is clear that a successful strategy to control these phenomena must take into account strong interrelationships between them.

In view of the above considerations, a primary object of the present invention is to avoid or reduce the deleterious effects of implants and disturbs in memory, displays, or processing devices based on electrets or ferroelectrics in passive matrix addressed configurations. It provides a basic strategy to make or reverse.

It is another main object of the present invention to disclose certain methods and procedures for extracting data from memory cells comprising highly imprinted electret or ferroelectric materials.

Another major object of the present invention is to disclose certain methods and procedures for conditioning or restoring electret or ferroelectric materials after imprint has developed.

It is another main object of the present invention to disclose certain methods and procedures for reflashing or restoring the polarization state of an electret or ferroelectric in cells to which a disturb has been applied.

It is another main object of the present invention to disclose an apparatus for implementing the above-mentioned strategies, methods and procedures.

The above objects according to the invention are realized by providing methods and structures which enable the polarization of electrets or ferroelectrics in individual cells according to any electric drive protocol, the latter being caused by electrical and environmental effects on the same cells. Consider the history of, and the operational requirements of the device in which the cells are located.

The method is characterized by including a re-lash procedure including the following steps.

a) selecting the one or more cells for the refresh according to a criterion programmed in the memory device controller and inputting the addresses of the selected one or more cells into the relash request processed by the controller

b) a second step of monitoring and processing the refresh request and initiating the refresh procedure, taking into account active or reserved memory operations and priorities assigned thereto;

c) One or more cells selected for relashing voltage pulses having a defined polarity with a magnitude equal to or higher than the coercive voltage and having a defined polarity, while a voltage that is significantly smaller than the coercive voltage is applied to all unselected cells. Applied at the same time, the third step

d) A train of one voltage pulse or voltage pulses-at least one of the voltage pulses being similar to or greater than the coercive voltage, while a significantly smaller voltage or 0 V is applied to all unselected cells relative to the coercive voltage. A fourth step, having a high magnitude and a polarity opposite to the positioned polarity in step c) simultaneously to all selected cells

Other features and advantages of the invention will be apparent from the accompanying independent claims.

The invention will be better understood from the following discussion of the general background and various preferred embodiments with reference to the following figures.

Figure 1 shows a basic passive matrix arrangement as mentioned above, with horizontal wordlines and vertical bitlines intersecting as described in more detail above, with cells superimposed with wordlines and bitlines intersecting with each other. Located in the volume.

FIG. 2 shows a cross section of one of the cells belonging to the matrix of FIG. 1 as mentioned above.

FIG. 3 shows a given cell in a passive matrix achieved by controlling the potential at one wordline (active wordline: AWL) and one bitline (active bitline: ABL) that intersect each other in the selected cell as mentioned above. The electrical choice is shown.

4 shows a generalized hysteresis curve for a capacitor filled with electret or ferroelectric in the absence of an imprint phenomenon, as mentioned above. Important features are indicated, including the coercive force voltage (V _C ) and residual polarization (P _R ).

5a) -f) show a generalized hysteresis curve for an electret or ferroelectric filled capacitor at various stages of imprint related to residual polarization in the + and − directions.

Figure 6 shows a passive matrix memory in which all cells in all rows on a wordline are read simultaneously.

7A) and b) show examples for voltage pulse protocols that perform a read / refresh / write sequence.

8a) and b) show examples for voltage pulse sequences used in the present invention.

9A shows an example of the application of the pulse protocol of a passive matrix memory, using the 1/3 voltage selection rule known in the art and used in the present invention.

9B shows an application of the pulse protocol to a matrix memory without disturb on unaddressed cells.

10 illustrates an embodiment of the invention using wordline mapping and applied to a partitioned matrix memory.

Fig. 11 shows an embodiment of the present invention applicable to a matrix memory when most of the memory has not been accessed for a long time.

Figure 12 illustrates an embodiment of the present invention that is suitable for the backlash of highly imprinted memory cells.

Before describing the invention in greater detail, the general background of the inventive idea will be discussed briefly.

Imprint phenomena are believed to be universally present in all ferroelectric materials attempted so far in ferroelectric-based memory devices, where the materials include both inorganic (ceramic) and organic (polymeric) materials. However, the severity of imprinting varies over a wide range and can be affected by processing and material changes. Typically, the imprint develops rapidly (from a few milliseconds to several seconds) when the material is polarized in a given direction, and then in some cases a logarithmic relationship to time up to a very long time (hours to years). (logarithmic time dependence), and in other cases it appears to flatten out to a fixed value for a long time, gradually developing gradually.

The model for describing the imprint phenomenon includes a ferroelectric and charge migration within its interface in response to an internal field of the ferroelectric cell. In order to provide a method of improvement as described in the present invention, a detailed understanding of the underlying mechanisms is not necessary, but this subject will not be pursued here any further. The basic premise for the present invention is that imprint can be mitigated by using the electric field stress in the electret or ferroelectric material of the memory cells discreetly. This is based on extensive experimental data accumulated for a series of related substances.

5A-F , the shift of the hysteresis curve is associated with the memory material polarized in the + P _r or -P _r state. The cell is initially assumed to be a non-imprinted state with residual polarization -P _r as shown in FIG . 5A . How this is achieved is not essential in the following discussion. At some given time, it is switched to + P _r as shown in FIG . 5B and allowed to remain in this state. Afterwards, the imprinting process gradually shifts the hysteresis curve to the left, eventually moving completely as shown in FIG . 5C . In this regard, it may be appreciated that imprinting tends to fix polarization in the imprinted state . Applying a voltage in the positive polarity direction will immediately induce excursion along the saturated top of the hysteresis curve (i.e., the portion of the curve where the non-switching dielectric response predominates) and the voltage is removed. When the polarization returns to + P _r state. Applying a voltage in the polarity direction will not cause any perceptible switching in the + P _r state until the magnitude of the voltage significantly exceeds the non-imprint coercive voltage (-V _C ) shown in FIG. 5C. will be. If a sufficiently high switching voltage of polarity is applied then it will return to zero, and as shown in FIG . 5D , the cell will switch and terminate to the -P _r state. If this occurs on a short time scale when compared to the imprinting process, the cell will initially respond according to the applied voltage according to the hysteresis curve shown in FIG. 3D. Over time, the hysteresis curve will gradually shift to the right, developing into a temporary, non-imprint state as shown in FIG . 5E , and eventually a new imprint showing -P _r polarization as shown in FIG . 5F . Finish in the state. Indeed, the speed and final state of the process depends not only on the size and duration of the switching pulse, but also on various other factors, including the materials and processes used to create the cell structure. In many cases it has been observed that imprint and disturb properties are affected by the switching history (fatigue) of the cell and environmental parameters such as humidity and temperature.

An important consequence of the above is that a cell that is in one of two residual states (+ P _r or -P _r ) will always be imprinted in one direction or the other if left in one of these states for a long enough time. will be. Thus, in a memory device operating under normal write / read / erase protocols where polarization is always present in the cells and may experience reversal of direction but not diminish to zero, the non-imprint state may be partial or complete in polarization. It is only faced as part of the dynamic situation in combination with the pulse causing the switching. As a result, procedures that cause the cell to be non-imprinted may only be useful if the operations occur on a short time scale relative to the typical time required for the imprint to develop (temporarily move the cell in the original direction of the imprint). An example of a process for creating an essentially non-imprint state irrespective of it is to apply a series of pulses of sufficient intensity to lift the cells in the original imprint state, which will cause the imprint to develop in either direction. On the other hand, when the object is performing an operation on these cells at an unspecified time, the small amount obtained through the refreshing process to remove the imprint from the cells exist.

Returning to FIGS. 5A-F , it is simple to find that the imprint and the disturb are deeply connected: if the cell is ready for a given polarization state and is allowed to imprint as shown in FIG . 5C for the + P _r state It is effectively fixed in this state and can withstand significant disturbance voltage stress without loss of polarization. On the other hand, if the cell was recently switched in the imprint state and left in the opposite polarization state, the effective coercive field for switching back to the imprint state is much less than -V _C. This can be clearly seen in FIG. 5D , where the application of a suitable voltage in the + direction will result in a transition to the + P _r state. Therefore, Even when under the recording protocol that limits the discharge Tubingless voltage to V _S / 3 operation, the imprint is not allowed to be sufficiently long cells maintained (unperturbed) without change to the new state in stabilizing the new state, and the remaining Significant back-switching can occur with the resulting loss of polarization (see FIGS. 5E, 5F ).

In accordance with the foregoing, the present invention is based on a precept that the dynamic nature of the imprinting process can result in reflash or recovery operations on memory cells through the sensible selection of pulse sequences. Relash is effective within timeframes that allow read and write operations.

The above objects are achieved by applying a multi-step retrace process , the basic elements of which are as follows:

In the first step, cells that are subjected to retrace are selected. This is performed according to a criterion programmed in the controller of the memory device, and the selected cells may include from one memory cell or word line until the entire memory device is included. After the selection, the refresh request shark is set in the controller.

In a second step, a request for a refresh is processed taking into account ongoing or scheduled memory operations and priorities assigned to them, and the refresh voltage pulse sequence is initiated.

In a third step, the initializing pulse in the refresh sequence is applied to the selected cells. Since these pulses destroy any data that was stored before the application of the pulse, a command for temporary storage (for example in the case of a refresh with re-write) or data transfer (in the case of reading) must be provided. do.

In a fourth step, the remaining voltage pulses of the refresh sequence are applied.

Optionally, in the next writing step in which temporarily stored or new data is to be written to the refreshed cells, a write pulse sequence is applied using either a full word or single cell write protocol. This step must be performed when the beneficial effects of relash still remain.

The first stage of the relash process will now be discussed. As is evident from the description of the background above, the selection of cells to be refreshed must take into account external parameters and processes that are deployed simultaneously and interdependently with each other. Thus there is a progressive development of imprint that holds polarization in place, resulting in a slower and reduced switching response during disruptive readout. This is above all a time integration effect and is essentially independent of disturb voltage stress, but potentially dependent on the temperature and fatigue state of the cells concerned. Adding this disturb effect to the imprint, the dynamic development of the imprint becomes important not only for the short time scale but also for the long time scale. After all, so many repetitive disturbs can cause a gradual decline of polarization, even in very imprint-stable cells. Given any pulse protocol for operating a memory device (eg, incorporating a V _S / 3 write protocol) and with so many disturbances, the decision as to when to perform a refresh operation is typically a disturb event. It will be determined by the number of.

In accordance with the present invention, three types of decision modes can be invoked to select the cells to be refreshed. These will be described under categories such as Default mode, Predictive mode, and Feedback mode.

1) Default mode: preferred embodiment.

In this mode, the reflash / recovery operations according to the present invention are implemented automatically, i.e., independent of any evaluation or cognitive level of imprints and disturbs in the cells being refreshed.

According to one preferred embodiment of the present invention, this means that whenever a matrix or memory device, where the matrix is part of the memory device, is idle or after a period of time switched off, the instruction is received to read or write data. would. As an example of this, the implementation of the refresh process is automatically performed in combination with the first read or write operation, which occurs after boot-up, independent of the usage history of the matrix before the boot event.

According to another preferred embodiment, including the default mode, the refresh / recovery operations are any time marks, as determined by an internal or external clock showing absolute time or accumulated system operating time. Initialized at Examples may be once every hour or once every day / week / month.

In one sub-category of these preferred embodiments, the refresh process is only applied to the addressed word line or word lie for read or write access.

In another sub-category of these preferred embodiments, the complete matrix, or a portion thereof, is refreshed by executing a refresh process including a write-back step, per wordline, in a stepped sequence. do. The data content on each wordline is temporarily stored elsewhere in the memory device.

In another sub-category of these preferred embodiments, the complete matrix or a part thereof is refreshed by performing a rewrite process including a re-write step, and including in parallel two or more word lines. Record them. The data content on each wordline is temporarily stored elsewhere in the memory device.

2) Prediction mode: preferred embodiment.

In this mode, it is assumed that imprints and disturbs develop in a predictable manner with respect to metrics that can be defined and determined numerically from the history of use of the matrix.

Preferred embodiments including the metric are based on:

Elapsed time after the reflash process including the write step has been performed on a given cell or group of cells in the matrix. Here, the elapsed time may be defined as including or not including a period in which the memory device is switched off.

The number of write disturb events that have been suffered by a given cell or group of cells since the cells or group of cells have been recorded or refreshed (re-written).

Combined input, such as accumulated disturb stress, determined by adding disturb events to a given cell or group of cells weighted by time, e.g., after the cells or group of cells were last written / refreshed Metrics based on data. An important class of metrics in the combined form is where environmental parameters, especially temperature, are used as input variables: empirically, the temporal development of the imprint can be significantly dependent on the temperature in the electret or ferroelectric, typically at high temperatures. Develop faster.

In the prediction mode, the refresh / recovery process is typically implemented less frequently than in the default mode, and requires less system resources.

3) Feedback mode: preferred embodiment.

This means confirming the actual state of the affairs within a given cell or group of cells by measuring the relevant cell response parameters-for example polarization switching response (speed and magnitude) for a standardized pulse protocol. The latter may include pulses of various amplitudes separated by time delays.

In one class of preferred embodiments, the measurement is performed on the cell or groups of cells that are the target of the write / read operation during the normal operation of the memory device. This is possible by inserting a diagnostic feature into the detection of the switched charge during the third phase of the refresh process associated with scheduled readout or re-flash if not otherwise. Since this adds time and complexity to the normal pulse protocol, it does not have to be performed at all times, but the memory device controller responds to the counting of access events as described, for example, under 2) prediction mode. And when so determined, may be implemented.

In a related preferred embodiment, the first three steps of the refresh process are combined such that when step 3 is executed in response to a read command, it includes diagnostic features such as switching speed measurement. In accordance with steps 1 and 2, which weaken the need for a refresh condition, the following steps in the refresh process will follow.

In another preferred embodiment, another cell or group of cells with similar operating history is used to serve as a reference. To ensure that the operation history is substantially similar, the selected reference cell or cells can be placed in the same wordline or group of wordlines, as these cells or cells are monitored for potential refresh. And the number of switching accesses will be reduced.

In another preferred embodiment, the control unit in the memory device records the operation history for the associated memory cells or group of memory cells, for example in the form of a sub-matrix as described above, and assigns for this purpose. A measurement is made for reference cells, in which the same operating history with the presence of "shadow" or "slave" was appropriately applied to a portion of the matrix.

The second stage of the refresh process will now be discussed: The refresh and re-write process takes time to perform and requires a lot of resources of the memory device. This implies that special care is needed to minimize conflicts with the normal operation of the memory device, e.g. regarding temporary access priorities for the matrix and auxiliary hardware. In addition, the performance for implementing coercive force measurement according to the present invention has consequences for physical complexity and the cost of memory devices. In addition, the decision modes described above will typically be part of a priority hierarchy suitable for the technical performance of the device and the expected usage profile. For this purpose, one or all of the following strategies can be described below:

Perform as few refresh / recovery operations as possible while meeting the minimum requirements for error rate in reads and stored data integrity. In this connection, the decision modes of 1), 2) and 3) can be configured to allow progressively less disturbance to the general operations of the memory device.

Create use of idle time when write / erase / read instructions containing the corresponding matrix or sub-matrix are not running.

Decisions related to the priority hierarchy diagram can be made to the controller unit, recording input instructions, ongoing operations in the matrix, instantaneous fatigue, disturb and imprint status of the matrix or its sub-units, possible relevant environmental parameters (temperature), and the like. Is generated by

One decisive factor in controlling the controller function is that no data will be lost. During any time in each refresh / recovery operation, there may be data in temporary storage in the device while waiting for re-write. In some circumstances, such data will be lost if the refresh / recovery operation is interrupted or terminated too early. Thus, although an incoming write / erase / read command can be defined as having a higher priority than a scheduled refresh / recovery operation, instances may be faced if the latter must be allowed to complete its process. have. On the other hand, if a prioritized memory access comes in, ongoing re-flash / recovery processes can be suppressed at the closest point in the cycle, which does not compromise data content, and is suspended until memory access is complete. May remain. This example would be, for example, a temporary interruption during the entire refresh of the completed matrix, where the matrix is constrained to a refresh process including a re-write step, for each wordline in the sequence of steps. In this case, the refresh / recovery process may be temporarily delayed between one wordline refresh / recovery and the following. If contingency occurs so much that prioritized memory access occurs before the refresh / recovery process can be completed, this contingency can be controlled by a properly programmed controller. Referring back to step 1, the refresh operation may be initialized at a time interval such that, for example, the refresh process is allowed to start at t _refresh seconds after the target cells are finally _refreshed . If the time (t _refresh) even when reaching the data is still controlled, so that it can be read and written with reliable way time (t _refresh) is selected, the other more acceptable activity of the higher priority so as to interfere with and access the memory In order to do so, it may be possible to abort the reset reinitialization process for another finite period of time. However, there will always be an arbitrary time limit if reading and writing may not be allowed for a long time until the refresh process is completed. At any time after this time limit, i.e. at t _force and before the refresh process is completed, the refresh process must be forced to the highest priority. By choosing an appropriate value with t _refresh <t _force for any memory application, the _refresh process is for most memory accesses in most cases when compared to situations involving a refresh process that always requires the highest priority. Can be transparent. Clearly, there is a trade-off between achieving smooth, fast and transparent access to the data content in the memory device on the one hand and avoiding complicated and heavy processing and memory functions in the controller on the other. In applications where there is no problem with the occurrence of delayed memory accesses, it is a simple solution to ensure that normal accesses do not have priority during the refresh / restore.

The third step of the reflash process will now be discussed: As shown in an example of one embodiment of FIG . 6 , a voltage pulse is applied to all cells on a selected word line (“active word line”, AWL in the figure). This voltage pulse has a predetermined polarity and sufficient intensity to switch the cells polarized opposite to the direction of the field generated thereby. This is accomplished by a signal source and an amplifier connected to the selected wordline as shown. At the same time, all other word lines (inactive word lines, IWL in the figure) and all bit lines (active bit lines, ABL in the figure) have zero or both voltages across all other cells relative to the voltage of the selected word line. It is held at a potential that guarantees to be almost zero. (The bitline potential is actively held at virtual ground by the sense amplifier circuit shown by reference in the figures.) In this method, it connects to unaddressed cells, AWL in the matrix. Disturbing voltage does not appear across cells that are not. If this third step is performed as part of the read operation, the switching current resulting from the application of the voltage pulses is simultaneously written by a sense amplifier connected to each bit line and the corresponding logic state of the switched cells on the selected word line. Are determined. This process is reminiscent of the prior art "full row read", where it is used to provide high parallel reads without disturb from passive matrix addressed memory arrays. However, in this case of particular interest in the possibility that the cells may be very imprinted prior to operation, the voltage pulse applied to the cells on the active wordline may be chosen to have a magnitude and / or duration that exceeds a significant margin. This limit is indicated by the switching voltage V _S shown in FIG . 4 and is necessary to achieve a change between residual polarization states (+ Pr and -Pr) in the non-imprinted cell. If this third step is performed only as part of a re -flash or pre-set operation, the switching current still needs to be written, and the data temporarily stored while waiting for re-write will cause the cells to leaf. If it is to be lashed or pre-set, it contains information that would otherwise be lost. If there is no need to store data, the bit line may be forced to the actual ground by a switch, instead of being maintained at a virtual ground, such as that illustrated in FIG. As will be readily appreciated by one skilled in the art, the correct selection of potentials as shown in FIG. 6 is for illustrative purposes only. The same read schemes can be devised, where the potentials are evenly shifted or exchanged compared to those shown in FIG . 6 , for example placing the word line potentials at ground and all other lines to the switching voltage. It is arranged at a potential different from the ground by a corresponding voltage.

To terminate, this third step unlocks the imprinted cells as opposed to the direction of the pulse applied in this step and polarizes them in one direction. This can be done in response to a read command, or if you want to polarize all addressed cells in the same direction, or as an initialization step to release very imprinted cells. In conjunction with subsequent steps, this step adjusts the cells to electrically represent a low imprint within any time-span after these operations.

The fourth step in the refresh process will now be discussed: a series of pulses is applied to the selected wordline according to a predefined protocol, where it reduces or eliminates imprints in the cells and facilitates subsequent write / read operations. In order to do this, the number, intensity, duration and polarity of the individual pulses of the pulse train are selected. At the same time, the potential on all other word lines and all bit lines is controlled such that the voltage across all other cells is near zero or at least the switching threshold, similar to the case described under the third step above, than the voltage on the selected word line. It is less than (threshold).

Imprint phenomena are complex and varied, but there is a significant amount of empirical knowledge regarding the effects of electric fields on imprinted electrets or ferroelectrics. Of particular relevance in this regard are voltage pulse sequences that can be applied to reduce or eliminate imprints in memory cells such as those shown in FIGS . 1 and 2 . Before proceeding, may also be useful to refer to 5e, Figure 5e is a state (situation) of the single cell at any instant the future after the switch to the new sangchae of opposite polarized in the imprinting status of a given polarization Shows: At any time, depending on how quickly the imprint develops, the cell will later be imprint-free in appearance in response to an applied electrical pulse.

When the imprint is removed from many cells at the same time, it should be taken into account that the cells may be imprinted in different directions when the entire row of cells on the wordline is adjusted at the same time, and a single unipolar pulse would be inappropriate. Empirically, it is understood that a sequence of bipolar pulses can be effective for removing imprints regardless of the initial imprint direction. An example of such a bipolar pulse sequence is shown conceptually in FIG . 7 . Here, only the voltage appearing across the cells on the addressed wordline is shown: following the bipolar pulse in step 3, followed by the train of bipolar pulses in step 4 ("refresh"), which is typically followed by subsequent writing. It ends with the last pulse with a predetermined polarity that sets the stage for the step. The number of pulses in step 4 can be from one to several thousand, and typically needs to be hundreds. In situations where a high switching voltage is not required or not obtainable, the same switching effect can be obtained by pulses of smaller magnitude but with a longer duration. In general, although this situation does not always need to be maintained, each of the pulses in step 4 will have a magnitude and duration sufficient to switch the polarization back and forth between + Pr and -Pr:

More complex pulse sequences may also be involved, including sequences in which strong switching pulses are combined with weak pulses. Some further examples of pulse sequences are shown in FIG. 8 . In FIG. 8A , step 4 is of opposite polarity to that in step 3, and of sufficient size to ensure that the cells imprinted in the direction of step 3 are released and switched (which may remain undisturbed by the pulse in step 3). It consists of a single pulse with and duration. Thus, the bipolar pulse formed in steps 3 and 4 will release the imprinted cells in either direction. Timing is important, but if the pulse in step 4 follows very soon after the pulse in step 3 and the cell has been switched in imprint by the pulse in step 3, then the pulse of intrinsic step 3 in the gradual movement of the hysteresis curve The de-imprinting effect of has not yet had time to develop, and the pulse of step 2 will switch the cell back to the imprint state. Thus, any wait time τ _wait will typically be defined between two pulses, where τ _wait should be long enough to allow any measurement of polarization stabilization in the cell, but It should not be long enough to slow down the movement. FIG. 8B shows a variant of the sequence in FIG. 8A , where a train of positive switching pulses is now added. In this example, the last pulse has a predetermined polarity corresponding to that used for the pre-set cell. The train of bipolar pulses should be selected according to the materials involved and the operating conditions. This also applies to interpulse spacing (τ _off ) and pulse width (τ _on ).

7 and 8 show only the voltages across the addressed cells except the voltage across the unaddressed cells. The latter will depend on the choice of pulse protocol for the entire matrix. 9A and 9B show examples of voltages applied to word lines and bit lines according to two different protocols: Unaddressed cells in FIG. 9A are exposed to a V _S / 3 disturb pulse. In FIG. 9B , even if a strong pulse is applied to the addressed cells, the unaddressed cells are not exposed to the disturb pulse. Which scheme is chosen in each given case depends on the disturbance characteristics of the cells and the performance and cost specifications for the device.

Now we want to start an optional recording step . This is provided for writing data into cells that have been regulated through the reflash process, or for pre-setting the cells to a specific polarization state during later operation. In FIG. 7A , the sequence includes a final write step that puts the cell in logic state 0 (eg, corresponding to the + P _r polarization state), while in FIG. 7B , logic 1 (eg, The corresponding pulse sequence for recording -P _r polarization state) is shown. In the latter case, the negative-polar write pulse in the write step is indicated by the dotted line, since the last pulse in step 4 as shown here is negative and will polarize the cell to the desired logic state (1), The cell will be maintained during the recording phase. It should be noted that write will always induce disturb voltages in the unaddressed cells, and thus will benefit from the write characteristics of uniform, imprint-free addressed cells. Thus, the standard V _S / 3 write protocol can be used without the need for overvoltage or extra wide write pulses, which can otherwise cause excessive disturbance in unaddressed cells. Pre-setting or blanking of the cells can in principle be performed in a disturb-free manner by directly polarizing one or more entire word lines simultaneously. Still, in some cases it may be desirable to preset some, but not all, of the cells of a given wordline. In such a case, operating the entire three-step process according to the present invention may be a preferred default process, which guarantees that any imprint of the pre-set cells will be limited to developing only after the pre-setting operation and discontinuity. Because it minimizes. This imprint will be uniform in size and direction between the preset cells.

In accordance with the present invention, the recording will occur after the reflash process is over and before any significant imprint is re-created in the cell itself. In general, this is done immediately, for example as part of a single pulse sequence as shown in FIG . 7 . In other cases, the imprint development may be slow enough so that other operations, idle periods or shut-down periods in the memory device may occur before the next write or adjusted cell pre-setting.

Within the scope of the present invention, the disclosed relash process may be described and extended in detail to achieve some specific purposes. Specific examples will be given below as part of any preferred embodiments.

The description will now be given by any preferred embodiments .

In a preferred embodiment, especially in boot situations, data stored in cells that may be strongly imprinted is read, and then the same cells are refreshed:

In this case, steps 1) to 4) are carried out. Since a strong read pulse can be used in the third step without causing any disturb elsewhere in the matrix, reliable read is achieved regardless of the initial imprint state of the individual cells on the selected wordline. In addition, the fourth step ensures that the residual pre-read imprint or new imprint generated by the powerful read pulse in the third step is removed from all cells on the addressed wordline.

 In a second preferred embodiment, one has just been written, either spontaneously by excessive imprint or generated by disturbs from cells elsewhere in the same matrix to which a switching pulse has been applied, for example associated with writing or relashing. Avoid flip-back of polarization in the imprinted cell.

In this case, all steps including the recording step are performed. Since the cells are to be written so that they are provided uniformly and essentially free of imprint during the refresh phase prior to the write phase, the newly written cells are no longer strongly biased by the imprint which may cause flip-back. Unaddressed cells in the matrix will generally be subjected to a minimum disturb stress suitable for the selected write protocol (eg V _S / 3).

In the first class of preferred embodiments, one avoids possible loss and gradual polarization decline of data in the cells, for example due to disturbs from cells elsewhere in the same matrix to which switching pulses related to the write or rewrite operation are applied. Avoid: Referring to a given single cell representing a wordline or a block of wordlines, the criterion for selection under the first refresh step is that the number of disturb events that the cell has experienced since the last time it was written or refreshed should be any number. It is exceeding. After the refresh, a re-write step is included and performed:

The data can be written back to their original physical location in the matrix. In any case, it may be desirable to use encoding into logics 1 and 0 that are assigned with the opposite polarity as was recorded at the location before the re-flash. While this will involve a certain amount of internal bookkeeping in the memory device, this may allow steps 3 and 4 to be modified or simplified for speed advantage.

Optionally, the re-write occurs at other physical locations in the emptied and refreshed matrix. In this case, the memory device controller must record the elapsed time since the last refresh in the relevant position.

In the second class of preferred embodiments, as shown in FIG. 10, the partitioned memory (N segments) is constructed in such a way that there are n word lines per segment that do not contain data at any suitable moment. do. At regular time intervals t _refresh (determined by the disturb characteristics and the imprint speed of a particular memory film), the refresh operation is initiated in these word lines. The de-imprint operation is typically a full word with a voltage high enough for the cell to switch fully to the available pulse duration, τ ₁ (eg 10us) duration, τ ₂ (eg 10 us) pause time. Contains N _{pulses, 1} (eg 500) bipolar _pulses applied to the line. All UAWL-UABL pairs are kept at zero voltage to avoid disturb using a special timing diagram. Immediately after the refresh process, data is read from the first wordline of segment 1 and written to the first wordline of the recently refreshed n wordlines of segment 2. Immediately following this operation, data from the first wordline of segment 3 is written to the first wordline of the n most recently refreshed wordlines of segment 4. This process continues until data from all n word lines is transferred to n refreshed word lines in another segment. Once this is done, the most recently read n wordlines of all segments are refreshed in the manner described above. New data of n new word lines of N segments is transferred to a recently refreshed word line or the like until all word lines of all segments are refreshed.

The same method can be used to refresh memory that has been idle (powered down) for longer than t _refresh . In this case, however, more cycles will be applied. It may also be necessary to extend the pulse length and / or increase the voltage to still include a complete switch.

One major advantage of this implementation is that even if very many switches are needed to eliminate the imprint, the total time spent in the relash can be kept small.

Another major advantage is that this method can handle unexpected power failures without data loss, which may be the case when large amounts of data are stored in buffer memory.

As shown in Figure 11, in a third preferred embodiment, where most of the memory is suitable for memory applications that have not been accessed for a long time, information regarding the access status of all word lines is stored in a register. At regular time intervals (t _refresh ), all word lines or groups of word lines are targeted and initialized using an addressing scheme following the concept of word line mapping. Disclosed in Norwegian patent application No. NO20035225. Two different relash methods are applied. When t _refresh is reached, the interval t _refresh will be selected so that the imprint can only be deployed with any known limit for cells not accessed during the interval t _refresh , ie t _refresh is specified memory It should be chosen according to the distort characteristics of the film and the imprint speed. One method, now referred to as hard refresh, involves reading the entire wordline and storing information in another recently refreshed segment or buffer memory, where the cell is fully switched within the available pulse duration. Followed by N _pulses applied to the entire wordline with a sufficiently high voltage, τ ₃ (e.g. 10us) duration, τ ₄ (e.g. 10us) dwell time, _{and 2} (e.g. 500) bipolar pulses. . All UAWL-UABL pairs are kept at zero voltage to avoid disturb. If the data originally stored on these word lines is stored in the buffer, the same data is written again. Another method of referring to imprint reversal involves a readout followed by a write back in the opposite direction of the previous direction (inversion of the data bits).

For wordlines that were not accessed during the last t _refresh interval, imprint inversion is applied. For wordlines that were accessed during the last t _refresh interval, hard refresh is applied.

One major advantage of this embodiment is that the total time spent in refreshing can be kept low, even if very many switches are needed for hard refresh.

In a fourth preferred embodiment, the content requested in memory that has been idle (eg booting up) for longer than t _refresh is sufficient to perform the entire switch of cells (95% of the achieved polarization). The long pulse duration is used to read every word line (keeping all unaddressed word lines close to zero voltage or zero voltage for the bit lines). The data is then written back in the opposite direction (the inverse of the data bits) in the previous direction. After all requested data has been read and written back to memory, hard refresh is performed to the entire memory. And hard leaf lash comprises a data storage device in the leaf lash the other segment or buffer memory to read out and the latest full word line, and a sufficiently high voltage to the cell to fully switch in the available pulse duration, τ ₃ (e. For example, 10us) is followed by N _{pulses, 2} (e.g. 500) bipolar _pulses applied to the entire wordline with a duration of τ ₄ (e.g. 10us). All UAWL-UABL pairs are kept at zero voltage to avoid disturb. If the data originally stored on these word lines is stored in the buffer, the same data is written again.

The advantage of using this method is that the memory read can occur at a much higher rate than if it had to be a combined read / refresh for every wordline or block of wordlines. Another advantage is that memory cells that are read and re-written are de-imprinted themselves for a period of time from the end of the read through the polarization reversal until the hard refresh begins.

In the fifth embodiment, as shown in FIG. 12, the fourth step includes a plurality of anode switching pulses to achieve an effective retrace. In any case involving very imprinted cells, it is known that hundreds to thousands of pulses are required, which consume a lot of time. During this polarization cycle, it is generally very difficult to achieve polarization switching at the beginning of the pulse sequence of step 4 because the imprint effect gradually decreases as the number of switches performed is larger. Thus, as conceptually shown in FIG. 12, the preferred embodiment can switch even very imprinted cells, and at least one wide pulse while stepping or gradually decreasing the width of the pulse while still switching cells. Provide to begin the pulse sequence of step 4, including. Due to the many pulses involved, this will reduce the total time spent in step 4.

Claims (26)

A method of operating a passive-matrix addressable ferroelectric or electret memory device, the memory device comprising memory cells in the form of a ferroelectric or electret thin film polarizable material exhibiting hysteresis, in particular a ferroelectric or electret polymer thin film. One or more arrays or matrices, and first and second sets of parallel electrodes, respectively, wherein the electrodes of the first set forming wordlines WL in the device are bits in the device. Provided in a substantially orthogonal relationship with the second set of electrodes forming lines BL, wherein the first and second sets of electrodes are directly or indirectly with the thin film material of the memory cells. And a polarization state of the individual memory cells is thus provided in each of said first and Can be read, erased or written by applying appropriate voltages to the second set of individual electrodes, the method implementing a voltage pulse protocol based on a 1/3 voltage selection rule, so that unaddressed cells are Disturbing voltages are applied at both ends not exceeding approximately one third of the switching voltage V _S , and the voltage pulse protocol respectively applies time sequences of voltage pulses having a predetermined amplitude, polarity and length. Including a read cycle and a write / erase cycle, wherein the read cycle applies a set of voltage differences to the first and second sets of electrodes of each of the electrodes when data is read from the memory cells. Wherein the write / erase cycle is different from the voltage differences to the first and second sets of electrodes of each of the electrodes. Comprising the step of applying an agent, The method, a) selecting one or more cells for a refresh according to a criterion programmed in a memory device controller and inputting the addresses of the one or more cells selected as described above in the refresh request processed by the controller; b) monitoring and processing the refresh request and initiating a refresh process in view of ongoing or scheduled memory operations and priorities assigned thereto; c) all non-selected memory cells are subject to zero voltage or significantly less than the coercive voltage, while the one or more cells selected for relash correspond to a defined polarity and the coercive voltage; A third step of simultaneously applying a voltage pulse having a magnitude greater than this, and d) zero voltage is applied to all unselected cells or significantly less than the coercive voltage, whereas all selected cells are trained with one voltage pulse or voltage pulses-at least one of the voltage pulses. And wherein said relash process comprises a fourth step, simultaneously applying a coercive voltage having a magnitude greater than or equal to said coercive voltage and having an opposite polarity to said predetermined polarity of step c). A method of operating a matrix addressable ferroelectric or electret memory device. The method of claim 1, And performing a write operation defined by the write cycle of the voltage pulse protocol on the one or more cells selected for re-flash. 19. A method of operating a passive-matrix addressable ferroelectric or electret memory device. The method of claim 1, At least one cell is selected in step a), wherein the selected cells correspond to the entire row of the memory device. The method of claim 1, At least one cell is selected in step a), wherein the selected cells correspond to a block of cells in at least two rows of the memory device. The method of claim 1, Step d) comprises using pulses with the same or different time profile, comprising at least two pulses, wherein the amplitude, pulse length and interpulse delay are selected according to a predefined protocol. Operating a passive-matrix addressable ferroelectric or electret memory device. The method according to any one of claims 1 to 5, By applying a predetermined potential to one selected wordline WL and simultaneously applying different but essentially identical potentials to all other wordlines and all bitlines belonging to the same passive matrix or segment thereof, Generating the voltage pulses of step c) of claim 1, the method of operating a passive-matrix addressable ferroelectric or electret memory device. The method of claim 1, A series of time-dependent potential levels are applied to all wordlines and bitlines belonging to the same passive matrix or segment thereof, in such a way that the potentials on all lines except one selected wordline or set of selected wordlines are essentially the same. Generating said voltage pulses of step d) of claim 1. The method according to claim 1 or 2, Extracting stored data from selected cells on at least one wordline in step c), temporarily storing the extracted data elsewhere in the memory device, and then storing the extracted data in the at least one wordline during the next additional writing step. And rewriting the same data. 19. A method of operating a passive-matrix addressable ferroelectric or electret memory device. The method of claim 8, Operating each passive-matrix addressable ferroelectric or electret memory device, characterized in that each bit is written back to the same physical location where they were located prior to the first read or erase step, but in the reversed polarization direction . Way. The method of claim 1, Step a) selects to re-flash all cells of the memory device subjected to a first read or write operation after boot-up, wherein the passive-matrix addressable ferroelectric or electret memory device is selected. How it works. The method of claim 1, Step a) is selected to re-flash all cells of the memory device that have been idle for a period of time exceeding a predetermined time period. 20. A method of operating a passive-matrix addressable ferroelectric or electret memory device. The method of claim 10 or 11, And wherein said selected cells constitute a block or segment of a matrix comprising at least two word lines. The method of claim 1, Passive-matrix addressable, characterized by defining the pulse amplitude and timing of steps c) and d) by an algorithm involving input parameters calculated from at least one environmental and / or usage history metric. A method of operating a ferroelectric or electret memory device. The method of claim 13, Selecting the environmental metric as an instantaneous temperature or temperature history at one or more points in the vicinity, above or in the memory device, the method of operating a passive-matrix addressable ferroelectric or electret memory device. The method of claim 13, A passive-matrix addressable ferroelectric or electret, characterized in that the usage history metric is selected as the number of write and / or read events experienced by a single wordline or matrix segment since the last application of the refresh pulse protocol. How to operate a memory device. The method of claim 1, Passive-matrix addressable ferroelectric or electret memory device, characterized in that all cells on a wordline at least one cell exhibiting polarization switching performance corresponding to at least one predetermined criterion are selected for relash in step a). How to operate. The method of claim 1, Passive-selecting, in step a), all cells belonging to a block or segment in a matrix in which at least one cell on one wordline exhibits polarization switching performance corresponding to one or more predetermined criteria. A method of operating a matrix addressable ferroelectric or electret memory device. The method according to claim 16 or 17, And within said criterion, reducing the polarization switching speed to a predetermined threshold or less. 10. A method of operating a passive-matrix addressable ferroelectric or electret memory device. The method according to claim 16 or 17, And within said criterion, reducing the polarization switching charge to a predetermined threshold or less. 16. A method of operating a passive-matrix addressable ferroelectric or electret memory device. The method according to claim 16 or 17, And the selected memory cells in the memory device are memory cells addressed during a normal read, erase or write operation of the memory device. The method according to claim 16 or 17, And said selected memory cells in said memory device are memory cells specifically allocated for reference or control purposes. The method of claim 1, The passive-matrix addressable ferroelectric or elective, characterized in that the priority assigned in step b) is based on a predetermined layer of priorities, including electronic access to wordlines and bitlines in each matrix segment. How to operate a let memory device. The method of claim 1, Starting on a given wordline or set of wordlines, completing steps c) and d), and only if the read data has been stored or transferred elsewhere in the memory device in accordance with the read command; And read data into the passive-matrix addressable ferroelectric or electret memory device. The method of claim 1, And executing the refresh process by default during the idle period in the memory device or sub-unit thereof. The method of claim 1, Operating a passive-matrix addressable ferroelectric or electret memory device, characterized in that to implement the refresh process in accordance with a predetermined program, to include predetermined matrices or matrix blocks or segments in the memory device. Way. The method of claim 1, A passive-matrix addressable ferroelectric or electret memory, characterized in that during the fourth stage, a bipolar pulse train is selected, the width of the pulse being gradually or stepwise reduced as pulsing proceeds. How to operate the device.

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