KR20070091846A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to eliminate the necessity for an additional OPC(optical proximity correction) process by performing an exposure process on cells positioned at the edge of a cell block region without influencing the periphery of the cells. A plurality of cell block regions(200) in which unit cells with a uniform pattern are formed is formed in a semiconductor device. The cell block regions are separated from each other by a cell block peripheral region(210). A mask layout(600) in which the pattern shape of cells formed in each cell block region appears is extended to the cell block region and the cell block peripheral region adjacent to the cell block region to perform an exposure process. A mask layer(610) can be installed under the mask layout extended to the cell block peripheral region so that the cell block peripheral region isn't substantially exposed.

Description

Method for manufacturing a semiconductor device {Method for fabricating semiconductor device}

1A to 1D show plan views of such layers, where FIG. 1A is an arrangement of landing plug contacts, FIG. 1B is a bit line contact, FIG. 1C is a storage node contact, and FIG. 1D is a storage node. It shows the arrangement of.

2 is a diagram schematically illustrating that a plurality of cell block regions are formed spaced apart from a cell block peripheral region.

3 is an enlarged view illustrating region B of FIG. 2 enlarged.

4A and 4B illustrate simulation results of performing an exposure process using a photomask having the same layout as the cell block region in the boundary region of the cell block region and the cell block peripheral region.

5 is a plan view showing a form in which a photomask layout is arranged in a cell block area in order to solve the technical problem of the present invention.

6 is a cross-sectional view taken along the line C-D of FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, in performing an exposure process for forming a predetermined pattern in a block cell region such as a landing plug contact, an exposure condition near a boundary of each block cell region is determined. The present invention relates to a method of manufacturing a semiconductor device capable of overcoming a poor exposure phenomenon that occurs at the boundary of a block cell region, which is not the same as the inside of a block cell.

In the manufacturing process of a DRAM semiconductor device, peripheral circuits exist in layers such as landing plug contacts, bit line contacts, storage node contacts, and storage nodes. Instead, only the unit cells are repeated regularly.

1A to 1D show plan views of such layers, where FIG. 1A is an arrangement of landing plug contacts, FIG. 1B is a bit line contact, FIG. 1C is a storage node contact, and FIG. 1D is a storage node. It shows the arrangement of.

1A to 1D, there are a plurality of cell block areas in which these cells are collected, and each cell block area is spaced apart from each other by the cell block peripheral area.

FIG. 2 is a diagram schematically illustrating that a plurality of cell block regions are formed spaced apart from a cell block peripheral region, and FIG. 3 is an enlarged view of region B of FIG. 2.

Referring to FIG. 2, it can be seen that there exists a cell block region 200 that forms a boundary between the cell block region 200 and the cell block region in which cells exist in a block form.

By the way, in FIG. 2, a predetermined pattern is repeatedly formed in the inner region A of the cell block region 200, so that the peripheral cells are not affected much in forming each cell. Since the cells are repeatedly arranged in the vicinity of the boundary area B where the cell block area 200 and the cell block peripheral area 210 meet, the cells are not present in the cell block peripheral area 210, and thus, the cell block area 200 The cells adjacent to the cell block peripheral area 210 among the existing cells have different results from those inside the cell block area 200 due to the surrounding environment even if the mask pattern gives the same layout as the cell inside. Can be imported.

4A and 4B illustrate simulation results of performing an exposure process using a photomask having the same layout as the cell block region in the boundary region of the cell block region and the cell block peripheral region.

However, simulation conditions of FIGS. 4A and 4B were performed using an ArF 0.93NA crosspole 30 illuminator using a 66nm half pitch layout structure and a 6% attenuated PSM (Phase Shift Mask). .

In this simulation, the photomask (FIG. 4A) in which the cell block region 200 and the cell block peripheral region 210 are clearly separated is subjected to the exposure under the above simulation conditions. As shown in FIG. 2, the exposure of the cell block region 200 to a light transmissive region of the photomask is performed at an appropriate size. However, in the cell block region 200, the exposure of the cell block region 200 is near the boundary of the cell block region 200. It can be seen that the exposure has not been done at all, or even if it has been done, it is deviating greatly from the intended size.

In order to solve the above problems, OPC (Optical Proximity Correction) or a method using a multi-step mask process is used, but these methods are not only an element that complicates the process, but also The higher the difficulty, the more limited the application.

The technical problem to be achieved by the present invention is to perform the exposure process using a photomask on the cells near the boundary region of the cell block region and the cell block peripheral region, the cells near the boundary region are the same reliability as the cells of the cell block region. It is to provide a method of manufacturing a semiconductor device that can be exposed to the light.

Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention for solving the above technical problem, a plurality of cell block regions in which unit cells having a predetermined pattern exist are present, and the cell block regions are formed by surrounding cell blocks with each other. In performing the exposure process on the semiconductor elements spaced apart from each other, a photomask in which the pattern shape of the cells formed in each cell block region is shown is installed to extend to the cell block region and the cell block peripheral region adjacent to the cell block region. It is characterized by performing an exposure process.

According to an embodiment of the present invention for solving the above other technical problem includes.

Specific details of other embodiments are included in the detailed description and the accompanying drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

FIG. 5 is a plan view illustrating a photomask layout arranged in a cell block region in order to solve the technical problem of the present invention, and FIG. 6 is a cross-sectional view of the cut surface taken along the line C-D of FIG. 5.

Referring to FIG. 5, it can be seen that the mask layout used in the present invention extends not only the cell block region 200 but also the cell block peripheral region 210 spaced apart from the cell block regions 200.

However, the masquel layout does not extend to the entire cell block peripheral area 210, but only to the vicinity of the boundary of the cell block area 200.

The reason for extending the mask layout to the cell block peripheral area 210 is that the cells in the boundary area of the cell block area 200 to the cell block area 210 to be exposed are also inside the cell block area 200. This is to impose the same exposure conditions as the cells of.

Therefore, the mask layout extending to the cell block peripheral region 210 should have the same mask layout not only in the cell block region 200 but also in the cell block peripheral region 210.

FIG. 6 is a cross-sectional view of the cut surface of the CD region of FIG. 5. Referring to FIG. 6, the mask layout 600 may include not only the cell block region 200 but also the cell block region 200 of the cell block peripheral region 210. The cell block region 200 extends to an adjacent region, but the portion to be exposed is the cell block region 200, and thus, the cell block peripheral region 210 is disposed under the mask layout 600 extending to the cell block peripheral region 210. A light shielding film 610 is provided to block light from entering during exposure.

Where the light shielding film 610 is installed, the mask layout 600 should be installed in all areas extending beyond the cell block area 200 to the cell block peripheral area 210 and the material for forming the light shielding film 610. The furnace is preferably made of the same chrome pattern as the mask 600.

In addition, the light shielding film 610 is preferably installed at a distance of about 100 μm from the surface of the mask layout 600, specifically, a distance of about 70 μm to 150 μm, and may effectively block I-line, KrF, and ArF lasers. It should consist of materials that can be used. In addition, the light blocking film 610 does not affect the diffraction information of the surroundings by causing reflection and scattering when light entering the mask layout 600 reaches the light blocking film 610.

It is preferable to manufacture the light shielding film 610 through a separate manufacturing process, and attach the light shielding film 610 so as to be exactly aligned with the original mask layout position.

However, at this time, the range of the mask layout 600 extending to the cell block peripheral area 210 should be a range that can sufficiently alleviate the proximity effect, and is six or more based on one unit cell. It should be possible.

As such, the mask layout 600 extends not only to the cell block region 200 but also to the cell block peripheral region 210 adjacent to the cell block region 200, thereby extending the mask layout 600 to the boundary edge of the cell block region 200. Exposure to the located cells can be normally performed, thereby obtaining the same exposure result as the center of the cell block region 200.

While the embodiments of the present invention have been described with reference to the accompanying drawings and tables, the present invention is not limited to the above embodiments, but may be manufactured in various forms, and the general knowledge in the art to which the present invention pertains. Those skilled in the art will appreciate that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor device manufacturing method according to an embodiment of the present invention there is one or more of the following effects.

First, the cells located at the edge of the cell block region may be exposed without being affected by the surroundings thereof, and thus do not require a separate OPC operation.

Second, the mask revision process can be minimized, resulting in a reduction in product development speed and cost.

Claims (4)

In performing an exposure process on a semiconductor device in which a plurality of cell block regions including unit cells having a predetermined pattern exist and the cell block regions are spaced apart from each other by a cell block peripheral region, And a mask layout in which the pattern of the cells formed in each of the cell block regions is formed so as to extend to the cell block region and the cell block peripheral region adjacent to the cell block region. Method of preparation. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that a light shielding film is provided below the mask layout extending to the cell block peripheral area so that exposure is not substantially performed in the cell block peripheral area. The method of claim 1, And the mask layout extends only to a region adjacent to the cell block region among the cell block peripheral regions. The method of claim 2, The light shielding film is a method of manufacturing a semiconductor device, characterized in that provided with a distance of 70 ~ 150㎛ the mask layout.

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