KR20070086719A - Semiconductor device and operation control method for same - Google Patents

Abstract

A semiconductor device includes an inversion gate for electrically connecting an inversion layer to a global bit line by forming the inversion layer, which is to be a local bit line, on a semiconductor substrate, and a memory cell which uses the inversion layer as a source and drain. Thus, since the inversion gate can be operated as a sector transistor, there is no need for providing an extra sector transistor. Since an area for the sector transistor can be reduced, increase of a circuit area can be suppressed. Further, at the time of erasing, electrons injected to the memory cell may be extracted to the semiconductor substrate side by using FN tunnel effects. At the time of erasing, the electrons injected to the memory cell may be extracted to a word line side by using the FN tunnel effects. At the time of erasing, the electrons injected to the memory cell may be extracted from the inversion gate by using the FN tunnel effects.

Description

Semiconductor device and its operation control method {SEMICONDUCTOR DEVICE AND OPERATION CONTROL METHOD FOR SAME}

The present invention relates to a semiconductor device and an operation control method thereof.

In a memory having a function of storing information, there is a nonvolatile memory that continues to be stored even when the power is turned off. A nonvolatile memory that can be rewritten is a flash memory. In such a flash memory, a floating gate is provided, and writing and erasing can be performed by injection and drawing out of electrons to and from the floating gate. The following are proposed as a prior art regarding a flash memory.

Non-Patent Document 1 relates to an AG-AND type flash memory without a diffusion layer using a floating gate. Figure 1 is a plan view of a memory array of AG-AND flash memory of 90-nm-node. Fig. 2 (a) is a cross sectional view showing a voltage condition at the time of programming, and (b) is a cross sectional view showing a voltage condition at the time of reading. 3 is a diagram illustrating an array configuration of AG-AND.

Assist gates AG ₀ to AG ₃ are disposed on the silicon substrate. This assist gate (AG ₀ To AG ₃ ) an inversion layer (channel) is formed on the substrate underneath. Thus, no diffusion layer is present. The word line WL extends in a direction perpendicular to the assist gate AG. In the program operation, as shown in FIG. 2A, voltages of 0, 5, 1, and 8V are supplied to the assist gates AG ₀ , AG ₁ , AG _2, and AG ₃ , respectively. A voltage of 18V is supplied to the word line WL of the selected cell.

A channel serving as a source is formed under the assist gate AG to which 5V is applied. A drain channel is formed under the assist gate AG to which 8V is applied. The channel under the assist gate AG to which 1V is applied is weakened, so that the electric field at the boundary with the floating gate FG becomes strong and at the same time the current is suppressed. 0V is applied to the assist gate on the left side of the assist gate AG to which 5V is applied to cut off the channel so that no current flows.

The flow of electrons from the source is sequentially through the channel under the assist gate AG ₁ , the floating gate FG of the cell, the assist gate AG ₂ , the floating gate FG of the selected cell, and the assist gate AG ₃ . Since the electric field at the boundary of the floating gate under the assist gate AG to which 1V is applied is strong, hot electrons are injected into the floating gate of the selected cell.

In the read operation, as shown in Fig. 2B, by applying a voltage of 5 V to the assist gates AG on both sides of the floating gate, a channel is formed under the assist gate AG, one of which is the source and the other. By using one side as a drain, reading of the floating gate FG is performed.

Patent document 1 relates to an AG-AND type flash memory using a SONOS type memory cell. Two assist gates are provided between two diffusion regions serving as a source or a drain, and a SONOS type memory cell is formed between the assist gates. By changing the source and the drain, it has been shown that electrons are trapped in the nitride film region of two portions near the assist gate of the memory cell, and two-bit storage can be simultaneously performed.

Non Patent Literature 1: Y. Sasago et al., 90-nm-node multi-level AG-AND type flash memory with cell size of true 2F2 / bit and programming throughput of 10 MB / s, Dec. 2003, Technical Digest, pp. 823-826.

Patent Document 1: Japanese Patent Application Publication No. 2001-156275

However, in the conventional AG-AND type flash memory, a sector transistor connected to a selection gate line in order to connect a local bit and a global bit (DL _{m -3} to DL _{m +2} ). Since (SecTor Transistor, ST Tr) is required, there is a problem that the circuit area is increased. In addition, in the technique of Patent Document 1, since the source and the drain are formed in the diffusion layer, there is a problem that the memory array region is increased.

Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device and an operation control method thereof capable of suppressing an increase in circuit area.

In order to solve the above problems, the present invention forms a semiconductor substrate, a word line, a global bit line, and an inversion layer that becomes a local bit line on the semiconductor substrate to electrically connect the inversion layer to the global bit line. A semiconductor device including an inversion gate and a memory cell using the inversion layer as a source and a drain. According to the present invention, since the inversion gate can function as a sector transistor, there is no need to provide a sector transistor. For this reason, the area | region for a sector transistor can be reduced. Therefore, increase in circuit area can be suppressed. In this way, an array structure including a decoding circuit for making the array size as small as possible can be provided.

Preferably, the inversion layer is connected to the global bit line through a metal wiring. The memory cell is formed between adjacent inversion gates. The present invention further includes a selection circuit for selecting a memory cell for supplying a predetermined voltage to the inversion gate to write or erase. The inversion gate may include a first inversion gate forming an inversion layer serving as a source, a second inversion gate forming an inversion layer serving as a drain, and a third provided between the first inversion gate and the second inversion gate. And an inversion gate, and further comprising a selection circuit for selecting a memory cell to write by supplying a predetermined voltage to the first to third inversion gates at the time of writing.

Preferably, the selection circuit supplies a voltage to the third inversion gate to form a smaller channel region under the third inversion gate among the channel regions formed between the source and the drain in the semiconductor substrate. . Technically, by slightly turning on the transistor of the inversion gate, the channel region under the third inversion gate can be made small among the channel regions formed between the source and the drain in the semiconductor substrate.

The inversion gate further includes a fourth inversion gate disposed at a position opposite to the third inversion gate when viewed from the first inversion gate, wherein the selection circuit is formed in the semiconductor substrate in the fourth inversion gate upon writing. It is desirable to supply a voltage for cutting the channel to be cut. Technically, the channel formed in the semiconductor substrate in the fourth inversion gate can be cut by turning off the transistor of the inversion gate. The present invention further includes a write voltage supply circuit for supplying a write voltage to the inversion layer when writing. The present invention further includes a voltage supply circuit for supplying the word line with a voltage for drawing electrons injected into the memory cell to the semiconductor substrate side using an FN tunnel effect during erasing. At this time, the voltage for drawing out to the semiconductor substrate side is preferably a negative voltage.

The present invention further includes a voltage supply circuit for supplying the word line with a voltage for drawing electrons injected into the memory cell to the word line side using the FN tunnel effect during erasing. The present invention further includes a voltage supply circuit for supplying a voltage for drawing electrons injected into the memory cell to the inverted gate during erasing using the FN tunnel effect. The present invention has a plurality of column sets (i) consisting of a plurality of global bit lines, and a page buffer corresponding to a predetermined global bit line in the column set by a common selection signal C, respectively. and a decoder connected to the page buffer 60-i.

The inversion layer is shared by a plurality of memory cells. The memory cell stores two bits per cell by storing one bit at each end of the insulating film between the inversion gates. The memory cell is preferably of the SONOS type. It is preferable that the semiconductor device is a semiconductor memory device.

The present invention provides a first step of electrically connecting the inversion layer to a global bit line by supplying a predetermined voltage to an inversion gate to form an inversion layer that becomes a local bit line on a semiconductor substrate, and a second step of selecting a word line. It includes a method. According to the present invention, since the inverting gate can be operated like a sector transistor, there is no need to provide a sector transistor. For this reason, the area | region for a sector transistor can be reduced. Therefore, increase in circuit area can be suppressed. In this way, an array structure including a decode circuit for making the array size as small as possible can be provided.

The inversion gate includes a first inversion gate forming an inversion layer serving as a source, a second inversion gate forming an inversion layer serving as a drain, and a third inversion gate disposed between the first inversion gate and the second inversion gate. Wherein the first step supplies a predetermined voltage to the first to third inverted gates upon writing. The first step includes supplying a voltage to the third inverted gate to form a smaller channel region under the third inverted gate among channel regions formed between the source and the drain in the semiconductor substrate.

The inversion gate further includes a fourth inversion gate disposed at a position opposite to the third inversion gate when viewed from the first inversion gate, wherein the first step cuts a channel formed in the semiconductor substrate upon writing. And supplying a voltage to the fourth inversion gate. The inversion gate includes a first inversion gate forming an inversion layer serving as a source, a second inversion gate forming an inversion layer serving as a drain, and a third inversion gate disposed between the first inversion gate and the second inversion gate. And storing the bit by bit in the insulating film at both ends of the third inversion gate during writing.

The invention further includes the step of supplying a write voltage to the inversion layer through the global bit line at the time of writing. The present invention further includes supplying a voltage to the word line for drawing electrons injected into the memory cell to the semiconductor substrate using the FN tunnel effect during erasing. At this time, the voltage for drawing out to the semiconductor substrate side is preferably a negative voltage.

According to this invention, the semiconductor device and method which can suppress the increase of a circuit area can be provided.

1 is a diagram illustrating a memory array of a conventional AG-AND flash memory.

Fig. 2A is a cross-sectional view showing the voltage condition at the time of programming, and Fig. 2B is a cross-sectional view showing the voltage condition at the time of reading.

3 is a diagram illustrating an array configuration of AG-AND.

4 is a plan view of a memory array of the semiconductor memory device of the present embodiment.

5 is a cross-sectional view taken along the word line of FIG. 4.

6 is a schematic cross-sectional view showing a program operation state of the semiconductor memory device of the present embodiment.

7 is a schematic cross-sectional view showing a read operation state of the semiconductor memory device of the present embodiment.

8 is a schematic cross-sectional view showing an erase operation state of the semiconductor memory device of the present embodiment.

9 is a layout diagram of a core array in the embodiment of the present invention.

FIG. 10 is a cross-sectional view along the line A-A 'in FIG.

FIG. 11 is an equivalent circuit diagram of the core array shown in FIG. 9.

12 is a block diagram of the semiconductor memory device according to the present embodiment.

13 is an enlarged view of a column decoder, page buffer, BL decoder and global bit line (GBL).

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to attached drawing. 4 is a plan view of a memory array of the semiconductor memory device according to the embodiment of the present invention. 5 is a cross-sectional view taken along the word line of FIG. 4. As shown in FIG. 4, the word line WL extends perpendicular to the inversion gates IG ₀ to IG ₃ . The inversion gates IG ₀ to IG ₃ are for electrically connecting the inversion layer to the global bit line by forming an inversion layer (channel) serving as a local bit line on the semiconductor substrate. In other words, these IG gates IG ₀ to IG ₃ have the same function as the conventional sector transistors.

As shown in FIG. 5, the memory cell has a structure of a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) structure. A part of the surface of the semiconductor substrate 11 and the inversion gates IG ₀ to IG ₃ are covered by the ONO film 12 having a structure in which an oxide film, a nitride film and an oxide film are laminated. On the ONO film 12, a polysilicon gate electrode 13 that becomes a word line W ₃ is formed. A channel is formed by applying a predetermined voltage to the inversion layer used as the source and drain of the memory cell to raise the gate voltage. The memory cell of the SONOS structure is performed by changing the bias direction in which charge injection into the gate insulating film is applied to both electrodes serving as a source or a drain, and writes binary information independently to the gate insulating film near both electrodes. By inserting, two bits can be stored per memory cell. That is, this memory cell can store two bits per cell by storing one bit at both ends of the insulating film between the inversion gates.

6 is a schematic cross-sectional view showing a program operation state of the semiconductor memory device of the embodiment of the present invention. In the example shown in FIG. 6, writing to the memory cell is performed by source-side injection. Source side injection refers to the injection of electrons into the region located on the source side of the gate insulating film between adjacent IGs. As shown in Fig. 6A, in the left bit program operation, voltages of 0V, 5V, 1V, and 8V are supplied to the inverting gates IG ₀ , IG ₁ , IG _2, and IG ₃ , respectively. A voltage of 10 to 15V is supplied to the word line WL of the selected cell.

When 5V is applied to the inversion gate (first inversion gate) IG ₁ , an inversion layer (channel) 14 serving as a source is formed in the semiconductor substrate 11 below it. When 8V is applied to the inversion gate (second inversion gate) IG ₃ , the inversion layer 15 serving as a drain is formed in the semiconductor substrate 11 below it. By applying 1V to the inverted gate (third inverted gate) IG ₂ , the channel region under the inverted gate IG ₂ can be reduced, the electric field at the boundary can be strengthened, and the current can be suppressed. 0V is applied to the inversion gate (fourth inversion gate) IG ₀ to cut the channel so that no current flows. By applying 0V to the inversion layer 14 and 4.5V to the inversion layer 15, electrons move from the source toward the drain in the channel. Since the electric field on the drain side under the inversion gate IG ₂ becomes high, electrons moving in this channel acquire high energy to become hot electrons, and a part of them are trapped in the ONO film 12 as a bit A.

As shown in FIG. 6 (b), in the right bit program operation, voltages of 0 V, 8 V, 1 V, and 5 V are supplied to the inverting gates IG ₀ , IG ₁ , IG _2, and IG ₃ , respectively. A voltage of 10 to 15 V is supplied to the word line WL of the selected cell. When 5V is applied to the inversion gate IG ₃ , the inversion layer 17 serving as a source is formed in the semiconductor substrate 11 below it. When 8V is applied to the inversion gate IG ₁ , the inversion layer 16 serving as a drain is formed in the semiconductor substrate 11 below it. By applying a 1V to the inverted gate (IG _2), it is possible to weaken the channel below the inversion gate (IG _2), and suppress the electric current at the same time to strengthen the electric field boundary. 0V is applied to the inversion gate IG ₀ to cut the channel so that no current flows. By applying 0 V to the inversion layer 17 and 4.5 V to the inversion layer 16, electrons move from the inversion layer 17 serving as a source to the inversion layer 16 serving as a drain in the channel. Since the electric field on the drain side under the inverted gate IG ₃ becomes high, electrons moving in the channel acquire high energy to become hot electrons, and a part thereof is trapped in the ONO film 12 as a bit B.

Further, by applying a 1V to the inverted gate (IG _2), weaken the channel below the inversion gate (IG _2), and it is possible to suppress the current flowing through the channel, the program current, for example, to 100nA / cell or less It can be suppressed. Compared to the need to flow about 100 μA / cell of program current in a conventional floating gate or mirror bit (NOR flash memory), the program current is 1/100 or less. For this reason, cells can be written about 100 times at a time compared with the conventional one, for example, 1k bits can be programmed simultaneously. Therefore, high speed writing becomes possible.

7 is a schematic cross-sectional view showing a read operation state of the semiconductor memory device of the present embodiment. As shown in Figure 7, the read operation in the inverting gate (IG ₁₎ and inverting gate (IG ₂₎ by applying a voltage of 5V, the inverting gate (IG ₁₎ and inverting gate (IG ₂₎ the semiconductor substrate below (11 Inversion layers 18 and 19 are formed, respectively. When a voltage of 0 V is supplied to the inversion layer 18, 1.5 V to the inversion layer 19, and a voltage of 4 to 5 V is supplied to the word line WL of the selected cell, data of the corresponding cell is read.

8 is a schematic cross-sectional view showing an erase operation state of the semiconductor memory device of the present embodiment. As shown in Fig. 8A, during erasing, the inversion layers 20 and 21 are applied to the semiconductor substrate 11 below by applying a voltage of 5 V to the inversion gates IG on both sides of the memory cell. Is formed. A voltage of -15 to -20V is applied to the word line WL. The inversion layers 20 and 21 under the inversion gate IG are biased to 0V. Electrons injected into the ONO film 12 can be drawn out to the semiconductor substrate 11 side using a Fowler Nordheim (FN) tunnel effect.

In addition, as shown in FIG. 8B, when erasing, a voltage of 0 V is applied to the inverting gates IG on both sides of the memory cell of interest and a voltage of 15 to 20 V is applied to the word line WL. For example, the inversion gate IG is 0V, and the channel 22 is in a floating state. Electrons injected into the ONO film 12 can be drawn out to the word line 13 by using the FN tunnel effect.

In addition, as shown in FIG. 8C, during erasing, a voltage of 15 to 20 V is applied to the inversion gate IG, and a voltage of 0 V is applied to the word line WL, and the corner ( By field enhanced FN tunneling at the corners, electrons injected into the nitride film 122 of the ONO film 12 including the oxide film 121, the nitride film 122, and the oxide film 123 are extracted. Also good.

9 is a layout of the core array in the embodiment of the present invention. FIG. 10 is a cross-sectional view of the core array cut along the line AA ′ in FIG. 9. In Fig. 9, reference numeral S denotes a sector selection region, and M denotes a sector region each composed of, for example, 4 Mb memory cells. The semiconductor device according to the present invention includes a plurality of sector selection areas and sector areas. IG (0) to IG (3) represent inverted gate wiring patterns made of metal wiring, and GBL (0) to GBL (9) represent global bit lines made of metal wiring, respectively. The memory cell is located in an area where the word line WL and the global bit lines GBL (0) to GBL (9) are orthogonal to each other. Memory cells are formed between adjacent inverting gates. The part enclosed by the dotted line corresponds to the unit cell.

In the semiconductor substrate, polysilicon P1 serving as an inversion gate IG forming an inversion layer serving as a local bit line is formed in parallel with each other corresponding to the global bit lines GBL (0) to GBL (9). . The inverted gate wiring patterns IG (0) to IG (3) are connected to the polysilicon P1 via contacts 30. By applying a predetermined voltage to the inversion gate wiring patterns IG (0) to IG (3), an inversion layer 23 serving as a local bit line is formed on the semiconductor substrate under the polysilicon P1. The inversion layer 23 is connected to the metal wiring M1 via n + diffusion region S / D and the contact 31. The metal wiring M1 is electrically connected to the global bit lines GBL (0) to GBL 9 through the contact 32. By applying the voltages shown in Figs. 6 to 8 to the global bit lines GBL (0) to (9), inverting gates IG and word lines WL, writing, reading and erasing are performed on the memory cells. Becomes possible.

In this way, since the inversion gate IG functions as a switching transistor, as indicated by IGTr, an inversion layer serving as the local bit line LBL is electrically connected to the global bit lines GBL (1) to GBL (9). Can be accessed. For this reason, it is not necessary to provide the sector transistor which was conventionally required. Therefore, the area for the sector transistor can be reduced. Thereby, height (width of the code | symbol S of FIG. 9) can be made into 2 micrometers or less, for example. In addition, as described above, by applying 1 V to the inversion gate IG, the channel under the inversion gate IG can be weakened, and the current flowing in the channel can be suppressed, and the program current is, for example, 100 nA / It can suppress below a cell. Therefore, even when the width W of the word line is narrowed, it is possible to sufficiently flow the program current necessary for writing. Therefore, it is also possible to make the width W of a word line 90 nm or less. In the example shown in Fig. 9, although there are eight word lines, for example, 128 or 256 words may be used.

FIG. 11 is an equivalent circuit diagram of the core array shown in FIG. 9. As shown in FIG. 11, in the memory cell array M, a plurality of memory cells M11 to Mnm having ONO films are arranged in a matrix. In the memory cell array M, the group of memory cells arranged in the row direction is common to any one of the word lines WL extending in the memory cell array M in the row direction at each gate electrode. Is connected. In addition, the group of memory cells arranged in the column direction share an inversion layer serving as a local bit line LBL. That is, the source and the drain of the group of memory cells arranged in the column direction are common to any one of the global bit lines GBL through an inversion layer formed by the inversion gate IG and functioning as a local bit line LBL. Is connected. By applying the voltages shown in FIGS. 6 to 8 to the global bit lines GBL (1) to (9), the inversion gates IG, and the word lines WL, writing, reading, and erasing are performed on the memory cells. Becomes possible.

Since the inversion gate IG functions as a switching transistor, as indicated by IGTr, the inversion layer serving as the local bit line LBL can be electrically connected to the global bit line GBL. For this reason, it is not necessary to provide the sector transistor which was conventionally required, and the area | region for a sector transistor can be reduced.

12 is a block diagram of the semiconductor memory device according to the present embodiment. As shown in FIG. 12, the semiconductor memory device 51 includes a memory cell array 52, an I / O register buffer 53, an address register 54, a status register 55, and a command. Register 56, state machine 57, high voltage generation circuit 58, row decoder 59, page buffer 60 and column decoder 61, inversion The gate decoder 70 and the BL decoder 71 are included. The semiconductor memory device 51 may be provided in a semiconductor device.

In the memory cell array 52, nonvolatile memory cell transistors capable of rewriting along a plurality of word lines WL and a plurality of bit lines BL are arranged on a matrix.

The I / O register buffer 53 controls various signals or data corresponding to the I / O terminals. The address register 54 is for temporarily storing the address signal input through the I / O register buffer 53. The status register 55 is for temporarily storing state information. The command register 56 is for temporarily storing an operation command input through the I / O register buffer. The state machine 57 controls the operation of each circuit in the device in response to each control signal, and controls to apply a voltage to each component as shown in FIGS. 6 to 8.

The high voltage generation circuit 58 is to generate a high voltage used inside the device. The high voltages used inside the device include the high voltages for data writing, the high voltages for data erasing, the high voltages for data reading, and the checking whether the memory cells are writing or erasing sufficiently for data writing / erasing. Verification high voltage, etc. Therefore, the high voltage generation circuit 58 supplies the writing voltage to the inversion layer when writing. In addition, the high voltage generation circuit 58 supplies a voltage to the word line for drawing electrons injected into the memory cell to the semiconductor substrate 11 side using the FN tunnel effect during erasing. In the erase operation, the high voltage generation circuit 58 supplies a voltage to the word line for drawing electrons injected into the memory cell to the word line side using the FN tunnel effect. The high voltage generation circuit 58 supplies a voltage for drawing electrons injected into the memory cell to the inverted gate by using the FN tunnel effect during erasing.

The row decoder 59 selects a word line WL by decoding a row address input through the address register 54. The page buffer 60 includes a data latch circuit, a sense amplifier circuit, and the like. Upon reading, the page buffer 60 collectively senses and latches data stored in a plurality of memory cells connected to the same word line. At the time of writing, the write data input from the I / 0 register buffer 53 is sequentially latched to the latch circuit through the column decoder 61, and the write voltage is supplied to the memory cell in accordance with the latch data. In the page buffer 60, for example, 512B (one page) is provided.

The column decoder 61 decodes the column address input through the address register 54, selects a plurality of latch data latched in the page buffer 60 at predetermined units, and reads the I / O register buffer 53 at a predetermined unit. To be sent). At the time of writing, the write data input from the I / O register buffer 53 is sequentially transferred to the latch circuit in the page buffer 60 at predetermined units. In addition, the I / O register buffer 53, the row decoder 59, the column decoder 61, and the high voltage generator circuit 58 function based on the control from the state machine 57.

The inverting gate decoder 70 selects a memory cell that supplies a predetermined voltage to the inverting gate IG to perform writing or erasing. The inverted gate decoder 70 supplies a predetermined voltage signal to the inverted gate IG by the control of the address register. In sectors not selected by the input address, ₀ V is given to IG ₀ to IG ₃ . Depending on which global bit line GBL is selected in the selection sector, 0 V, 1 V, 5 V and 8 V are supplied to the predetermined inversion gate IG at the time of writing, and 0 V and 5 V are the predetermined inversion at the time of reading. It is supplied to the gate IG. The inversion gate decoder 70 supplies a voltage for weakening a channel formed between the source and the drain in the semiconductor substrate 11 to the inversion gate IG ₂ at the time of writing. In addition, the inversion gate decoder 70 writes a channel formed in the semiconductor substrate 11 to an inversion gate IG ₀ provided at a position opposite to the inversion gate IG _{2 as} viewed from the inversion gate IG ₁ . Supply the voltage to cut.

13 is an enlarged view of the column decoder 61, the page buffer 60, the BL decoder 71, and the global bit line GBL. The BL decoder 71 includes a plurality of path transistors 711 controlled by the signals C0, / C0 to C3, / C3 from the address register 54. The global bit line GBL has four sets of i-0 to i-3, each controlled by a common selection signal C0, / C0 to C3, / C3, and each page buffer 60-. i). At the time of reading, as described with reference to FIG. 7, for example, the selection signal C2 is set at the selection level High, and the global bit line GBLi-2 is connected to the page buffer 60 to supply the read voltage 1.5V. The global bit line GBLi-1 is set to 0V with the selection signal / C1 at the selection level High. At the time of writing, for example, as described with reference to FIG. 6A, the selection signal C3 is set to the selection level High, and the global bit line GBLi-3 is connected to the page buffer 60 to write the voltage. 4.5V is supplied, and the global bit line GBLi-1 is set to 0V with the selection signal / C1 being at the selection level High.

As mentioned above, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. In addition, the structure of a memory cell is not limited to the said embodiment.

Claims (23)

A semiconductor substrate; A word line; A global bit line; An inversion gate forming an inversion layer that becomes a local bit line on the semiconductor substrate and electrically connecting the inversion layer to the global bit line; And And a memory cell using the inversion layer as a source and a drain. The method of claim 1, And the inversion layer is connected to the global bit line through a metal wiring. The method of claim 1, And the memory cell is formed between adjacent inverting gates. The method of claim 1, And a selection circuit for selecting a memory cell for writing or erasing by supplying a predetermined voltage to the inversion gate. The method of claim 1, The inversion gate may include a first inversion gate forming the inversion layer serving as the source, a second inversion gate forming the inversion layer serving as the drain, and a second inversion gate disposed between the first inversion gate and the second inversion gate. Includes 3 inversion gates, And a selection circuit for supplying a predetermined voltage to the first to third inverted gates to select a memory cell for writing when writing. The method of claim 5, The selection circuit supplies a voltage for forming a channel region below the third inversion gate to be smaller in the channel region formed between the source and the drain in the semiconductor substrate at the time of writing. Semiconductor device. The method of claim 5, The inversion gate further comprises a fourth inversion gate disposed at a position opposite to the third inversion gate as viewed from the first inversion gate; And And the selection circuit supplies a voltage for cutting a channel formed in the semiconductor substrate to the fourth inverting gate upon writing. The method according to any one of claims 1 to 7, And a write-voltage supply circuit for supplying a write voltage to the inversion layer at the time of writing. The method according to any one of claims 1 to 4, And a voltage supply circuit for supplying the word line with a voltage for drawing electrons injected into the memory cell to the semiconductor substrate using an FN tunnel effect during erasing. The method according to any one of claims 1 to 4, And a voltage supply circuit for supplying the word line with a voltage for drawing electrons injected into the memory cell to a word line side using an FN tunnel effect during erasing. The method according to any one of claims 1 to 4, And a voltage supply circuit for supplying a voltage for drawing electrons injected into the memory cell to the inverted gate during erasing by using an FN tunnel effect. The method of claim 1, And a decoder having a plurality of column sets consisting of a plurality of said global bit lines and connecting predetermined global bit lines in said column set to corresponding page buffers respectively by a common selection signal. The method of claim 1, And the inversion layer is shared by a plurality of memory cells. The method according to any one of claims 1 to 13, And the memory cell stores two bits per cell by storing one bit at both ends of the insulating film between the inversion gates. The method according to any one of claims 1 to 14, And said memory cell is of SONOS type. The method according to any one of claims 1 to 15, And said semiconductor device is a semiconductor memory device. A first step of electrically connecting the inversion layer to the global bit line by supplying a predetermined voltage to the inversion gate to form an inversion layer that becomes a local bit line on the semiconductor substrate; And And a second step of selecting a word line. The method of claim 17, The inversion gate includes a first inversion gate forming an inversion layer serving as a source, a second inversion gate forming an inversion layer serving as a drain, and a third inversion provided between the first inversion gate and the second inversion gate. A gate; And And said first step comprises supplying a predetermined voltage to said first to third inverting gates upon writing. The method of claim 18, The first step may include supplying a voltage to the third inversion gate to form a smaller channel region below the third inversion gate among channel regions formed between the source and the drain in the semiconductor substrate. How to. The method of claim 18, The inversion gate further includes a fourth inversion gate disposed at a position opposite to the third inversion gate when viewed from the first inversion gate; And And wherein said first step further comprises supplying a voltage for cutting a channel formed in said semiconductor substrate to said fourth inversion gate upon writing. The method of claim 17, The inversion gate includes a first inversion gate forming an inversion layer serving as a source, a second inversion gate forming an inversion layer serving as a drain, and a third inversion provided between the first inversion gate and the second inversion gate. Including a gate, And at the time of writing, storing the bit by bit in the insulating film at both ends of the third inversion gate. The method according to any one of claims 17 to 21, Supplying a write voltage to the inversion layer through the global bit line upon writing. The method of claim 17, And supplying a voltage to the word line for drawing electrons injected into a memory cell to the semiconductor substrate using an FN tunnel effect during erasing.

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