KR20070081916A - Film for die bonding, packaging method for semiconductor chip and semiconductor chip package using the same - Google Patents

Abstract

A die bonding film, a method for packaging a semiconductor chip and a semiconductor chip package using the same are provided to prevent voids from being produced at an interface of the semiconductor chip by using adhesive layers having different fluidity. A semiconductor chip package includes boding wires(310,510) electrically connecting a wiring formed on a substrate(100) with semiconductor chips(300,500) formed on the substrate, in which upper and lower semiconductor chips are adhered to each other by a die bonding film. The die bonding film has at least two adhesive layers. The adhesive layer adhered on the lower semiconductor chip has fluidity higher relative to other adhesive to cover the bonding wire, and the adhesive layer adhered on the upper semiconductor chip has a lower fluidity.

Description

Film for die bonding, semiconductor chip packaging method and semiconductor chip package using the same {Film for die bonding, packaging method for semiconductor chip and semiconductor chip package using the same}

The following drawings attached to this specification are illustrative of preferred embodiments of the present invention, and together with the detailed description of the invention to serve to further understand the technical spirit of the present invention, the present invention is a matter described in such drawings It should not be construed as limited to.

1 is a cross-sectional view schematically showing the configuration of a semiconductor chip package according to the prior art.

2 is a cross-sectional view schematically showing the configuration of a semiconductor chip package according to a preferred embodiment of the present invention.

3 is a cross-sectional view showing an embodiment of a die bonding film used in a semiconductor chip package according to a preferred embodiment of the present invention.

<Description of Major Reference Marks in Drawing>

100. Substrate 200. Bonding material 300. First semiconductor chip

400. Die film 500. Second semiconductor chip

The present invention relates to a die bonding film used in the process of manufacturing a semiconductor chip package in which a plurality of semiconductor chips are laminated. More specifically, the die bonding film can simplify the process and improve the reliability of the product. The present invention relates to a semiconductor chip packaging method and a semiconductor chip package using the same.

In general, a semiconductor packaging process includes a wafer dicing process for cutting a wafer into unit semiconductor chips, and a die for attaching the cut semiconductor chip to a chip mounting frame such as a lead frame, a printed circuit board, or a substrate such as a tape wiring board. A unit bonding process of a die bonding process, a wire bonding process of electrically connecting the semiconductor chip and the chip mounting frame, and an epoxy molding compound (EMC) process of sealing the semiconductor chips and the bonding wire. .

1 is a cross-sectional view of a portion of a stacked multi-chip package according to the prior art. As shown in FIG. 1, when the two semiconductor chips 30 and 60 are sequentially stacked on the printed circuit board 10, an adhesive layer 20, for example, an epoxy paste, may be formed on the upper surface of the printed circuit board 10. epoxy paste) 20 is applied and the first semiconductor chip 30 is attached. The first semiconductor chip 30 is electrically connected to the substrate 10 by performing wire bonding (see 70a) with the wiring layer 11 of the printed circuit board 10.

Then, the second semiconductor chip 60 is attached onto the first semiconductor chip 30 using the die bonding film 50. Next, the second semiconductor chip 60 performs wire bonding (see 70b) with the wiring layer 11 of the printed circuit board 10 to electrically connect the second semiconductor chip 60 to the substrate 10.

Meanwhile, a spacer 40 is interposed between the first semiconductor chip 30 and the die bonding film 50 to provide a space for the bonding wire 70a connected to the first semiconductor chip 30. As the spacer 40, a chip without an element is mainly used. In this case, the vertical and horizontal widths of the spacer 40 are smaller than those of the first and second semiconductor chips 30 and 60.

However, the above structure is not only cumbersome because the process of attaching the spacer 40 separately is added, and the interface between the spacer 40 and the first semiconductor chip 30, the spacer 40, and the die bonding film 50. A void 80 may be caused to deteriorate the reliability of the semiconductor chip package. In addition, the adhesion of the contact surface is weakened by the generation of voids, there is a problem that the semiconductor chip is shaken or separated during the wire bonding.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the die bonding film which can simplify the process of bonding a plurality of semiconductor chips and can suppress the generation of voids at the interface between the semiconductor chip and the adhesive layer and the semiconductor chip packaging using the same Its purpose is to provide a method and a semiconductor package.

Die bonding film according to an aspect of the present invention for achieving the above object, a semiconductor chip comprising a bonding wire for laminating a plurality of semiconductor chips on a substrate and electrically connecting each semiconductor chip and the wiring provided on the substrate A die bonding film for bonding upper and lower semiconductor chips to each other in a package, the die bonding film comprising at least two adhesive layers, and the adhesive layer contacting the lower semiconductor chip among the upper and lower semiconductor chips having the die bonding film interposed therebetween. The fluidity is relatively high compared to other adhesive layers so as to cover the bonding wire, and the fluidity is relatively small toward the adhesive layer to which the upper semiconductor chip contacts.

According to another aspect of the present invention, a semiconductor chip package includes a substrate and a first semiconductor chip mounted on the substrate, a bonding material interposed between the first semiconductor chip and the substrate and bonded thereto, and the first semiconductor chip. A first bonding wire electrically connecting an electrode of the electrode and a wiring layer provided on the substrate, a second semiconductor chip mounted on the first semiconductor chip, and interposed between the first semiconductor chip and the second semiconductor chip. And a second bonding wire for bonding the die bonding film to cover the first bonding wire and electrically connecting the electrode of the second semiconductor chip and the wiring layer provided on the substrate.

Preferably, the thickness of the die-bonding film is 40 to 70㎛.

Preferably, the die-bonding film is an elastomer film, the elastomer film is a resin mixture in which the weight ratio of epoxy resin and rubber resin is mixed in a ratio of 3: 7 to 8: 2, 1-40 parts by weight of the added flow regulator and a small amount of the curing agent per 100 parts by weight of the resin mixture.

In addition, the semiconductor chip packaging method according to the present invention comprises the steps of preparing a substrate having a wiring layer for wire bonding on the upper surface, attaching a first semiconductor chip through the bonding material on the substrate, and the first Electrically connecting an electrode of a semiconductor chip and a wiring layer provided on the substrate through a bonding wire, and a second semiconductor chip having a die attaching film having fluidity on the first semiconductor chip having the bonding wire formed thereon. Laminating and bonding the first semiconductor chip and the second semiconductor chip to each other while the die bonding film covers the bonding wire.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the ordinary or dictionary meanings, and the inventors should have properly applied the concept of terms in order to best explain the invention of the photograph. It should be interpreted as a semantic concept consistent with the technical spirit of the present invention based on the principle that it can be defined. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various equivalents that may be substituted for them at the time of the present application It should be understood that there may be water and variations.

2 is a cross-sectional view schematically showing the configuration of a semiconductor chip package according to an embodiment of the present invention.

2, a semiconductor chip package according to the present invention includes a semiconductor chip 300, 500, a substrate 100 on which the semiconductor chip 300 is mounted, and a semiconductor chip 300 between the substrate 100 and the substrate 100. The interposed bonding material 200, the die bonding film 400 and the bonding wires 310 and 510 interposed between the semiconductor chip 300 and the semiconductor chip 500 are included.

The substrate 100 is where the semiconductor chip 300 is mounted, and one surface thereof is coated with a bonding material 200 for adhering the semiconductor chip 300. The substrate 100 includes a wiring layer 110 electrically connected to an electrode of the semiconductor chip 300. As the semiconductor chip mounting substrate 100, a printed circuit board is mainly used.

The semiconductor chip package according to the present exemplary embodiment has a structure in which a plurality of semiconductor chips 300 and 500 are stacked, and includes a first semiconductor chip 300 and a second semiconductor chip 500. The first semiconductor chip 300 is bonded onto the substrate 100 through a bonding material 200. At this time, an epoxy paste is used as the bonding material 200. However, the present invention is not limited thereto.

The first semiconductor chip 300 is electrically connected to the substrate 100 through the first bonding wire 310. The first bonding wire 310 connects the connection electrode (not shown) formed on the upper surface of the first semiconductor chip 300 to the wiring layer 110 provided on the substrate 100.

The second semiconductor chip 500 is mounted on the first semiconductor chip 300. At this time, the die bonding film 400 according to the present invention is interposed between the first semiconductor chip 300 and the second semiconductor chip 500 to bond the two semiconductor chips 300 and 500.

The die bonding film 400 has the same width and length as the first and second semiconductor chips 300 and 500. Therefore, the die bonding film 400 covers the first bonding wire 310 on the first semiconductor chip 300. To this end, it is preferable that the die bonding film 400 has fluidity before curing of the film is completed in the bonding process of the first and second semiconductor chips 300 and 500. For example, an elastomer film having fluidity is used as the die-bonding film 400 (hereinafter referred to as an elastomer film).

The elastomer film 400 is a low modulus epoxy-rubber material that can reduce the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the substrate and improve the reliability of the semiconductor chip package.

The elastomer film 400 is a resin mixture in which the weight ratio of epoxy resin and rubber resin is mixed in a ratio of 3: 7 to 8: 2, and a fluidity regulator added in an amount of 1 to 40 parts by weight based on 100 parts by weight of their total content. And a small amount of hardener.

The epoxy resin is a bisphenol A (DGEBA; diglycidyl ether of bisphenol A) epoxy, a phenolic (Phenol) Novolac epoxy, a bisphenol F (DGEBF (diglycidyl ether of bisphenol F) epoxy, trifunctional epoxy, acrylate polymer, acrylic It is resin which the rate-epoxy copolymer, silicone, imide, and urethane mixed in the predetermined ratio.

The rubber resin is CTBN (carboxyl terminated butadiene acrylonitrile), ETBN (epoxy-terminated butadiene-acrylonitrile), ATBN (amine-terminated butadiene-acrylonitrile), acrylonitrile (Acrylonitrile) is a resin mixed in a predetermined ratio.

As the fluidity regulator, Cabot's fumed silica M50 and TS720 are mixed and used, and the fumed silica serves to control the flowability of the elastomer film 400.

As the curing agent, a solid amine curing agent, a liquid amine curing agent or a mixture thereof is used.

The elastomer film 400 should have fluidity to cover the first bonding wire 310 during the bonding process of the first semiconductor chip 300 and the second semiconductor chip 500, and if not causing voids and defects of the bonding wire Two semiconductor chips 300 and 500 should be effectively bonded. Accordingly, physical properties such as storage elastic modulus, viscosity, surface tension, and resin flow of the film should be controlled. As a method of controlling the physical properties of the film, there is a method of adjusting the type and content of the components constituting the film or a method of irradiating ultraviolet rays, etc. to the produced film, but the amount of irradiation and the direction of irradiation.

Specifically, the elastic modulus of the elastomer film 400 is preferably 1 to 1000MPa. More preferably, the storage modulus is 10 to 300 MPa. If the storage elastic modulus is less than 1 MPa, an overflow may occur to cause a defect in the bonding wire. If the storage elastic modulus exceeds 1000 MPa, the bonding wire may be excessively pressed to cause disconnection of the bonding wire.

The viscosity of the elastomer film 400 is preferably 5 to 500 gf / cm, more preferably 7 to 100 gf / cm. If the viscosity is less than 5 gf / ㎝, the adhesion between the film and the semiconductor chip is weak, if the viscosity exceeds 500 gf / ㎝ may cause peeling phenomenon at the interface between the substrate and the first semiconductor chip due to the high adhesion between the film and the semiconductor chip .

The surface tension of the elastomer film 400 is preferably 10 to 50 erg / cm 2, more preferably 25 to 45 erg / cm 2. If the surface tension is less than 10 erg / cm 2, there is a limit to the formation of the film layer with a desired thickness due to the heavy flow of the elastomer film, and if the surface tension exceeds 50 erg / cm 2, a problem may occur in the adhesive force between the film and the semiconductor chip. .

The elastomeric film 400 was cut to a size of width x length x height of 1 cm x 1 cm x 1 mm, and then attached to glass, and laterally extended from the center of the elastomer film when pressed at a pressure of 0.2 MPa at 100 ° C. It is preferable that length and height are 10 micrometers-5000 micrometers. More preferably 60 µm to 1000 µm. If the extended horizontal and vertical length is less than 10㎛, there is a problem that the fluidity of the elastomer film is too small to press without naturally covering the bonding wire, and if the extended horizontal and vertical length exceeds 5000㎛, the flow is too low during pressing There is a serious problem.

On the other hand, the elastomer film may be applied in various ways in consideration of the adhesive force in addition to fluidity.

3 is a cross-sectional view showing an embodiment of a die bonding film 400 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the die bonding film 400 is formed of a plurality of layers, for example, three layers 410, 420, and 430. Here, the fluidity of each layer is changed by adjusting the type and content of the components constituting the elastomer film 400.

Specifically, since the first layer 410 should cover the bonding wire 310 provided on the first semiconductor chip 300 when the semiconductor chip 300 is bonded, the first layer 410 has a relatively large fluidity compared to other layers. However, when the semiconductor chip is bonded, the die-bonding film flows down due to pressure, which may cause a defect in the bonding wire. Therefore, in order to compensate for this, the fluidity of the second layer 420 and the third layer 430 is relatively small. The third layer 430 is adjusted to be close to a solid state to prevent flowing down due to pressure and to improve adhesion to the second semiconductor chip 500 on the upper surface.

Meanwhile, in the present embodiment, the die bonding film 400 is illustrated in a three-layer structure, but the present invention is not limited thereto. For example, the die bonding film 400 may be formed of a single layer similar to the thickness of the final film described above, that is, a die bonding film composed of a plurality of layers. After forming the die bonding film, the fluidity of the die bonding film of the single layer is differently controlled using the same precursor material. For example, the ultraviolet ray is irradiated to the thick die-bonding film, and the irradiation amount and irradiation direction of the ultraviolet rays are changed for each part so as to have different fluidity in the single layer film.

In addition, the die bonding film 400 is provided with a protective film 440 on the upper and lower surfaces, respectively. Preferably, the protective film 440 uses a polyethylene terephtalate (PET) film. However, the present invention is not limited thereto.

Next, a semiconductor chip packaging method according to the present invention will be described.

First, the substrate 100 on which the wiring layer 110 is provided is prepared. Then, the first semiconductor chip 300 is attached to the substrate 100 through the bonding material 200, and the electrode of the first semiconductor chip and the wiring layer 110 provided on the substrate 100 are bonded through the bonding wires. Connect electrically.

Next, the second semiconductor chip 500 is stacked on the first semiconductor chip 300, and a die bonding film 400 is attached to one surface of the second semiconductor chip 500. The second semiconductor chip 500 and the first semiconductor chip 300 to which the die bonding film 400 is attached are bonded to each other. Here, the die bonding film 400 has fluidity, and when the surface on which the die bonding film 400 of the second semiconductor chip 500 is attached is contacted with the first semiconductor chip 300, the first semiconductor chip Covering bonding wires 310 provided on both ends of the upper surface of the (300). That is, the die bonding film 400 flows in the direction of the first semiconductor chip 300 without pressing the bonding wire 310 to bond the first semiconductor chip 300 and the second semiconductor chip 500 to each other.

On the other hand, the semiconductor chip package of the present embodiment has a structure in which two semiconductor chips are stacked, but is not limited thereto, and may have a structure in which three or more semiconductor chips are stacked by interposing the above-described single layer or multilayer elastomer film. Accordingly, three or more semiconductor chips can be stacked successively in the same manner as described above.

Hereinafter, an experimental example will be described in detail to help the understanding of the present invention. However, the experimental examples according to the present invention may be modified in various other forms, and the scope of the present invention should not be construed as being limited to the following experimental examples. Experimental examples of the present invention are provided to more completely explain the present invention to those skilled in the art.

Experimental Example

Among the epoxy resins, 40g of DGEBA epoxy having 180g / mol of epoxy equivalent weight (EEW; molecular weight divided by epoxy resin), 40g of DGEBA epoxy having an epoxy equivalent of 20000g / mol, and CTBN having a product name of 1300 * 8 as rubber resin 5 g, 15 g of CTBN having a product name of 1300 * 13, and diphrandiamide 3phr as a curing agent were mixed, and these were mixed by using a mechanical method at a speed of 300 rpm for 3 hours to prepare a mixture. Then, the molded mixture was molded into a desired shape on the PET film, and then subjected to an ultraviolet curing process, where the lower semiconductor chip is attached with a relatively low fluidity and the upper semiconductor chip is attached. The part completed the relatively fluid elastomeric film. Through this method, a plurality of elastomer films having different overall thicknesses were prepared.

Table 1 summarizes the components and the respective contents of the above-described mixture.

ingredient content  DGEBA epoxy EEW = 180 g / mol 40 g EEW = 20000 g / mol 40 g  Hycar CTBN 1300 * 8 5 g 1300 * 13 15 g dicyandiamide - 3phr

Then, the elastomer film prepared according to the experimental example was attached to a semiconductor wafer, and the physical properties of the elastomer film were measured.

1. Thickness Measurement

The package on which the semiconductor wafer and the elastomer film were bonded was broken, and its cross-sectional thickness was measured using a scanning electron microscope (SEM).

2. Thickness deviation

The package on which the semiconductor wafer and the elastomer film were bonded was broken, and the thickness variation of the cross section was measured using a scanning electron microscope (SEM).

Thickness deviation (%) = A / B x 100%

Here, A is the thickness of the thickest portion of the elastomer film minus the thickness of the middle thick portion of the elastomer film, B is the thickness of the middle portion of the elastomer film attached to one side of the semiconductor wafer.

If the thickness variation of the elastomer film is 10 µm or more, the rejection treatment is performed.

3. Semiconductor chip adhesion characteristics

The semiconductor chip was attached to the elastomer film by applying a pressure of 0.8 MPa at 120 ° C. for 1.5 seconds, and the shear stress strength of the attached semiconductor chip was measured. Here, if a shear stress intensity is 0.5 Kgf / square 5mm * 5mmchip or more, it is a pass.

4. Moisture Resistance Test (MRT)

85 ° C. 1 day at 85% Reliability of semiconductor chip package by judging the occurrence of crack and pop-corn phenomenon when IR Reflow (heating by infrared radiation heat) at high temperature up to 260 ℃ (or Pbfree condition specified by Jedec) after constant temperature and humidity storage Was evaluated.

After measuring the physical properties of the elastomer film prepared according to the above experimental example, the results are summarized in Table 2 below.

Experimental Example 1 Experimental Example 2 Experimental Example 3 Experimental Example 4 Experimental Example 5 Experimental Example 6 Thickness of Die Adhesive Film 30 μm 40 μm 50 μm 60 μm 70 μm 80 μm Thickness variation of film for die bonding Within 10% Less than 10% Less than 10% Less than 10% Less than 15% Less than 20% Bad bonding wire Bad Good Good Good Good Good Void occurrence has exist none none none none none MRT pass pass pass pass pass pass

Referring to Table 2, in Experimental Example 1, the thickness of the die-bonding film, that is, the elastomer film, was 30 µm, respectively, and the thickness variation of the film was within 10%, within 3 µm, thereby satisfying the pass treatment range. In addition, although no voids occurred when the die was attached, defects occurred in the bonding wires.

In Experimental Example 6, there was no problem in bonding wire defects, voids, or MRT test during die bonding, but the film thickness variation was less than 20% (less than 16 µm) in all cases and did not satisfy the pass treatment range.

On the other hand, in the case of Experimental Example 2 to Experimental Example 5, the thickness variation of the film, the defect of the bonding wire, the void generation, the MRT test was all good enough to pass or use.

Therefore, the thickness of the elastomer film capable of bonding a plurality of semiconductor chips with fluidity so as to cover the bonding wire is preferably 40 to 70 µm.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

According to the present invention, it is possible to reduce the inconvenience of providing a separate space before the wire bonding process by using a fluid die-bonding film, thereby preventing voids generated on the interface of the semiconductor chip.

In addition, it is possible to improve the reliability of the semiconductor chip package product by suppressing voids and drippings.

Claims (21)

A die bonding film for laminating a plurality of semiconductor chips on a substrate, and bonding upper and lower semiconductor chips of a semiconductor chip package including bonding wires electrically connecting the semiconductor chips and wirings provided on the substrate. The die bonding film includes at least two adhesive layers, and the adhesive layer contacting the lower semiconductor chip among the upper and lower semiconductor chips with the die bonding film interposed therebetween is relatively fluid compared to other adhesive layers so as to cover the bonding wire. Die bonding film, characterized in that the fluidity is relatively large toward the adhesive layer in contact with the upper semiconductor chip. The method of claim 1, The die bonding film includes a resin mixture in which a weight ratio of an epoxy resin and a rubber resin is mixed at a ratio of 3: 7 to 8: 2, a flow regulator and a small amount of 1 to 40 parts by weight added to 100 parts by weight of the resin mixture. Contains a curing agent, The adhesive layer in contact with the lower semiconductor chip is a die bonding film, characterized in that the relatively higher content of the fluidity regulator than the adhesive layer in contact with the upper semiconductor chip. The method of claim 1, The die bonding film is irradiated with ultraviolet rays, the irradiation amount and the direction of irradiation is adjusted for each part of the die contact portion is characterized in that the fluidity is relatively higher than the portion in contact with the lower semiconductor chip Adhesive film. The method of claim 1, The die bonding film has a thickness of 40 to 70 µm. The method of claim 1, The die-bonding film, characterized in that the storage modulus of the die-bonding film is 1 to 1000 MPa. The method of claim 1, The die-bonding film, characterized in that the viscosity of the die-bonding film is 5 to 500gf / cm. The method of claim 1, The die-bonding film, characterized in that the surface tension of the die-bonding film is 10 to 50erg / ㎠. The method of claim 2, The flow control agent is a die-bonding film, characterized in that fumed silica (fumed silica). The method of claim 8, The dry silica is a die-bonding film, characterized in that the carbot (Carbot) M50 or TS720. A semiconductor chip mounting substrate; A first semiconductor chip mounted on the substrate; A bonding material interposed between the first semiconductor chip and the substrate; A first bonding wire electrically connecting an electrode of the first semiconductor chip to a wiring layer provided on the substrate; A second semiconductor mounted on the first semiconductor chip; A die bonding film interposed between the first semiconductor chip and the second semiconductor chip and bonded to each other and covering the first bonding wire; And And a second bonding wire electrically connecting the electrode of the second semiconductor chip to the wiring layer provided on the substrate. The method of claim 10, The die-bonding film has a thickness of 40 to 70㎛ semiconductor chip package, characterized in that. The method of claim 10, The die adhesion film is a semiconductor chip package, characterized in that the elastomer film. The method of claim 12, The elastomer film may include a resin mixture in which a weight ratio of an epoxy resin and a rubber resin is mixed in a ratio of 3: 7 to 8: 2, a flow control agent added to 1 to 40 parts by weight based on 100 parts by weight of the mixture, and a small amount of a curing agent. Semiconductor chip package comprising a. The method of claim 12, The elastomer film has a storage modulus of 1 to 1000MPa semiconductor chip package. The method of claim 12, The elastomeric film is a semiconductor chip package, characterized in that the viscosity of 5 to 500gf / cm. The method of claim 12, The elastomer film is a semiconductor chip package, characterized in that the surface tension of 10 to 50erg / ㎠. The method of claim 12, The flow control agent is a semiconductor chip package, characterized in that fumed silica (fumed silica). The method of claim 17, The dry silica is a semiconductor chip package, characterized in that Carbot (M50 or TS720). The method of claim 10, The die bonding film includes at least two adhesive layers, and the adhesive layer of the die bonding film contacting the lower semiconductor chip among the upper and lower semiconductor chips having the die bonding film interposed therebetween bond wires of the lower semiconductor chip. The semiconductor chip package, characterized in that the fluidity is relatively high compared to the other layers to cover, the fluidity is relatively small toward the adhesive layer of the die bonding film in contact with the upper semiconductor chip. The method of claim 10, The die bonding film is provided with a single adhesive layer, and a relatively large amount of ultraviolet rays are irradiated to a portion of the upper and lower semiconductor chips contacted with the lower semiconductor chip through which the die bonding film is interposed, and thus, compared with other layers. The semiconductor chip package, characterized in that the fluidity is large, the relatively small amount of ultraviolet radiation is irradiated toward the portion in contact with the upper semiconductor chip. Preparing a substrate having a wiring layer for wire bonding on an upper surface thereof; Attaching a first semiconductor chip to the substrate through a bonding material; Electrically connecting an electrode of the first semiconductor chip and a wiring layer provided on the substrate through a bonding wire; And Laminating a second semiconductor chip with a die attach film having fluidity on the first semiconductor chip having the bonding wire formed on an upper surface thereof, so that the die attach film covers the bonding wire and the first semiconductor chip and the first A method of manufacturing a semiconductor chip package comprising a; bonding the semiconductor chips to each other.

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