KR20070080929A - Display device - Google Patents

Abstract

A display device is provided to prevent an abnormal image from being displayed on a screen by preventing an abnormal data voltage from being applied to pixels. A display device includes plural pixels, a gate driver(400), and a data driver. The gate driver sequentially applies a gate-on voltage to the pixels in synchronization with a gate clock signal. The data driver receives data in synchronization with a data clock signal, converts the data to an analog data voltage, and applies the analog data voltage to the pixels. A state of the gate clock signal is fixed from when an abnormal data is transferred to the data driver until normal data is transferred to the data driver. The abnormal data is generated due to a variation in the data clock signal. When the gate-on voltage is synchronization with a rising edge of the gate clock signal, the gate clock signal is fixed at a high level.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a data driver integrated circuit of a data driver according to an exemplary embodiment of the present invention.

5 is a signal waveform diagram illustrating an operation of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a block diagram of a gate driver of a liquid crystal display according to another exemplary embodiment of the present invention.

7 is a signal waveform diagram illustrating an operation of a liquid crystal display including the gate driver of FIG. 6.

The present invention relates to a display device.

In recent years, with the reduction in weight and thickness of personal computers and televisions, display devices are also required to be lighter and thinner, and cathode ray tubes (CRTs) are being replaced by flat panel displays.

Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), organic light emitting displays, plasma display panels (PDPs), and the like. There is this.

In general, in an active matrix flat panel display, a plurality of pixels are arranged in a matrix form, and an image is displayed by controlling the light intensity of each pixel according to given luminance information. Among them, the liquid crystal display includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The liquid crystal display device applies an electric field to the liquid crystal layer, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

An object of the present invention is to provide a liquid crystal display device for preventing an error occurring during data transmission between a signal controller and a data driver.

According to an exemplary embodiment of the present invention, a display device includes a plurality of pixels, a gate driver for sequentially applying a gate-on voltage to the pixels in synchronization with a gate clock signal, and data in synchronization with a data clock signal. And a data driver for converting the data into an analog data voltage and applying the data to the pixel, wherein normal data is transmitted to the data driver from the time when abnormal data according to the change of the data clock signal is transmitted to the data driver. The state of the gate clock signal is fixed until

When the gate on voltage is synchronized at the rising edge of the gate clock signal, the gate clock signal may be fixed to a high level from when the abnormal data is transmitted until the normal data is transmitted.

When the gate-on voltage is synchronized at the falling edge of the gate clock signal, the gate clock signal may be fixed at a low level from when the abnormal data is transmitted until the normal data is transmitted.

The pixel may display black for a predetermined period according to the normal data.

The gate driver may receive an output enable signal for adjusting a holding time of the gate-on voltage, and may fix the state of the output enable signal from when the abnormal data is transmitted until the normal data is transmitted. .

The data driver includes a plurality of data driver circuits, the data driver circuits receiving a plurality of data from the data driver circuits at the front end, selecting one data from the received data, and remaining data not selected at the rear end. It can be transferred to the data drive circuit.

The data driving circuit may include a delay circuit for rearranging the data according to the data clock signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 550 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 550.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data voltage ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, a pixel connected to an i-th (i = 1, 2, ..., n) gate line G _i and a j-th (j = 1, 2, ..., m) data line Dj PX includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 2, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 550 generates two gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ). The detailed structure of the gate driver 400 will be described later.

Data driver 500 is connected with the data lines (D ₁ -D _m) of the liquid crystal panel assembly 300, select a gray voltage from the gray voltage generator 800 and the data lines do this as a data voltage (D ₁ -D _m ). The detailed structure of the data driver 500 will be described later.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 550, and 600 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 550, and 600 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 550, and 600 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the normal operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one gate clock signal CLK for controlling the output timing of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is configured to apply an analog data voltage to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of the transmission of the image signal DAT for one row of pixels PX. The load signal LOAD and the data clock signal HCLK are included. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the analog data voltage relative to the common voltage Vcom (hereinafter referred to as " polarity of the data voltage " RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives a plurality of output image signals DAT for one row of pixels PX, and outputs each output image signal DAT. The output image signal DAT is converted into an analog data voltage by selecting a gray scale voltage corresponding to and then applied to the data lines D ₁ -D _m .

The gate driver 400 receives the gate control signal CONT1 from the signal controller 600 and outputs the gate-on voltage Von in synchronism with the rising edge of the gate clock signal CLK. When the gate-on voltage (Von) is applied to the gate lines (G ₁ -G _n) is a gate line switching element (Q) connected to the (G ₁ -G _n) is turned on. Then, the data voltage applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data voltage applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in the transmittance of light by a polarizer attached to the display panel assembly 300, whereby the pixel PX displays the luminance represented by the gray level of the output image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied, and the data voltage is applied to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarities of the data voltages flowing through one data line may be changed (eg, row inversion and point inversion), or polarities of data voltages applied to one pixel row may be different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Now, the data driver 500 will be described in detail with reference to FIGS. 3 and 4.

3 is a block diagram of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram of a data driver integrated circuit of a data driver.

Referring to FIG. 3, the data driver 500 according to an embodiment of the present invention may include a plurality of, for example, first through kth data driving integrated circuits IC1, IC2,..., ICk (k). Is a natural number).

The data driving integrated circuits IC1, IC2,..., And ICk are sequentially arranged in the row direction of the display panel unit 300, and are integrated between the signal controller 600 and the first data driving integrated circuit IC1 and adjacent data driving integrated circuits. Transmission line groups DT1-DTk including at least one transmission line group are connected between the circuits IC1, IC2,..., ICk.

The number of transmission line groups belonging to the first transmission line group DT1 positioned between the signal controller 600 and the first data driving integrated circuit IC1 is the number of data driving integrated circuits IC1, IC2,..., ICk (= k). ), The number of transmission lines belonging to the transmission line group DT ₁ -DT _k decreases by one each time the data driving integrated circuits IC1, IC2, ..., ICk pass through one. Therefore, the transmission line group belonging to the pth transmission line group DT _p between the (p-1) th data driving integrated circuit ICp-1 (p = 2, ..., k) and the pth data driving integrated circuit ICp. The number is (k + 1-p). In addition, the number of transmission line groups belonging to the last transmission line group DTk between the last data driving integrated circuit ICk and the previous data driving integrated circuit ICk-1 is one.

The signal controller 600 includes k data transmission integrated circuits IC1, IC2,... Each of k transmission line groups belonging to the first transmission line group DT1 (the transmission line group belonging to the kth transmission line group is referred to as the kth transmission line). , One video signal (DAT ₁ -DAT _k ) allocated to ICk is transmitted.

Each transmission line group also has the same number of signal lines as the number of primary colors represented by the pixels PX of the display device. For example, if the input image signals R, G, and B input to the signal controller 600 are for the pixels PX representing red, green, and blue (hereinafter, the pixels representing red, green, and blue are red, respectively). Pixels, green pixels, and blue pixels, and image signals associated with these pixels are called red image signals, green image signals, and blue image signals, respectively, and each of the transmission line groups is a red signal line (not shown) for transmitting red image signals. , A green signal line (not shown) for transmitting the green image signal, and a blue signal line (not shown) for transmitting the blue image signal. Each of the red, green, and blue signal lines may include a sub signal line (not shown) corresponding to or less than the number of bits of the video signal.

In this structure, each of the data driving integrated circuits IC1, IC2, ..., ICk receives only the image signals DAT ₁ -DAT _k necessary for its own and the remaining image signals are transmitted through the transmission line group to the next data driving integrated circuit IC1. , IC2, ..., ICk).

For example, the first data driver integrated circuit (IC1) 540 receives k image signals DAT ₁ -DAT _k from the signal controller 600 through the k first transmission line groups DT ₁ , The first image signal DAT1 required for the first data driver integrated circuit IC1 is selected, and the remaining (k-1) image signals DAT ₂ -DAT _{k select} the second transmission line group DT ₂ . Transfer to the second data driver integrated circuit (IC2) through.

The p th data driving integrated circuit ICp is (k + 1-p) from the previous data driving integrated circuit, ie, the (p-1) th data driving integrated circuit IC _p-1 through the p th transmission line group DT _p . ) Video signals (DAT _p -DAT _k ) are received, and the _{p- th} video signal group (DAT _p ) is selected therefrom, and the remaining video signals (DAT _{p +1} -DAT _k ) are transmitted (p + 1). The data is transferred to the next data driving integrated circuit IC _{p + 1} through the group DT _{p + 1} . The last k-th data driving integrated circuit ICp receives one image signal DAT _k from the (k-1) th data driving integrated circuit IC _k-1 through the k _- th transmission line group DT _k . This can be done.

In the case of transmitting the image signals DAT _{1 to} DAT _{k in the} cascading transmission scheme, the data driving integrated circuits IC1, IC2, and the data driving integrated circuit ICk far from the signal controller 600 may be transferred. Each time…, I, k) decreases the transmission line group. Therefore, while significantly reducing the number of wires, the logic for receiving and transmitting by the reduced number of wires can also be reduced, thereby reducing power consumption of the data driver 500.

Referring to FIG. 4, a data driver integrated circuit according to an embodiment of the present invention, typically a first data driver integrated circuit (IC1) 540, will be described.

The first data driver integrated circuit (IC1) 540 includes an input unit 545, an output unit 546, and a shift register 541 and a latch 542 connected in turn. ), A digital-to-analog converter 543 and an output buffer 544.

Input unit 545, the signal controller 600 receives the first transmission military first (DT _1), k of the output video signal (DAT ₁ -DAT _k) from which are connected with, and of which a first output image signal (DAT1) Choose.

The output unit 546 is connected to the second transmission line group DT ₂ , and rearranges the remaining output image signals DAT ₂ -DAT _k except for the first output image signal DAT1 according to the data clock signal HCLK. The second data driving integrated circuit IC2 is transmitted through the second transmission line group DT ₂ -DT _k . The output unit 546 includes a delay circuit for realigning the output image signals DAT _{1 to} DAT _k , for example, a delay lacked loop (DLL), and the like.

The shift register 541 transfers the selected first output image signal DAT1 to the latch 542 when the horizontal synchronization start signal STH (or the shift clock signal) is input. The shift register 541 of the data driving integrated circuits IC1, IC2, ..., ICk sends the shift clock signal to the shift register 541 of the data driving integrated circuits IC1, IC2, ..., ICk of the subsequent stage.

The latch 542 stores each data of the output image signal DAT1 and sends it to the digital-to-analog converter 543 according to the load signal LOAD.

The digital-analog converter 543 receives the gray voltage from the gray voltage generator 550, converts the output image signal DAT1 into an analog voltage, and outputs the gray voltage to the output buffer 544.

The output buffer 544 outputs the output voltage from the digital-to-analog converter 543 to the output terminals Y1, Y2, ..., Yr as data voltages, and maintains it for one horizontal period.

Hereinafter, an operation of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIG. 5 when the frequency of the data clock signal HCLK changes.

The delay circuit of the output unit 546 of the data driving integrated circuits IC1, IC2,..., And ICk may reduce skew of the output image signals DAT _{1 to} DAT _k , but the frequency of the data clock signal HCLK may be reduced. Can not react in real time according to the rapid change of. Therefore, a sufficient reset time is required when the data clock signal HCLK frequency changes rapidly, and an abnormal output image signal is transmitted to the latch 542 during the reset time.

Referring to FIG. 5, when a normal display operation is performed and a frequency of the data clock signal HCLK suddenly changes in the data input section of the j-th pixel row, the DOS window is displayed on the full screen. In the case of enlarging, in the case of enlarging to the full screen during the game, the reset section T1 is started).

During the reset period T1, the data driving integrated circuits IC1, IC2,..., And ICk convert abnormal output image signals into analog data voltages and output the corresponding data lines D ₁ -through the output terminals Y1, Y2,. D _m )

In this case, the signal controller 600 outputs the high level gate clock signal CLK to the gate driver 400 during the reset period T1. The gate driver 400 shifts the j-th gate signal Vg _j to the gate-on voltage Von in synchronization with the rising edge of the gate clock signal CLK and supplies it to the pixel PX.

Since the high level of the gate clock signal CLK is maintained during the reset period T1, the gate driver 400 maintains the j-th gate signal Vg _j as the gate-on voltage Von during the reset period T1. The next gate signal Vg _{j + 1} is not output. Therefore, when the reset period T1 is 5H, the j-th gate signal Vg _j maintains the gate-on voltage Von for 5H, and the j + 1 th to j + 4 th gate signals Vg _{j + 1} − Vg ₊₄ maintains the gate off voltage Voff, which is the level of the previous frame. Therefore, even when the abnormal data voltage is output to the data lines D1 -Dm for 5H, the switching element Q of the pixel PX remains turned off according to the gate off voltage Voff, so that the pixel PX is displayed abnormally. Keep the display of the previous frame without doing.

In this case, when the gate driver 400 receives the output enable signal OE that defines the duration of the gate-on voltage Von, the gate signal Vg _j is at the rising edge of the output enable signal OE. Since masking is performed, the output enable signal OE is maintained at a high level during the reset period T1.

Next, when the delay circuit of the data driver 400 is reset, a fail safe section T2 is started. During the emergency safety period T2, the signal controller 600 outputs the black normal output image signal to the data driving integrated circuits IC1, IC2,..., ICk, and the data driving integrated circuits IC1, IC2,..., ICk. Converts the black normal output video signal to an analog normal data voltage.

In addition, the gate clock signal CLK transitions to the low level according to the signal controller 600, and has a clock signal of the same cycle as before. Therefore, at the next rising edge of the gate clock signal CLK, the j + 1th gate signal Vg _{j + 1} has the gate-on voltage Von and the pixel PX along the j + 1st gate line Gj + 1. Is passed on. The switching element Q of the pixel PX is turned on according to the gate-on voltage Von of the _{j +} 1th gate signal Vg _{j + 1} to receive a normal data voltage. The pixel PX displays black by varying the arrangement of liquid crystals according to the normal data voltage.

This operation is sequentially performed in the pixels PX forming a row during the emergency safety period T2, and the pixels PX display black. The signal controller 600 outputs an output image signal DAT ₁ -DAT _k for displaying an image again to the data driving integrated circuits IC1, IC2,..., ICk after the emergency safety section T2 ends, and drives the data. The integrated circuits IC1, IC2, ..., ICk transmit the output image signals DAT ₁ -DAT _k according to the changed frequency.

Accordingly, the abnormal image may be prevented from being displayed by not applying the abnormal data voltage due to the sudden frequency change of the data clock signal HCLK to the pixel PX.

In the above description, the gate signals Vg ₁ -Vg _m are synchronized on the rising edge of the gate clock signal CLK. However, the gate signals Vg ₁ -Vg _m are synchronized on the falling edge of the gate clock signal CLK. In the case of synchronization, the gate clock signal CLK may be fixed to the low level during the reset period T1.

Hereinafter, a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIGS. 6 and 7.

6 is a block diagram of a gate driver 400 of a liquid crystal display according to another exemplary embodiment. FIG. 7 is a signal waveform diagram illustrating an operation of the liquid crystal display including the gate driver 400 of FIG. 6. to be.

Referring to FIG. 6, the gate drivers 400 of the liquid crystal display according to another exemplary embodiment of the present invention are arranged in a line and have a plurality of stages 410 connected to the gate lines G ₁ -G _n , respectively. As the shift register to be included, the scan start signal STV, the initialization signal INT, the plurality of clock signals CLK1 and CLK2 and the gate off voltage V _off are input.

Each stage 410 includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output terminal ( OUT1) and carry output terminal OUT2. However, the last dummy stage does not have the reset terminal R and the frame reset terminal FR.

In each stage, for example, the set terminal S of the j-th stage ST _j , the carry output of the front stage ST _j-1 , that is, the front carry output Cout (j-1), is a reset terminal. The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1), is input to R, and the first clock signal CLK1 and the second clock are supplied to the clock terminals CK1 and CK2. The clock signal CLK2 is input, and the gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of the shift register 400 instead of the front carry output.

In addition, when the first clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST _j and the second clock signal CLK2 is input to the clock terminal CK2, (j-1) adjacent thereto. The second clock signal CLK2 is provided at the clock terminal CK1 of the first and (j + 1) th stages ST _j-1 and ST _{j + 1} , and the first clock signal CLK1 is provided at the clock terminal CK2. Is entered.

As illustrated in FIG. 7, the duty ratio of the first and second clock signals CLK1 and CLK2 may be 50%, and the phase difference between the first and second clock signals CLK1 and CLK2 may be 180 Hz.

Referring to FIG. 7, in a normal operation, each stage ST ₁ -ST _n of the gate driver 400 receives a carry signal of a previous stage and receives rising edges of the first or second clock signals CLK1 and CLK2. The gate signals Vg ₁ -Vg _{m are} sequentially shifted to the gate-on voltage Von in synchronism with. That is, the odd-numbered gate signal is synchronized with the rising edge of the first clock signal CLK1 and the even-numbered gate signal is synchronized with the rising edge of the second clock signal CLK2 to have the gate-on voltage Von.

Next, when the frequency of the data clock signal HCLK changes abruptly in the data input section of the j + 2 (j is odd) pixel row, the reset section T3 starts.

During the reset period T3, the data driving integrated circuits IC1, IC2,..., And ICk convert the abnormal output image signal into an analog data voltage and output it to the data lines D ₁ -D _m .

In this case, the signal controller 600 fixes the first clock signal CLK to a high level, and the gate driver 400 synchronizes the rising edge of the first clock signal CLK1 to set the gate-on voltage Von to j +. The pixel PX is supplied to the pixel PX through the second gate line Gj + 2. In addition, the signal controller 600 fixes the second clock signal CLK2 to a low level during the reset period T3. Therefore, the gate driver 400 maintains the _{j +} 2th gate signal Vg _{j + 2} at the gate-on voltage Von during the reset period T3 and does not output the next gate signal Vg _{j + 3} . That is, when the reset period T3 is 5H, the j + 2 th gate signal Vg _{j + 2} maintains the gate-on voltage Von for 5H, and the j + 3 th through j + 7 th gate signals Vg. _{j + 3} -Vg _{j + 7} ) maintains the gate-off voltage Voff, which is the level of the previous frame. Therefore, even when the abnormal data voltage is output to the data lines D ₁ -D _m for 5H, the pixel PX does not display abnormal display and maintains the display state of the previous frame.

Next, when the delay circuit of the data driver 500 is reset, the emergency safety section T4 is started, and the data driver integrated circuits IC1, IC2,..., And ICk receive the black normal output image signal and receive the analog normal data voltage. Convert to

In addition, since the first and second clock signals CLK1 and CLK2 have the same clock signal as the previous period, the gate driver 400 has a j + 3th gate on the next rising edge of the second clock signal CLK2. The signal Vg _{j + 3} has the gate-on voltage Von, and the pixels PX of the j + 3th row display black according to the normal data voltage.

As described above, according to the present invention, an abnormal image may be prevented from being displayed by not applying an abnormal data voltage to a pixel due to a sudden change in the frequency of the data clock signal.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A plurality of pixels, A gate driver which sequentially applies a gate-on voltage to the pixel in synchronization with a gate clock signal, and A data driver which receives data in synchronization with a data clock signal, converts the data into an analog data voltage, and applies the data to the pixel. Including; Fixing the state of the gate clock signal from when abnormal data according to the change of the data clock signal is transmitted to the data driver until normal data is transmitted to the data driver. Display device. In claim 1, And when the gate on voltage is synchronized at the rising edge of the gate clock signal, fixing the gate clock signal to a high level from when the abnormal data is transmitted until the normal data is transmitted. In claim 1, And when the gate on voltage is synchronized at the falling edge of the gate clock signal, fixing the gate clock signal to a low level from when the abnormal data is transmitted until the normal data is transmitted. The method of claim 2 or 3, And the pixel is black for a predetermined period according to the normal data. In claim 4, The gate driver receives an output enable signal for adjusting the holding time of the gate-on voltage, Fixing the state of the output enable signal from when the abnormal data is transmitted until the normal data is transmitted. Display device. In claim 4, The data driver includes a plurality of data driver circuits, The data driving circuit receives a plurality of data from the data driving circuit of the previous stage, selects one data from the received data, and transfers the remaining unselected data to the data driving circuit of the subsequent stage. Display device. In claim 6, And the data driver circuit includes a delay circuit to reorder the data according to the data clock signal.

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