KR20070077329A - Method for forming algorithm of auto defect classification - Google Patents

Abstract

A method of forming automatically defect classifying algorithm is provided to decrease a node length of decision tree and improve the precision when defect of interest is detected. Defect parameters of each defect are received from a defect analyzer(S10), and then are classified into major defects and minor defects by manual operation(S12). Two of the defect parameters are selected to plot 2-dimensional graphs for classifying the major defect and the minor defect(S14). The 2-dimensional graph for easily classifying the major defect and the minor defect is selected from the 2-dimensional graphs(S16). The 2-dimensional graph is processed to display an image, thereby forming a map differently displaying a major defect region and a minor defect region. A rule of decision tree is created to contain all major defect regions(S20).

Description

Method for forming algorithm of auto defect classification

1 is a flowchart illustrating a method for generating an automatic defect classification algorithm according to an embodiment of the present invention.

2 briefly illustrates an example of a defect analysis data table output from a defect analysis apparatus.

3 shows a part of the result of plotting the two-dimensional graph using an auto ranking program.

4A is a two-dimensional graph of a defect FV.

FIG. 4B is a map generated by image processing of the 2D graph shown in FIG. 4A.

5 is a flowchart of an automatic defect analysis algorithm according to an embodiment of the present invention.

6 is a block diagram showing a configuration of equipment for classifying defects using the ADC algorithm.

The present invention relates to a method for generating an automatic defect classification algorithm. More specifically, the present invention relates to a method of generating an automatic defect classification algorithm for accurately classifying defects occurring in a semiconductor manufacturing process.

Various defects are generated on the wafer during the semiconductor fabrication process. Since the defect may affect the operation of the semiconductor device to reduce the yield of the semiconductor device, the defects are typically inspected and monitored before and after each unit process.

In recent years, as the performance of a device for analyzing a defect has developed very rapidly, even a minute defect can be easily detected using the defect analysis device. On the other hand, however, defects or noise defects (usually called nuisance defects) that do not affect the operation of the semiconductor device are detected on the other hand, so whether the defects on the wafer are actually important defects or what kind of defects are detected. It is becoming harder to figure out. Therefore, it is required to accurately classify only the critical defects (commonly referred to as DOI, defect of interest) that have a great influence on the operation of the semiconductor device from the defects detected by the analysis apparatus.

Typically, a method as described below is used to classify defects.

First, the defect analysis apparatus generates an image of a defect, and outputs parameter information of a defect called a feature vector (hereinafter referred to as FV) for each defect image. The FVs are classified into a plurality of defect analyzing apparatuses (ie, FV1 to FVn), and each FV represents a defect type, size, intensity, size, and the like. In addition, each FV is represented by a number between 0 and 1 to indicate the information of each defect.

The defects are automatically classified (hereinafter, ADC, Auto Defect Classification) using various algorithms for analyzing the distribution characteristics of the FV. Examples of ADC algorithms currently used include the method using the Nearest Neighbor Algorithm (hereinafter NN), the algorithm using the Decision Tree method (hereinafter DT), the algorithm using the Finger Print method, and the Kullback Leibler Boosting Algorithm (hereinafter KLB). There is this.

However, since the algorithm used to classify the defects differs according to the company manufacturing each defect analysis apparatus, the accuracy of the algorithm varies depending on the type of the defect analysis apparatus. In addition, even using the algorithm, it is not easy to accurately classify only a specific defect corresponding to the major defect (DOI). In addition, since the ADC algorithm is designed to classify defects based on a probability concept, a large difference in accuracy of the ADC occurs depending on a wafer in which a major defect is generated and a wafer in which a major defect is hardly generated.

Specifically, an algorithm such as Nearist Neighbor does not have a specific pattern and unilaterally proceeds with the ADC according to the defect distribution of the surroundings, thus eliminating the user's choice, and the distribution of accuracy is too wide. On the other hand, in the decision tree type algorithm, when the defects are concentrated in a specific FV region, each node becomes too deep, so it takes a long time to classify the defects, and there is a problem that the discrimination power decreases because the number of reference DOIs is small. .

In the case of algorithms that statistically run ADCs such as Finger Print and Nearest Neighbor, n-dimensional plotted areas are plotted by plotting n-dimensional FVs and manually classifying them when n FVs. Since the defects are classified by statistically calculating, the accuracy of the DOI is reduced by including the FV, which has a low discrimination of DOI, in the n dimension. In the case of a unit process having a plurality of DOI defects, accuracy is reduced by classifying defects at once in n-dimensions.

Accordingly, an object of the present invention is to provide a method for generating an automatic defect classification algorithm capable of classifying DOI accurately in a short time.

As a method of generating an automatic defect classification algorithm according to an embodiment of the present invention for achieving the above object, first, defect parameters of each defect are received from a defect analysis apparatus. The defects are manually distinguished from the defect parameters into major defects (DOIs) and non-DOI defects. Two of the defect parameters are selected to plot two-dimensional graphs so that the major defect and the noncritical defect are distinguished from each other. Among the two-dimensional graphs, a two-dimensional graph that can easily classify the major defects and non-critical defects is selected. The two-dimensional graph is imaged to form a map in which the critical defect area in which the major defect is located and the non-critical defect area in which the non-critical defect are located are displayed differently. The defect classification algorithm is completed by generating a decision tree rule to include all the critical defect areas in the map.

Each plotting the two-dimensional graphs may be performed statistically using any one algorithm selected from the group consisting of statistical logic called 2-D Piecewise Linear, KLBoosting Logic, and image processing algorithms. This can be done using an auto ranking program that plots the mean and range in the order in which they are best sorted.

Before generating the map, the method may further include selecting a section having a high defect discrimination power using any one algorithm selected from a group consisting of algorithms such as image processing, KLBoosting, and manual region setting.

The rule of the decision tree is generated to be classified as a critical defect when there is a defect in the critical defect area and as a non-critical defect when there is a defect in the remaining areas.

The user can directly select a two-dimensional graph that can easily distinguish the critical defect and the non-critical defect.

The method may further include checking accuracy and purity of the generated decision tree.

As described above, by using a novel ADC algorithm using an image processing technique, it is possible to improve the accuracy and purity at the time of DOI detection while reducing the number of separated nodes and the depth of the rule. In addition, it is possible to further improve accuracy by classifying defects by selecting the most discriminating FV floating region for the user to judge.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a method for generating an automatic defect classification algorithm according to an embodiment of the present invention.

Referring to FIG. 1, in order to generate an automatic defect classification algorithm, first, data obtained by analyzing a defect in a defect analyzing apparatus is obtained. (S10) Specifically, the defect analyzing apparatus generates an image of a defect and an image of each defect. For each function, parameter information of a defect called a feature vector (hereinafter, FV) is output. The FV data is then obtained to generate an automatic defect classification algorithm. The FV is classified into a plurality of defect analyzing apparatuses (that is, FV1 to FVn, n is a natural number larger than 1), and each FV represents a defect type, size, intensity, size, and the like. In addition, each FV is represented by a number between 0 and 1 to indicate the information of each defect.

2 briefly illustrates an example of a defect analysis data table output from a defect analysis apparatus.

Each defect is classified into bin 1 (BIN1) or bin 2 (BIN2) by the operator directly confirming the defect analysis data table as shown in FIG. Here, bin 1 (bin1) is a major defect (DOI) that may cause a malfunction or reliability failure in a semiconductor device, and bin 2 is a non-DOI that does not cause a malfunction or reliability failure in a semiconductor device. Means.

Hereinafter, the defect classification method by the operator will be described in more detail.

Referring to FIG. 2, in the defect analysis table, FV1 and FV3 are abnormally low in the case of defect 1 when compared to other defects. In addition, for defect 5, FV2 is abnormally high and FV3 is abnormally low compared to other defects. As described above, the operator can accurately classify each defect as bin 1 or bin 2 by comprehensively determining whether the FV values output from each defect are greater than or equal to a set range.

However, it is difficult to manually perform the task of classifying each defect into bin 1 or bin 2 by examining defect analysis data continuously output during the manufacture of the semiconductor device. Therefore, there is a need for an algorithm to detect this automatically and accurately and quickly.

In order to generate the automatic defect analysis algorithm described above, it is necessary to know whether each defect generated in the sample wafer is exactly bin 1 or bin 2. Therefore, it is required to classify each defect accurately by the user's manual operation as mentioned above.

The obtained FV data and the result of manually classifying the defects are combined and converted into a text file (txt file) in a form compatible with each defect detection apparatus.

Plot two-dimensional graphs, each of which is selected from each of the FV data, with X and Y axes, respectively. (S12) In this case, the defects to be dotted can be distinguished from bin 1 or bin 2. Plot two-dimensional graphs. As the number of FVs provided from the defect analysis device increases, the number of graphs plotted in the 2D also increases. Each graph is a defect distribution diagram of two-dimensional FV.

Plotting in two dimensions using the selected two FVs may be performed using an auto ranking program. The auto ranking program utilizes one of algorithms such as statistical logic called 2-D Piecewise Linear, KLBoosting Logic, image processing, etc. The FVs are displayed two-dimensionally in the best sorted order.

3 shows a part of the result of plotting the two-dimensional graph using an auto ranking program.

In FIG. 3, a symbol Δ is a defect classified as bin 1, and a symbol ○ is a defect classified as bin 2.

Next, the user selects a graph that can empirically distinguish the bin 1 and bin 2 empirically from the two-dimensionally plotted graphs. (S16) In some cases, a rank is determined in the auto ranking program. You can also automatically select the graph displayed in 1 (rank-1).

In the selected graph, one of the algorithms such as image processing, KLBoosting, manual region setting, etc. may be used to select a section having a high defect discrimination power.

Image processing is performed such that the bin 1 and the bin 2 are divided in the selected sections, thereby generating a map. (S18)

4A is a 2D graph, and FIG. 4B is a map generated by image processing of the 2D graph shown in FIG. 4A.

Referring to FIG. 4B, a portion displayed in red corresponds to bin 1 and a portion displayed in light green corresponds to bin 2. In other words, the area corresponding to the bin 1 becomes a major defect (DOI) area.

After that, based on the DT algorithm, DT is completed while continuously dividing the DT rules so that all of the critical defect areas are included in the map generated by the image processing.

A typical DT algorithm draws conclusions by including rules 100 which are the respective criterion and continuously judging whether the rules are met. That is, in the case of using the DT algorithm, whether each defect corresponds to bin 1 or bin 2 depends on whether each defect satisfies the rules. Therefore, when the bin 1 and the bin 2 exist in a similar area, a lot of rules are required to accurately classify the defects, the root of DT is increased, and the number of the separated nodes is also increased. It becomes very long. Therefore, the time required for classifying the defects becomes long.

Moreover, in the case of the DT algorithm, since each rule is divided into yes or no, it is divided into only an area larger or smaller than a reference line which is a straight line corresponding to each rule in the graph. Therefore, since it is not divided into sections of a specific region through one rule, it is highly likely that unwanted defects are included in a region larger or smaller than the baseline, and thus accuracy may be lowered.

On the other hand, according to the present embodiment, the criterion of determination in each of the above rules is not the reference line but whether the defect exists in the critical defect area. The critical defect area includes all independent areas in which bin 1 is located in the map. Hereinafter, each of the independent areas is referred to as first to n-th areas 120, 122, 124, and 130.

Hereinafter, the algorithm of the present invention based on the DT algorithm will be described in more detail. 5 is a flowchart of an automatic defect analysis algorithm according to an embodiment of the present invention.

4B and 5, a rule for distinguishing whether a defect exists in the first region 120 at the first route is created. In this case, the defect present in the first region 120 is classified as bin 1.

Next, when the defect is not located in the first region 120, a rule for distinguishing whether the defect belongs to the second region 122 is created. In this case, if the defect is located in the second region 122, it is classified as bin 1.

Subsequently, when the defect is not located in the second region 122, a rule for distinguishing whether the defect belongs to the nth region 130 is created. In this case, if the defect is located in the n-th region 130, it is classified as bin 1, and if the defect is not located in the n-th region, it is classified as bin 2.

As described above, each rule for checking whether there is a defect in the first to n-th regions 120, 122, 124, and 130 is prepared, and a check is made on the wafer by checking whether the rule is satisfied. Among the defects, bin 1 corresponding to the major defect is classified.

The completed DT rule is then a recipe for automatically classifying defects in wafers used in semiconductor manufacturing processes.

In the case of classifying defects as described above, unlike the conventional DT algorithm, each region classified as bin 1 may be expressed in one tree rule by imaging the distribution of the FV. As a result, the depth of the rule can be greatly reduced, and the number of defects sampled in the area classified as bin 1 can be increased to increase purity.

When the final DT rule is completed, it is necessary to check the accuracy and purity of the ADC for the rule to confirm whether the DT rule is applicable in semiconductor manufacturing. In other words, beforehand, the operator compares the result of manually classifying the bin 1 and the bin 2 with the result of automatically classifying the bin 1 and bin 2 using the DT rule.

Here, the accuracy of the ADC indicates how accurately the bin 1 is classified, and is calculated as a real bin 1 / real bin 1 × 100 (%) value among the classified bin 1. In addition, the purity of the ADC indicates how much of the actual bin 1 is included in the automatically classified bin 1, and is calculated as the actual bin 1 / classified bin 1 × 100 (%) value of the classified bin 1.

Table 1 is an example of data that classifies defects and verifies the results using an ADC algorithm according to an embodiment of the present invention.

In Table 1, the classification ID in the X direction represents a real bin and the classification ID in the Y direction represents a bin by ADI according to an embodiment of the present invention.

TABLE 1

Vienna by ADI 1 Bin 2 by ADI Sum water Real Bin 1 175 16 191 91% (175/191 × 100) Real Bin 2 43 406 451 90% (406/451 × 100) 218 422 642 accuracy 80% (175/218 × 100) 96% (406/422 × 100)

As shown in Table 1, when the defects are automatically classified using another ADC algorithm in one embodiment of the present invention, accuracy and purity are more than 80%, and thus, they can be sufficiently applied in semiconductor manufacturing.

By storing the final DT as an ADC recipe through the above process, a new ADC algorithm is generated.

6 is a block diagram showing a configuration of equipment for classifying defects using the ADC algorithm.

Referring to FIG. 6, a defect classification method using the ADC algorithm will be described.

First, the defect analysis device 150 analyzes a defect to generate an FV.

The generated FV is transmitted to the ADC manager (Manager 160) and changed into a text file (txt file), which is a format compatible with all equipment. Thereafter, the ADC is executed by selecting a recipe set-uo by the method described above. That is, the defects doped in the two-dimensional graph of each FV are classified into bin 1 or bin 2 using the DT rule included in the recipe. When the ADC is executed as above, each defect is divided into bin 1 or bin 2 and stored in the ADC database.

In addition, the data divided into bin 1 or bin 2 is output to the ADC data output unit and transmitted in real time to the control unit of the defect analysis apparatus. The data transmitted to the controller may be used as defect analysis data. In addition, when the transmitted defect map and the defect information are determined and out of a predetermined spec, interlock is performed to interrupt the operation of the process facility.

As described above, defect monitoring can be performed, so that processes and process facilities having a high occurrence frequency of defects can be known, thereby contributing to improvement in yield of semiconductor devices.

As described above, according to the present invention, a novel ADC algorithm using an image processing technique can be generated. In addition, by using the above algorithm in classifying defects occurring in the semiconductor manufacturing process, it is possible to improve the accuracy and purity at the time of DOI detection while reducing the length of the node of DT. In addition, it is possible to classify defects more accurately by selecting the most discriminating FV floating region for the user to judge. As described above, by accurately classifying DOIs, it is possible to identify defects generated in the substrate and to cope with them quickly, so that the yield improvement and the reliability of the semiconductor device can be expected.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to vary the present invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that modifications and variations can be made.

Claims (6)

Receiving defect parameters of each defect from a defect analyzing apparatus; Manually dividing the defects into critical and noncritical defects from the defect parameters; Selecting two of the defect parameters and plotting two-dimensional graphs so that the major defect and the noncritical defect are distinguished from each other; Selecting a two-dimensional graph that can easily classify the major defect and the non-critical defect among the two-dimensional graphs; Image-processing the two-dimensional graph to form a map in which the critical defect area in which the major defect is located and the non-critical defect area in which the non-critical defect are located are differently displayed; And And generating a rule of a decision tree so that all of the critical defect areas are included in the map. The method of claim 1, wherein each of the two-dimensional graphs is plotted using any one selected from the group consisting of statistical logic called 2-D Piecewise Linear, KLBoosting Logic, and image processing algorithms. A method for generating an automatic defect classification algorithm, comprising using an algorithm to plot statistically the average and the range in the best order. The method of claim 1, further comprising, before generating the map, selecting a section having a high defect discrimination power using any one algorithm selected from a group consisting of algorithms such as image processing, KLBoosting, and manual region setting. Automatic defect classification algorithm generation method characterized in that. The automatic defect classification of claim 1, wherein the rule of the decision tree is generated to be classified as a critical defect when there is a defect in the critical defect area, and classified as a non-critical defect when there is a defect in the remaining areas. Algorithm generation method. The method of claim 1, wherein the user selects a two-dimensional graph that can easily distinguish the major defect and the non-critical defect. 2. The method of claim 1, further comprising the step of checking the accuracy and purity of the generated decision tree rules.

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