KR20070076923A - Method and apparatus for estimating frame synchronization - Google Patents

Abstract

A method and an apparatus for estimating frame synchronization are provided to correct phase estimation errors generated by a frequency offset or Doppler transition. An apparatus for estimating frame synchronization includes a phase estimation unit(10), an inner product calculation unit(20), and a frame synchronization estimation unit(30). The phase estimation unit(10) obtains a phase shift of a mid amble code(MA) and a down link synchronization code(SYNC DL code) included in each sub frame from received signals transmitted from a base transceiver station by using a reference signal. The inner product calculation unit(20) calculates a complex inner product of a phase vector for a phase shift obtained from a reference vector for Phase Quadruple(S1) and four consecutive sub frames. The frame synchronization estimation unit(30) estimates the frame synchronization.

Description

Method and apparatus for estimating frame synchronization {method and apparatus for estimating frame synchronization}

1 is a flowchart illustrating a cell search process according to the prior art,

2 illustrates a format of a downlink subframe of a 3GPP TDD LCR system.

3 is a functional block diagram of a preferred embodiment of a frame synchronization estimation apparatus according to the present invention;

4 is a detailed configuration diagram of the phase estimation unit of FIG. 3;

5 is a detailed block diagram of the inner product calculation unit of FIG. 3.

The present invention relates to a frame synchronization estimation method and apparatus, and more particularly, to a downlink frame synchronization estimation method and apparatus in a terminal of a mobile communication system.

In the TD-SCDMA system, the UE searches for a downlink sync code (SYNC-DL), a basic midamble code, a scrambling code, a frame sync, broadcast channel (BCH) information, and a chip. As a process of acquiring chip timing information and the like, it is generally performed through the following four steps. 1 is a flowchart illustrating a cell search process according to the prior art.

1) Initial Synchronous Search Process (Search for DwPTS)

The UE estimates initial synchronization in a downlink pilot time slot (DwPTS) using 32 possible SYNC-DL codes without knowing cell information to be searched. Through this process, the UE must find the SYNC-DL code and the timing synchronization point that are used in the cell among the 32 SYNC-DL codes.

2) Basic midamble and scrambling code identification

Since the DwPTS code found in step 1) corresponds to one code group having four basic midambles, the UE finds a basic midamble being used in a cell among four basic midambles. Since the basic midamble is associated with the scrambling code, the scrambling code can be found by looking for the basic midamble.

3) Control multi-frame sychronization

The UE finds Master Information Blocks (MIBs) of BCH multi-frames from QPSK phase modulation of DwPTS for the P_CCPCH midamble.

4) Read the BCH

The terminal reads the BCH using the retrieved MIB to obtain BCH information.

The present invention relates to a frame synchronization acquisition process, which is a third step in the cell search process. Hereinafter, the frame synchronization acquisition process according to the prior art will be described.

In the TD-SCDMA system, since the BCH has a transmission time interval (TTI: 20 ms), the UE should find the presence or absence of the BCH in the next frame and the start position of the 20 ms TTI. The base station performs phase modulation based on the phase of the first time-slot midamble when modulating DwPCH to inform the start point of the BCH, and the value of the phase modulation remains the same for one subframe. do. Four phase modulation values obtained during four consecutive subframes are called 'Phase Quadruple', and there are two 'Phase Quadruples' of S1 and S2. Table 1 shows what the two 'Phase Quadruple' means. In Table 1, a Primary-Common Control Physical Channel (P-CCPCH) is a physical channel to which a BCH, which is a transport channel, is mapped.

Case Phase quadruple Meaning S1 135 °, 45 °, 225 °, 135 ° P-CCPCH exists in the next four subframes S2 315 °, 225 °, 315 °, 45 ° P-CCPCH does not exist in the next four subframes

In the prior art, after determining 'Phase Quadruple' for four subframes and determining whether it corresponds to S1, if it is determined to be S1, it is determined that P-CCPCH exists from the next subframe, and that Start receiving.

That is, the process of estimating 'Phase Quadruple' includes estimating a phase modulation value of a downlink sync code for each subframe, which is performed as follows. First, the phase value of the received midamble code and the phase value of the downlink sync code are estimated. Next, after obtaining the correlation between the estimated phase values of the two codes, 'Arctangent' is taken to obtain the modulated phase of the downlink sync code.

Thereafter, 'Phase Quadruple', which is a modulated phase value for each of the four subframes obtained by the above method, is compared with the phase values of S1 and S2 in Table 1. As a result of the comparison, if the obtained 'Phase Quadruple' corresponds to S1, the BCH is received in the next four subframes, and if it is not S1, the BCH does not exist in the next four subframes. In this case, the process of estimating 'Phase Quadruple' is repeated.

However, in the case of estimating the modulated phase value of the downlink sync code using 'Arctangent' according to the prior art as described above, 'Arctangent' operation is generally referred to as a Look Up Table for efficient implementation. Replaced by table mapping. Therefore, since a large amount of table values must be stored in a predetermined memory for accurate operation, there is a problem of increasing an excessive amount of memory.

In addition, since the modulated phase value of the downlink sync code may be distorted even by the frequency offset, it is difficult to calculate the correct phase modulation value by the conventional method using only the absolute phase difference.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to provide a frame synchronization estimation method and apparatus capable of estimating frame synchronization without excessive memory increase in a mobile communication system. will be.

Another object of the present invention is to provide a frame synchronization estimation method and apparatus capable of correcting a phase estimation error caused by a frequency offset.

The present invention discloses a method and apparatus for estimating frame synchronization in a mobile communication system using a correlation value between a received signal and a reference vector using a reference vector for a phase. Also disclosed are frame synchronization estimation methods and apparatuses that take into account all possible phase modulation possibilities and frequency offsets.

In one aspect of the present invention, the frame synchronization estimation method according to the present invention, in the downlink frame synchronization estimation method in a terminal of a mobile communication system, for M consecutive subframes transmitted from a base station, Obtaining a phase difference between a downlink sync code and a midamble code included in each subframe, and obtaining a reference vector, which is a vector representation of M reference phase values, and the M consecutive subframes. Calculating a complex dot product of the phase vector, which is a vector representation of the phase differences, and estimating frame synchronization using the calculated dot product.

In another aspect of the present invention, a downlink frame synchronization estimation apparatus in a mobile communication system according to the present invention includes a phase estimating unit for acquiring a phase difference between a downlink sync code and a midamble code included in a subframe transmitted from a base station; Compute a complex dot product of a reference vector, a vector representation of M reference phase values, and a phase vector, a vector representation of phase differences obtained for M consecutive subframes obtained by the phase estimator, And a frame synchronization estimator for estimating frame synchronization using the calculated inner value.

The construction, operation and other features of the present invention will be readily understood by the preferred embodiments of the present invention described below with reference to the accompanying drawings.

2 illustrates a format of a downlink subframe of a 3GPP TDD LCR system. In the 3GPP TDD LCR system, there are 32 reference signal SYNC-DLs of downlink sync codes, and each chip has a length of 64 chips. As shown in FIG. 2, the midamble code MA of the P-CCPCH is included in the first downlink time slot Ts0, and the downlink sync code SYNC-DL is the first downlink of the subframe. It is located after the time slot Ts0. The DwPTS consists of a guard period of 32 chips and a SYNC-DL code of 64 chips, and one of 32 SYNC-DL codes is selected and used for each cell.

3 is a functional block diagram of a preferred embodiment of the frame synchronization estimation apparatus according to the present invention. Referring to FIG. 3, the apparatus for estimating frame synchronization uses a received signal transmitted from a base station to determine a phase shift between a midamble code MA and a downlink synchronization code SYNC DL code included in each subframe. A phase estimator (10) obtained by using P, a reference vector, which is a vector representation of 'Phase Quadruple' S1, and a phase difference obtained by four phase subframes by the phase estimator (10). And a dot product calculating section 20 for calculating a complex dot product of the phase vector, which is a vector representation of the fields, and a frame sync estimating section 30 for estimating frame sync using the calculated dot product.

4 is a detailed block diagram of the phase estimator 10. Hereinafter, the downlink sync code SYNC when the phase of the midamble code MA included in the first downlink timeslot Ts0 of each subframe transmitted from the base station by the phase estimator 10 is referred to A process of obtaining a phase modulation value of DL code, that is, a phase difference between the downlink sync code and the midamble code will be described in detail with reference to FIG. 4.

, 수신신호의 미드앰블 코드를

, 단말이 이미 알고 있는 기준신호의 하향링크 동기 코드를

, 기준신호의 미드앰블 코드를

로 표시하면, 수신신호의 i번째 하향링크 동기 코드 및 미드앰블 코드는 각각 다음의 수학식 1 및 수학식 2와 같이 정의할 수 있다. 여기서, i는 하향링크 동기 코드와 미드앰블 코드의 칩 단위 인덱스이다.In the nth subframe, the downlink sync code of the received signal is

, The midamble code of the received signal

The downlink synchronization code of the reference signal

, The midamble code of the reference signal

In this case, the i-th downlink synchronization code and the midamble code of the received signal may be defined as Equation 1 and Equation 2, respectively. Here, i is a chip unit index of the downlink sync code and the midamble code.

은 n번째 서브프레임의 하향링크 위상 변조값이고,

는 노이즈(noise) 성분이며, h_i는 채널 성분을 나타내는 채널 계수(channel coefficient)이다.Where L is the length of the multipath channel (unit is chip),

Is the downlink phase modulation value of the nth subframe,

Is a noise component and h _i is a channel coefficient representing a channel component.

와 기준신호

와의 자기 상관을 각각 구한다. 이를 수학식으로 표현하면 각각 다음의 수학식 3 및 수학식 4와 같다. 여기서, h_o는 동기가 정확히 맞았을 때의 채널 성분이고,

,

은 무시할 수 있을 정도로 작은 값이라 가정한다.In order to extract the channel component and the phase modulation component, the downlink sync code correlation value detection module 11 and the midamble code correlation value detection module 12 receive the received signal.

And reference signal

Obtain each autocorrelation with. When this is expressed as an equation, Equation 3 and Equation 4, respectively. Where h _o is the channel component when the synchronization is correct,

,

Is assumed to be small enough to be ignored.

을 정규화(normalization)시키면 각각 다음의 수학식 5 및 수학식 6과 같다.Autocorrelation values obtained by equations (3) and (4) to remove channel components that vary in each subframe

Normalized to Equation 5 and Equation 6, respectively.

에 대한 정규화는, 하향링크 동기코드 상관값 검출 모듈(11) 및 미드앰블 코드 상관값 검출 모듈(12)에서 각각 수행될 수 있고, 하향링크 동기 코드 및 미드앰블 코드 상관값 검출 모듈(13)에서 수행될 수도 있다. 또는, 하향링크 동기코드 상관값 검출 모듈(11) 및 미드앰블 코드 상관값 검출 모듈(12)과, 하향링크 동기 코드 및 미드앰블 코드 상관값 검출 모듈(13) 사이에 마련되는 별도의 정규화 계산부(미도시)에 의해 수행될 수도 있다.At this time,

Normalization with respect to the downlink sync code correlation value detection module 11 and the midamble code correlation value detection module 12 may be performed respectively, and the downlink sync code and midamble code correlation value detection module 13 may be May be performed. Alternatively, a separate normalization calculator provided between the downlink sync code correlation value detection module 11 and the midamble code correlation value detection module 12 and the downlink sync code and midamble code correlation value detection module 13. It may be performed by (not shown).

의 상호 상관을 다음의 수학식 7에 따라 구한다.The downlink sync code and midamble code correlation value detection module 13 calculates a phase difference between the downlink sync code and the midamble code of the received signal.

The cross-correlation of is calculated according to the following equation.

및

는 수학식 3 및 수학식 4에서와 마찬가지로, 무시할 수 있을 정도로 작은 값이라 가정하면, 수신신호의 하향링크 동기코드와 미드앰블 코드 사이의 위상차 p_n이 산출된다.

And

As in Equation 3 and Equation 4, assuming that the value is negligibly small, the phase difference p _n between the downlink sync code and the midamble code of the received signal is calculated.

By the above-described method, the phase estimator 10 calculates the phase difference between the downlink sync code and the midamble code included in each subframe for four consecutive subframes, 20)

와, 상기 위상 추정부(10)에 의해 구해진 네 개의 연속적인 서브프레임의 위상차들의 벡터 표현인

의 복소 내적을 구한다. 상기 내적 산출부(20)에서 구해진 내적 값을 정규화하면 다음의 수학식 8과 같이 표현된다.5 is a detailed configuration diagram of the inner product calculation unit 20, the inner product calculation unit 20 is a coordinate representation of the vector form of 'Phase Quadruple' S1 (135 °, 45 °, 225 °, 135 °)

And a vector representation of phase differences of four consecutive subframes obtained by the phase estimating unit 10.

Find the complex dot product of. When the inner product value obtained by the inner product calculating unit 20 is normalized, Equation 8 is expressed as follows.

 The frame synchronization estimator 30 estimates frame synchronization by comparing the calculated inner value with a preset threshold. A method of determining the threshold value used by the frame synchronization estimator 30 will now be described in detail.

To determine the threshold, we can consider all cases where 'Phase Quadruple' S1, S2 can come. Assuming that there may be both S1 and S2 because the frame synchronization is not known, the number of cases where four consecutive phase differences can have is 14 in total as shown in Table 2. Here, for example, S1 + S2 means a case where S2 comes after S1, and in Table 2, 'Offset' means a frame synchronization error in units of subframes. That is, when 'Offset' is 1 in S1 + S2, it means four consecutive 'Phase Quadruple's consisting of S1's first' Quadruple 'and starting from the second' Quadruple 'of S1.

As shown in the preceding q , each of the coordinates of the vector phase having (1, -1) as an element is converted, and then the S1 vector and the complex dot product are obtained and normalized to have the values shown in Table 2.

case offset phase quadruple A real part Imaginary part Absolute value of dot product Frame sync is correct S1 0 135 °, 45 °, 225 °, 135 °

0

S2 0 315 °, 225 °, 315 °, 45 °

0

Frame sync is not correct  S1 + S2 One 45 °, 225 °, 135 °, 315 °

4 2 225 °, 135 °, 315 °, 225 ° 0

3 135 °, 315 °, 225 °, 315 °

2  S2 + S2 One 225 °, 315 °, 45 °, 315 °

0

2 315 °, 45 °, 315 °, 225 ° 0

3 45 °, 315 °, 225 °, 315 ° 0

 S1 + S1 One 45 °, 225 °, 135 °, 135 ° 0

2 225 °, 135 °, 135 °, 45 ° 0 0 0 3 135 °, 135 °, 45 °, 225 ° 0

 S2 + S1 One 225 °, 315 °, 45 °, 135 ° 0 0 0 2 315 °, 45 °, 135 °, 45 ° 0

3 45 °, 135 °, 45 °, 225 °

2

로서 가장 큰 값을 가지고, 두 번째로 큰 값은

이다. 따라서,

와

사이에 존재하는 임의의 값을 임계값으로 결정할 수 있다. 특히, 실제 수신되는 신호는 잡음과 페이딩에 의해 크기가 변화될 수 있으므로, 최대 우도 검출(Maximum Likelihood Detection) 방식을 적용하여, 임계값을

으로 결정할 수 있다. 이에 따라, 내적의 실수부의 크기가

이상인 경우에는 S1을 수신한 것으로 볼 수 있게 된다. Referring to Table 2 above, when the real part of the dot product is S1,

Has the largest value, and the second largest value

to be. therefore,

Wow

Any value existing in between can be determined as the threshold. In particular, since the actual received signal may change in size due to noise and fading, the maximum likelihood detection method is used to apply a threshold value.

Can be determined. Accordingly, the size of the real part of the inner product

In the case of abnormality, it can be seen that S1 has been received.

In some cases, for example, when there are 'Phase Quadruple' different from 'Phase Quadruple' S1 and S2 as in the 3GPP TDD LCR system, the threshold value may be determined using the imaginary part of the inner product.

On the other hand, if a frequency offset exists, a phase difference occurs between the downlink sync code and the midamble code due to the frequency offset rather than the 'Phase Quadruple'. In addition, when the frequency offset changes in time due to the operation of AFC (Auto Frequency Control), the estimated phase difference may occur differently in every subframe. Here, the frequency offset means a frequency difference generated by the frequency difference between the local oscillator of the base station and the terminal and the influence of the Doppler frequency in the channel. Furthermore, since the frequency offset generates sampling error in the terminal, and the error accumulates with time and causes serious degradation in reception performance, the terminal estimates the frequency offset through the AFC and continuously compensates for this.

Accordingly, in estimating frame synchronization in the frame synchronization estimator 30, a threshold value is set differently according to the presence or absence of a frequency offset, and / or the calculated internal value is compared with the set threshold value. It would be desirable to vary the method used for comparison.

For example, when the terminal estimates a frequency offset, and the estimated frequency offset is smaller than the reference value, the terminal estimates frame synchronization by comparing a real part of the first threshold value and the calculated inner product value, and the estimated frequency offset is If the reference value is larger than the reference value, the frame synchronization may be estimated by comparing the second threshold value with the absolute value of the calculated dot product.

이고, 나머지 경우 중 최대치는 4이므로, 상기에서 설명한 내적의 실수부를 이용하는 경우와 마찬가지로 최대 우도 검출(Maximum Likelihood Detection) 방식을 적용하여, 임계치를

으로 결정할 수 있다. 이로써, 내적의 절대값이

이상인 경우에 대해 S1이 수신된 것으로 볼 수 있게 된다.That is, in the case where the frequency offset exists, the method of using the absolute value of the inner product will be described since it is not possible to determine whether or not the S1 is received only by the real part of the inner value as described above. Referring to Table 2, the absolute value of the dot product when S1 is received

Since the maximum value of the remaining cases is 4, the maximum likelihood detection method is applied in the same manner as in the case of using the real part of the dot product described above,

Can be determined. Thus, the absolute value of the dot product

In the above case, it can be seen that S1 has been received.

가 발생할 수 있고, 내적의 절대값이 4일 경우에도 잡음과 페이딩에 의해 S1을 수신한 것으로 잘못 판단될 수 있는 소지가 있다. 이때에는,내적의 절대값을 이용하는 것에 부가하여, 직전에 수신된 위상 값 p_{n -1}과 'Quadruple'의 위상 값 중 어느 하나, 예를 들어, 첫 번째 값인 p_n의 위상 차이를 더 이용함으로써, 보다 정확하게 S1 수신 여부를 판단할 수 있게 된다. However, in the case of 'Phase Quadruple' S1 and S2 as in the 3GPP TDD LCR system, the absolute value of the same dot product as the case where S1 is received even when the synchronization with S1 is not matched.

May occur, and even when the absolute value of the dot product is 4, there is a possibility that it may be erroneously determined to have received S1 by noise and fading. At this time, in addition to using the absolute value of the inner product, by further using the phase difference between any one of the phase values p _{n -1} received earlier and the phase value of 'Quadruple', for example, the first value p _n Therefore, it is possible to more accurately determine whether or not the reception of S1.

또는 4이고 S1 동기가 맞지 않으면서 S1을 수신한 것으로 잘못 판단될 수 있는 경우에 대한 직전 'Phase Quadruple' 및 현재 수신된 'Phase Quadruple'은, 이하와 같다.Referring to Table 2, when S1 is received and the absolute value of the dot product is

Alternatively, the previous 'Phase Quadruple' and the currently received 'Phase Quadruple' for the case where it may be wrongly determined that S1 is received while S1 synchronization is not correct are as follows.

(1) When receiving S1

-If S1 came before S1: (135 °, 45 °, 225 °, 135 °), ( 135 °, 45 °, 225 °, 135 °)

-If S2 came before S1: (315 °, 225 °, 315 °, 45 °), ( 135 °, 45 °, 225 °, 135 °)

(2) Out of sync with S1

-S1 + S2, Offset 1: (225 °, 315 °, 45 °, 135 °), ( 45 °, 225 °, 135 °, 315 °)

-For S1 + S2, Offset 2: (315 °, 45 °, 135 °, 45 °), ( 225 °, 135 °, 315 °, 225 °)

On receiving the S1 or S1 and S2 is the previously may have been received, in which case the first value of the phase difference between the phase value p _n p _{n -1} and 'Quadruple' received immediately before each of 0 °, 90 °. On the other hand, when S1 synchronization is not correct, these phase differences are -90 ° and 180 °, respectively. When the phase differences are shown in the complex plane as shown in FIG. 6, the determination region between receiving and not receiving S1 can be divided by a straight line of y = -x. It can be performed as.

If Equation 9 is positive, S1 is received, and if it is negative, S1 is not synchronized.

The apparatus for estimating frame synchronization according to the present invention as described above may be implemented inside the terminal. Meanwhile, even when the frequency offset changes in time by compensating for the frequency offset according to the AFC, the estimated phase difference may occur differently in every subframe. Therefore, during the frame synchronization estimation process, it is preferable to stop the frequency offset compensation function according to the AFC to prevent the estimated phase difference from occurring differently in every subframe.

In addition, in estimating frame synchronization by the frame synchronization estimator 30, it is preferable to set a threshold value differently according to a frequency offset and compare the calculated internal value. That is, the terminal estimates the frequency offset, and if the estimated frequency offset is less than the reference value, the frame synchronization is estimated by comparing the real part of the first threshold value and the calculated internal value, and the estimated frequency offset is greater than the reference value. In the large case, it is preferable to estimate the frame synchronization by comparing the second threshold value with the absolute value of the calculated dot product.

It is apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

According to the present invention, it is possible to estimate frame synchronization without excessive memory increase in a mobile communication system and to correct a phase estimation error caused by a frequency offset or a Doppler transition.

Claims (18)

In the downlink frame synchronization estimation method in a terminal of a mobile communication system, Acquiring a phase difference between a downlink sync code and a midamble code included in each subframe for M consecutive subframes transmitted from a base station; Calculating a complex dot product of a reference vector, which is a vector representation of M reference phase values, and a phase vector, which is a vector representation of phase differences obtained for the M consecutive subframes; And Estimating frame synchronization using the calculated inner value. The method of claim 1, The calculated inner product value used for the frame synchronization estimation is at least one of a real part or an absolute value of the calculated complex product. The method of claim 2, Estimating a frequency offset between the base station and the terminal; In the frame synchronization estimation step, the use of the calculated inner product is different depending on the magnitude of the estimated frequency offset. The method of claim 3, And if the estimated frequency offset is less than or equal to a predetermined reference value, frame synchronization is estimated according to a comparison result of the calculated real part of the inner product value and a preset first threshold value. The method of claim 4, wherein And when the real part of the calculated inner value is equal to or greater than the first threshold value, estimates frame synchronization by determining that phase values of the phase vector coincide with phase values of the reference vector. The method of claim 3, And if the estimated frequency offset exceeds a predetermined reference value, frame synchronization is estimated using an absolute value of the calculated inner product. The method of claim 6, M is 4, the frame synchronization estimation method. The method of claim 6, Phase difference between the downlink sync code and the midamble code included in the immediately received subframe and the difference between the downlink sync code and the midamble code included in at least one of the M consecutive subframes. Estimating frame synchronization using a frame synchronization method. The method according to any one of claims 1 to 8, The frame synchronization estimation method characterized in that the correction for the frequency offset is not performed in each step. A phase estimator for obtaining a phase difference between a downlink sync code and a midamble code included in a subframe transmitted from a base station; Computing a complex dot product of a reference vector, which is a vector representation of M reference phase values, and a phase vector, which is a vector representation of phase differences obtained for M consecutive subframes obtained by the phase estimator, An internal calculation unit; And And a frame synchronization estimator for estimating frame synchronization using the calculated inner product. The method of claim 10, The calculated dot product used for the frame sync estimation is at least one of a real part or an absolute value of the calculated complex dot product. The method of claim 11, A frequency offset estimator for estimating a frequency offset with the base station; And the frame synchronization estimator is configured to vary the use of the calculated inner product according to the estimated frequency offset. The method of claim 12, When the frequency offset estimated by the frequency offset estimator is equal to or less than a predetermined reference value, the frame synchronization estimator estimates frame synchronization based on a result of comparing the real part of the calculated inner value with a preset first threshold value. Frame synchronization estimation device. The method of claim 13, And determining the frame synchronization by determining that the phase values of the phase vector coincide with the phase values of the reference vector when the real part of the calculated inner value is equal to or greater than the first threshold value. The method of claim 12, And when the frequency offset estimated by the frequency offset estimator exceeds a reference value, the frame sync estimator estimates frame sync using the calculated absolute value of the inner product. The method of claim 14, M is 4, the frame synchronization estimation apparatus. The method of claim 16, The frame synchronization estimator includes a phase difference between a downlink sync code and a midamble code included in a subframe received immediately before, and a downlink sync code and a midamble code included in at least one of the M consecutive subframes. Frame synchronization estimation apparatus characterized in that the frame synchronization is estimated using the difference between the phase difference. The method according to any one of claims 10 to 17, The frame synchronization estimation apparatus, characterized in that the correction for the frequency offset is not performed in the frame synchronization estimation process.

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