KR20070076787A - Method controlling operation of pseudo sram - Google Patents

Abstract

A method for controlling operation of a pseudo SRAM is provided to prevent the increase of current consumption caused by disabling a word line not requiring to be disabled. According to a method for controlling operation of a pseudo SRAM(Static Random Access Memory), when the two row addresses indicating the equal word line are applied continuously, an enable state of the word line is maintained from the time when the word line is enabled by the row address applied first among the two row addresses until the word line is selected again by the row address applied later. The pseudo SRAM is enabled when a command is applied, and disabled after a fixed time.

Description

Method controlling operation of pseudo SRAM

1 is an operation timing diagram for explaining a state of a word line during a read or write operation in a conventional pseudo SRAM.

Fig. 2 is an operation timing diagram for explaining a problem in the write operation in the conventional pseudo SRAM.

Fig. 3 is an operation timing diagram for explaining a problem in read operation in the conventional pseudo SRAM.

4 is an operation timing diagram for explaining a problem in another read operation in the conventional pseudo SRAM.

5 is a flowchart illustrating a method of controlling operation of a pseudo SRAM according to an embodiment of the present invention.

6 is an operation timing diagram for explaining an operation control method in a write operation of the operation control method in FIG. 5;

7 is an operation timing diagram for explaining an operation control method in the read operation of the operation control method of the pseudo SRAM according to the present invention.

8 is an operation timing diagram for explaining an operation control method in another read operation of the operation control method of the pseudo SRAM according to the present invention;

<Description of the symbols for the main parts of the drawings>

ADVB: Effective Address Bar Signal CLK: Clock

W / L: Wordline ADDR: Address

CSL: Column Selection Line VALID: Effective Address

DL9 to DL11: Delay DDL10: Data Delay

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of controlling an operation of a pseudo SRAM.

Among semiconductor memory devices, random access memory (RAM) is a semiconductor memory device capable of performing arbitrary access to a storage location, that is, a memory cell, and performing both reading and writing of data. The RAM is widely used as a memory device of a computer or a peripheral terminal device because of its small size, low power consumption, and high speed access. However, if the power is cut off due to its characteristic (although there is an exception), all the stored data is deleted. There are various types of RAM, but among them, a DRAM in which data is not erased only by performing a refresh operation at regular intervals while the power is connected, and an SRAM in which data is not erased when only power is connected. .

Generally, erasing data when the power is cut off is called volatile memory, and non-volatile memory is called data that is not erased when the power is cut off. The latter is called ROM (Read Only Memory).

SRAM has the advantage of connecting to other integrated circuits, but it is more complicated and expensive because it requires several times more devices to have the same capacity as DRAM.

Therefore, in recent years, a pseudo esram that implements an operation like an SRAM using a DRAM cell structure has been frequently used.

The pseudo static random access memory (PSRAM) internally uses a cell structure of a dynamic random access memory (DRAM), and the operation is similar to that of the SRAM. The pseudo SRAM cell structure, like DRAM, is also called UtRAM because it is configured in the form of one transistor and one capacitor.

The pseudo SRAM has a merit that high integration can be realized while reducing the chip size compared to the conventional SRAM, that is, the normal SRAM. However, since the cell has the same structure as that of the DRAM, there is a burden to perform the refresh operation internally.

1 is an operation timing diagram for describing a state of a word line during a read or write operation in a conventional pseudo SRAM.

Referring to FIG. 1, when the valid address bar signal ADVB is at a low level, a valid address is applied to the pseudo SRAM. That is, the effective address bar signal ADVB may be regarded as a command signal for a read or write operation. Therefore, the word line W / L is enabled in response to the valid address bar signal ADVB.

For pseudo SRAMs, the time at which the word line (W / L) is enabled and disabled is typically generated automatically. That is, the word line W / L is disabled without a separate command after one command.

In FIG. 1, the word line W / L is enabled by the valid address bar signal ADVB. In this case, the word line W / L has a delay time DL1. That is, the word line W / L is enabled after the delay time DL1 after the effective address bar signal ADVB becomes low. The word line W / L is automatically disabled after a predetermined clock has elapsed.

For example, as shown in FIG. 1, the word line W / L is disabled at eight clocks CLK. The word line W / L is enabled after the delay time DL1 according to the first command at the zero clock CLK, and the second command is applied to the same row address at the eight clock CLK. In this case, the word line W / L should be enabled again. That is, when a command is applied to the same row address, an unnecessary transition T1 occurs. In particular, since packet data read or written in the system has a high probability of being stored in memory cells connected to the same word line (W / L), the word line (W / L) that does not require disabling is required. Disabling increases the consumption of current and also delays the read or write operation speed.

2 is an operation timing diagram for explaining such a problem in the write operation in the conventional pseudo-SRAM. The case where the latency of the column address strobe is 4 and the burst length is 4 is taken as an example.

Referring to FIG. 2, the word line W / L corresponding to the valid address VALID is enabled after the delay time DL3 when the valid address bar signal ADVB transitions to the low level by the write command. . The word line W / L is automatically disabled after a predetermined clock has elapsed and then enabled after the delay time DL4 when the same row address is applied again. Since the write operation, the write enable bar signal WEB is at a low level. The column selection line CSL is selected to write data D0 to D3 and D01 to D31 applied to the data input pin DIN in the memory cell.

However, as described above, when the same row address is applied, an unnecessary transition T2 of the word line W / L is generated to increase current consumption and generate a data write delay DDL2. This is because the data write delay DDL1 is inevitable, but the data write delay DDL2 may not be generated if there is no transition T2 of the word line W / L.

3 is an operation timing diagram for explaining a problem in a read operation in a conventional pseudo SRAM. For example, the column address strobe latency (CAS latency) is 4 and the burst length (burst length) is 4.

Referring to FIG. 3, the word line W / L is enabled after the delay time DL5 has elapsed when the valid address bar signal ADVB transitions to a low level by a read command. Then, it is disabled while maintaining the enabled state for a certain period. The word line W / L is a word line corresponding to a valid address VALID. When the word line W / L is disabled and then enabled again, the word line W / L is enabled after the delay time DL6 has elapsed when the valid address bar signal ADVB transitions to a low level.

When the column select line CSL is enabled and the DQS goes high, data DQ0 to DQ3 are output to the data output pin. Thereafter, after the data delay DDL3 has elapsed, the data DQ01 to DQ03 are output. In the case of data of the same memory cell, the data may be the same, but in case of other memory cells connected to the same word line, the data may be different.

As such, the transition T3 of the word line causes a delay DDL3 of the data output to the data output pin.

4 is an operation timing diagram for explaining a problem in another read operation in the conventional pseudo SRAM. The case where the column address strobe latency (CAS latency) is 4 and the burst length is 4 is the same as in FIG. 3, but the case where an interrupt of the effective address bar signal ADVB occurs.

Referring to FIG. 4, the delay of the data output to the output pin during the interruption of the effective address bar signal ADVB is substantially similar to the length of the delay DDL3 illustrated in FIG. 3. This is because the word line W / L is enabled and then disabled regardless of which row address the later row address is. This is because it is characteristic of pseudo-SRAM. Thereafter, when the address specifying the word line W / L is applied, the data DQ01 to DQ31 are output through the data output pin while maintaining the delay DL8. Therefore, the data DQ01 to DQ31 are output after being delayed by the data delay DDL14.

As described above, the conventional pseudo SRAM generally automatically generates a time point at which the word line is enabled and disabled. That is, the word line is disabled after a command without a separate command. Therefore, if a subsequent command is applied to a row address that designates the same word line, the word line must be activated again. Therefore, there is a problem in that current consumption increases due to disabling word lines that do not necessarily have to be disabled. In addition, there is a problem that the operation speed is also delayed during the operation of the read or write.

Therefore, when a row address that designates the same word line is applied and the word line is to be enabled, a method of controlling the operation so as not to be automatically disabled is urgently required.

Accordingly, an object of the present invention is to provide a method for controlling the operation of a pseudo esram to improve problems in the operation of a conventional pseudo esram.

Another object of the present invention is to provide a method for controlling the operation of a pseudo SRAM for improving a problem in which current consumption is increased by disabling a word line that does not need to be disabled.

It is still another object of the present invention to provide a method for controlling the operation of a pseudo SRAM capable of improving an operation speed of a lead or a light.

In order to achieve the above objects, a method of controlling an operation of a pseudo SRAM according to an aspect of the present invention includes: a row that is applied first of two row addresses when two row addresses that designate the same word line are successively applied. The enable state of the word line is maintained until the word line is enabled by an address until the word line is selected again by a row address applied later among the two row addresses.

The pseudo SRAM may be disabled after a predetermined time after the word line is enabled when a command is applied.

Also, the word line may not be disabled after being enabled by the first applied row address and before being selected by the later applied row address.

According to an aspect of the present invention, a method for controlling an operation of a pseudo SRAM includes: enabling a word line designated by a first row address; Applying a second row address after applying the first row address; Comparing the first row address and the second row address; And maintaining the enable state of the word line when the first row address and the second row address are addresses that designate the same word line.

If the first row address and the second row address are not addresses that designate the same word line, the method may further include terminating an enable state of the word line.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. The following descriptions are merely shown and limited by way of example to help those skilled in the art to more fully understand the present invention. Accordingly, the following descriptions should not be used to limit the scope of the invention.

5 is a flowchart illustrating a method for controlling operation of a pseudo SRAM according to an embodiment of the present invention.

Referring to FIG. 5, in the method of controlling an operation of a pseudo SRAM according to an embodiment of the present invention, enabling a word line designated by a first row address A1 and applying the first row address A1. Subsequently applying a second row address (A2), comparing the first row address (A1) and the second row address (A2) (S10); And maintaining the enable state of the word line when the first row address A1 and the second row address A2 are row addresses that designate the same word line (S20). If the first row address A1 and the second row address A2 are not row addresses that designate the same word line, the method may further include terminating an enable state of the word line (S30). Can be.

As a result of the comparison in the step S10 of comparing the first row address A1 and the second row address A2 with a row address that designates the same word line or not, the first row address A1 and the first row address A1 are compared with each other. When the second row address A2 is a row address that designates the same word line, the word line is held. That is, the enabled state is maintained as it is. Thus, the current consumption due to the transition of the word line can be reduced, and the delay can be reduced. A more detailed description thereof will be described below with reference to FIGS. 6 to 8.

After the holding state is maintained as it is, an operation such as reading or writing to the memory cell is performed (S40).

If the first row address A1 and the second row address A2 are not row addresses specifying the same word line, the word line may be disabled (S30).

FIG. 6 is an operation timing diagram for describing an operation control method in a write operation among the operation control methods of FIG. 5.

Referring to FIG. 6, after a predetermined delay DL9 has elapsed, the word line W / L designated by the valid address VALID at the time when the effective address bar signal ADVB at the zero clock transitions to the low level has passed. Is enabled. When an address specifying the same word line as the word line W / L is applied, the word line W / L is not disabled but is enabled as it is.

Therefore, compared with FIG. 2, in the method of controlling the operation of the pseudo SRAM according to the present invention, since the time for writing data D01 to D31 is reduced, the write operation speed is increased. In addition, the operation control method of the pseudo SRAM according to the present invention can reduce the current consumption by reducing unnecessary word line transitions.

7 is an operation timing diagram for explaining an operation control method in a read operation of the operation control method of the pseudo SRAM according to the present invention. The case where the latency of the column address strobe is 4 and the burst length is 4 is taken as an example.

Referring to FIG. 7, the word line W / L designated by the valid address VALID at the time when the valid address bar signal ADVB at the zero clock transitions to the low level has passed a predetermined delay DL10. Is enabled. When an address specifying the same word line as the word line W / L is applied, the word line W / L is not disabled but is enabled as it is.

Therefore, the data DQ0 to DQ3 read from the memory cell designated by the valid address VALID applied at eight clocks are output faster than in the prior art. That is, after all data DQ0 to DQ3 read from the memory cell designated by the valid address VALID applied at the 0 clock are output, data read from the memory cell designated by the valid address VALID applied at 8 clocks is output. The time until the time when (DQ0) is applied is greatly reduced. Therefore, the operation control method of the pseudo SRAM according to the present invention speeds up the read operation speed. Also, by reducing unnecessary word line transitions, current consumption is reduced.

8 is an operation timing diagram for describing an operation control method in another read operation of the operation control method of the pseudo SRAM according to the present invention.

Referring to FIG. 8, the case where the column address strobe latency (CAS latency) is 4 and the burst length is 4 is the same as in FIG. 3, but when the interrupt of the effective address bar signal ADVB occurs. It is shown.

Compared to the case where an interrupt of the similar effective address bar signal ADVB occurs in the conventional pseudo SRAM illustrated in FIG. 4, the method of controlling the operation of the pseudo SRAM according to the present invention includes a conventional data delay DDL14. Decreases. Therefore, the operation control method of the pseudo SRAM according to the present invention can increase the data read operation speed. In addition, it is possible to reduce the current consumption by eliminating unnecessary transition of the word line.

As described above, in the method of controlling the operation of the pseudo SRAM according to the present invention, when two row addresses designating the same word line are successively applied, the word line is identified by the first one of the two row addresses. The enable state of the word line is continuously maintained from the enabled time until the word line is selected again by the row address applied later among the two row addresses. Thus, by reducing the unnecessary transition of the word line, the current consumption is reduced, and the operation speed is improved.

The operation control method of the pseudo SRAM according to the present invention described above is not limited to the above embodiments, and can be variously designed and applied without departing from the basic principles of the present invention. It will be self-evident to those who have the knowledge of.

As described above, the present invention can improve the problems in the operation of the conventional pseudo SRAM by providing a method for controlling the operation of the pseudo SRAM. In particular, the present invention has the effect of improving the problem that the current consumption is increased by disabling the word line that does not need to be disabled.

In addition, the present invention has the effect of improving the operation speed of the lead or light.

Claims (5)

In the method of controlling the behavior of the pseudo-SRAM: In the case where two row addresses designating the same word line are successively applied, the word line is applied by a row address applied later from a point in time when the word line is enabled by a row address applied first among the two row addresses. And maintaining the enabled state of the word line until the selected point again. The method of claim 1, The pseudo SRAM operation method of the pseudo SRAM, characterized in that the word line is enabled when a command is applied, but is disabled after a predetermined time elapses. The method of claim 2, And said word line is disabled by said first applied row address and then not disabled before being selected by said later applied row address. In the method of controlling the behavior of the pseudo-SRAM: Enabling a word line designated by the first row address; Applying a second row address after application of the first row address; Comparing the first row address and the second row address; And And maintaining the enabled state of the word line when the first row address and the second row address are row addresses that designate the same word line as a result of the comparison in the comparing step. RAM operation control method. The method of claim 4, wherein And terminating the enable state of the word line if the first row address and the second row address are not row addresses specifying the same word line.

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