KR20070076081A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to reduce the influence of an in-rush current during a power-up process. A semiconductor memory device includes logic circuits, a power-up reset circuit, and delay circuits. The power-up reset circuit generates a power-up reset signal to initialize the logic circuits. The delay circuits delay the power-up reset signal, and have different delay amounts. At least one of the logic circuits is a high voltage generation circuit. The semiconductor memory device is a DRAM(Dynamic Random Access Memory).

Description

Semiconductor Memory Device

1 illustrates an in-rush current generated during a power-up process of a general semiconductor memory device.

2 illustrates a semiconductor memory device according to the present invention.

3 shows a power-up reset signal VCCHB of a semiconductor memory device according to the present invention.

4 illustrates an in-rush current generated during a power-up process of the semiconductor memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

22,24,26,28: logic circuit

30: power-up reset circuit

2,44,46,48: delay circuit

The present invention relates to a semiconductor memory device, and more particularly to a power-up of the semiconductor memory device.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices may be classified into random access memory (RAM) and read only memory (ROM). RAM is a volatile memory device in which stored data is destroyed when power is cut off. A ROM is a nonvolatile memory device in which stored data is not destroyed even when a power supply is cut off. RAM includes Dynamic RAM (DRAM), Static RAM (SRAM), and the like. The ROM includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EPROM), a flash memory device, and the like.

In order to use the semiconductor memory device, applying a power supply voltage Vcc from the outside is called a power-up. In the power-up operation, the power supply voltage Vcc applied from the outside is not completely stabilized. Therefore, it is difficult to determine the logic high or logic low of various signals or data used in the semiconductor memory device. Also, it is common to initialize the semiconductor memory device when the power supply voltage Vcc is first applied.

In general, the semiconductor memory device includes a power-up reset circuit for initializing the semiconductor memory device while preventing the power supply voltage Vcc from operating in an unstable state during the power-up operation.

However, the conventional semiconductor memory device generates an in-rush current during a power-up operation. 1 illustrates an in-rush current generated during a power-up process of a conventional semiconductor memory device. This in-rush current has emerged as a problem that affects the setting of the power supply voltage inside the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a semiconductor memory device which reduces the influence of in-rush current during a power-up process.

A semiconductor memory device according to the present invention includes logic circuits; A power-up reset circuit for generating a power-up reset signal for initializing the logic circuits; And delay circuits for delaying the power-up reset signal, wherein the delay circuits have a plurality of different delay amounts.

In this embodiment, at least one of the logic circuits is characterized in that the high voltage (Vpp) generating circuit.

In this embodiment, the semiconductor memory device is a DRAM.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 illustrates a semiconductor memory device according to the present invention. Referring to FIG. 2, the semiconductor memory device 10 includes logic circuits 22, 24, 26, and 28, a power-up reset circuit 30, and delay circuits 42, 44, 46, and 48. .

Logic circuits 22, 24, 26, 28 are various functional circuits present in semiconductor memory device 10. For convenience of description, the logic circuits 22, 24, 26, and 28 are limited to four. However, the logic circuits 22, 23, 26, and 28 may be various circuits (eg, a high voltage generation circuit, a synchronous delay loop circuit, an on-die termination circuit, etc.) inside the semiconductor memory device 10.

The power-up reset circuit 30 generates a power-up reset signal VCCHB for resetting the respective logic circuits 22, 24, 26, and 28. The power-up reset signal VCCHB is transmitted to the respective delay circuits 42, 44, 46, and 48.

Delay circuits 42, 44, 46, 48 delay the power-up reset signal VCCHB in accordance with the respective logic circuits 22, 24, 26, 28. Logic circuits 22, 24, 26, 28 are reset by each delayed power-up reset signal VCCHB.

In general, internal logic circuits of a semiconductor memory device are simultaneously reset by a power-up reset signal VCCHB. However, in the semiconductor memory device 10 according to the present invention, the respective logics do not simultaneously perform a power-up reset. Having a delay circuit allows each logic circuit to perform a variety of power-up reset operations.

3 shows a power-up reset signal VCCHB of a semiconductor memory device according to the present invention. Referring to FIG. 3, a power-up reset operation occurs in four portions ①②③④ of the semiconductor memory device according to the present invention. Referring to FIGS. 2 and 3, the logic circuit Logic1: 22 generates a power-up reset at the first time point ① by the delay circuit D1: 42, and the logic circuit Logic2: 24 generates power. -Up reset occurs at the second time point (2) by the delay circuit (D2: 44), and logic circuit Logic3: 26 indicates that power-up reset is performed at the third time point (3) by the delay circuit (D3: 46). And the logic circuit Logic4: 26 is causing a power-up reset to occur at the fourth time point ④ by the delay circuit D4: 48.

4 illustrates an in-rush current generated during a power-up process of the semiconductor memory device according to the present invention. Referring to FIG. 4, it can be seen that in-rush current is distributed in the semiconductor memory device according to the present invention. This is because logic circuits in the semiconductor memory device 10 perform a power-up reset at different times.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the semiconductor memory device according to the present invention includes a delay circuit for delaying a power-up signal to distribute in-rush current which adversely affects the internal voltage setting of the semiconductor memory device.

Claims (3)

Logic circuits; A power-up reset circuit for generating a power-up reset signal for initializing the logic circuits; And And delay circuits for delaying the power-up reset signal, wherein the delay circuits have a plurality of different delay amounts. The method of claim 1, At least one of the logic circuits is a high voltage (Vpp) generation circuit. The method of claim 1, And said semiconductor memory device is a DRAM.

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