KR20070071436A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
KR20070071436A
KR20070071436A KR1020050134860A KR20050134860A KR20070071436A KR 20070071436 A KR20070071436 A KR 20070071436A KR 1020050134860 A KR1020050134860 A KR 1020050134860A KR 20050134860 A KR20050134860 A KR 20050134860A KR 20070071436 A KR20070071436 A KR 20070071436A
Authority
KR
South Korea
Prior art keywords
well
gate electrode
forming
semiconductor device
manufacturing
Prior art date
Application number
KR1020050134860A
Other languages
Korean (ko)
Inventor
박승표
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050134860A priority Critical patent/KR20070071436A/en
Publication of KR20070071436A publication Critical patent/KR20070071436A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

A method for fabricating a semiconductor device is provided to stabilize a threshold voltage by forming a P+ well of a double structure wherein the back bias voltage of a PMOS transistor constituting a latch-type sense amplifier is applied by the P+ well. An N well for forming a sense amplifier is formed on a P-type substrate, and first and second gate electrodes(27,29) are formed on the N well. Source and drain regions(35,37) are respectively formed inside and outside the first and second gate electrodes. Impurity ions are implanted into the N well at one side of the first gate electrode and the other side of the second gate electrode to form a P+ well(31,33) for applying a bias voltage. A first bitline contact(43) is formed in each P+ well. A second bitline contact is formed which comes in contact with the first and second gate electrodes. A third bitline contact(41) is formed in the source and drain regions.

Description

반도체 소자의 제조방법{MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE}MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

도 1은 종래 기술에 따른 반도체 소자의 제조방법을 도시한 평면도.1 is a plan view showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 평면도.2A to 2C are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 프로브 테스트시 래치형 감지증폭기를 구성하는 PMOS 트랜지스터의 문턱전압을 안정화시킬 수 있는 반도체 소자의 제조방법에 관한 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of stabilizing a threshold voltage of a PMOS transistor constituting a latch type sensing amplifier during a probe test.

반도체 소자는 셀 트랜지스터 및 캐패시터가 형성되는 셀영역과 셀영역의 소자를 구동시키기 위한 감지증폭기(Sense amplifier) 등이 형성되는 주변회로 및 로직 회로가 형성되는 코어 영역으로 구분된다. The semiconductor device is divided into a cell region in which cell transistors and capacitors are formed, and a peripheral region in which a sense amplifier for driving an element of the cell region and the like are formed, and a core region in which a logic circuit is formed.

한편, 반도체 소자는 제조 후 각 메모리 셀에 대해 프로브 테스트를 실시하여, 테스트 결과 초기 불량이 발생된 메모리 셀의 어드레스를 분석한 후 리페어가 가능한 셀에 대해 리페어(repair)를 실시한다.Meanwhile, the semiconductor device performs a probe test on each memory cell after fabrication, analyzes the address of the memory cell in which the initial failure occurs as a result of the test, and then repairs the repairable cell.

도 1은 종래 기술에 따른 반도체 소자의 제조방법을 도시한 평면도이다.1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1을 참조하면, P형 기판(미도시) 상에 감지증폭기를 위한 N웰(미도시)을 형성하고, 상기 N웰 상부에 게이트 전극(11, 13)을 형성한다. Referring to FIG. 1, N wells (not shown) for a sensing amplifier are formed on a P-type substrate (not shown), and gate electrodes 11 and 13 are formed on the N wells.

그 다음, 상기 게이트 전극(11, 13)의 내부와 외부에 드레인 영역(17) 및 소스 영역(19)을 형성하여 래치형 감지증폭기를 구성하는 PMOS 트랜지스터를 완성한다. Next, the drain region 17 and the source region 19 are formed inside and outside the gate electrodes 11 and 13 to complete the PMOS transistor constituting the latch type sense amplifier.

그리고, 상기 게이트 전극(13)의 일측의 상기 N웰에 불순물 이온을 주입하여 바이어스 전압을 인가하기 위한 P+영역(15)을 형성한다. An impurity ion is implanted into the N well on one side of the gate electrode 13 to form a P + region 15 for applying a bias voltage.

그 다음, 상기 게이트 전극(11, 13)과 접촉하는 비트라인 콘택(21)을 형성하고, 상기 드레인 영역(17) 및 소스 영역(19)에 각각 비트라인 콘택(23)을 형성한다. 그리고, 상기 P+영역(15)에 비트라인 콘택(25)을 형성한다. Next, bit line contacts 21 contacting the gate electrodes 11 and 13 are formed, and bit line contacts 23 are formed in the drain region 17 and the source region 19, respectively. A bit line contact 25 is formed in the P + region 15.

이때, 상기 비트라인 콘택(25)을 통해 PMOS 트랜지스터의 백 바이어스(back bias) 전압으로 VPP를 인가한다.At this time, VPP is applied to the back bias voltage of the PMOS transistor through the bit line contact 25.

상술한 종래 기술에 따른 반도체 소자의 제조방법은, 상기 게이트 전극(13)의 일측에 형성된 상기 비트라인 콘택(25)을 통해서만 백 바이어스 전압 VPP이 인가되어 PMOS 트랜지스터의 문턱전압이 백 바이어스 전압 VPP에 따라 변동하기 때문에, 프로브(probe) 테스트시 테스트 아이템 중의 하나인 래치형 감지증폭기를 구성하는 트랜지스터의 성능을 스크린하기 위한 2 Column Pause 등에서 페일(fail)이 유발되는 문제점이 있다. In the above-described method of manufacturing a semiconductor device, a back bias voltage VPP is applied only through the bit line contact 25 formed at one side of the gate electrode 13 so that the threshold voltage of the PMOS transistor is applied to the back bias voltage VPP. Since it varies depending on the probe, a failure occurs in a 2-column pause or the like for screening the performance of a transistor constituting a latch-type sense amplifier which is one of test items during a probe test.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 래치형 감 지증폭기를 구성하는 PMOS 트랜지스터의 백 바이어스 전압을 인가하기 위한 P+웰을 더블(double) 구조로 형성함으로써 문턱전압을 안정화시켜 프로브 테스트시 마진을 확보할 수 있도록 하는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and stabilizes the threshold voltage by forming a P + well having a double structure for applying a back bias voltage of a PMOS transistor constituting a latch type sensing amplifier. It is an object of the present invention to provide a method for manufacturing a semiconductor device to ensure a margin during the test.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, (a) P형 기판 상에 감지증폭기 형성을 위한 N웰을 형성하고, N웰 상부에 제 1 게이트 전극 및 제 2 게이트 전극을 형성하는 단계; (b) 제 1 게이트 전극 및 제 2 게이트 전극의 내부와 외부에 각각 소스 영역 및 드레인 영역을 형성하고, 제 1 게이트 전극의 일측 및 제 2 게이트 전극의 타측의 N웰에 불순물 이온을 주입하여 바이어스 전압을 인가하기 위한 P+웰을 형성하는 단계; 및 (c) P+웰 각각에 제 1 비트라인 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: (a) forming an N well for forming a sensing amplifier on a P-type substrate, and forming a first gate electrode and a second gate electrode on the N well; Doing; (b) source and drain regions are formed inside and outside the first gate electrode and the second gate electrode, and impurity ions are injected into the N well on one side of the first gate electrode and the other side of the second gate electrode to bias Forming a P + well for applying a voltage; And (c) forming first bitline contacts in each of the P + wells.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 평면도이다.2A to 2C are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, P형 기판(미도시) 상에 감지증폭기 형성을 위한 N웰(미도시)을 형성하고, 상기 N웰 상부에 게이트 전극(27, 29)을 형성한다. Referring to FIG. 2A, N wells (not shown) for forming a sense amplifier are formed on a P-type substrate (not shown), and gate electrodes 27 and 29 are formed on the N wells.

도 2b를 참조하면, 상기 게이트 전극(27, 29)의 내부와 외부에 소스 영역(35) 및 드레인 영역(37)을 형성하여 래치형 감지증폭기를 구성하는 PMOS 트랜지스터를 완성한다. Referring to FIG. 2B, a source region 35 and a drain region 37 are formed inside and outside the gate electrodes 27 and 29 to complete a PMOS transistor constituting a latch type sensing amplifier.

그리고, 상기 게이트 전극(27)의 일측 및 상기 게이트 전극(29)의 타측의 상기 N웰에 불순물 이온을 주입하여 바이어스 전압을 인가하기 위한 P+웰(31, 33)을 형성한다. Impurity ions are implanted into the N well on one side of the gate electrode 27 and the other side of the gate electrode 29 to form P + wells 31 and 33 for applying a bias voltage.

도 2c를 참조하면, 상기 게이트 전극(27, 29)과 접촉하는 비트라인 콘택(39)을 형성하고, 상기 소스 영역(35) 및 드레인 영역(37)에 각각 비트라인 콘택(41)을 형성한다. 그리고, 상기 P+웰(31, 33) 각각에 비트라인 콘택(43)을 형성한다.Referring to FIG. 2C, bit line contacts 39 contacting the gate electrodes 27 and 29 are formed, and bit line contacts 41 are formed in the source region 35 and the drain region 37, respectively. . A bit line contact 43 is formed in each of the P + wells 31 and 33.

이때, 상기 비트라인 콘택(39)에 백 바이어스 전압으로 VPP를 인가한다.At this time, VPP is applied to the bit line contact 39 as a back bias voltage.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 래치형 감지증폭기를 구성하는 PMOS 트랜지스터의 백 바이어스 전압을 더블(double) 구조로 형성된 P+웰을 통해 양측에서 공급함으로써 문턱전압을 안정화시켜 프로브 테스트시 마진 부족에 의한 페일을 방지할 수 있는 효과를 제공한다. As described above, the method of manufacturing a semiconductor device according to the present invention stabilizes the threshold voltage by supplying the back bias voltage of the PMOS transistor constituting the latch type sense amplifier from both sides through a P + well formed in a double structure. Probe test prevents failing due to lack of margin.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

(a) P형 기판 상에 감지증폭기 형성을 위한 N웰을 형성하고, 상기 N웰 상부에 제 1 게이트 전극 및 제 2 게이트 전극을 형성하는 단계;(a) forming an N well for forming a sense amplifier on the P-type substrate, and forming a first gate electrode and a second gate electrode on the N well; (b) 상기 제 1 게이트 전극 및 상기 제 2 게이트 전극의 내부와 외부에 각각 소스 영역 및 드레인 영역을 형성하고, 상기 제 1 게이트 전극의 일측 및 상기 제 2 게이트 전극의 타측의 상기 N웰에 불순물 이온을 주입하여 바이어스 전압을 인가하기 위한 P+웰을 형성하는 단계; 및 (b) source and drain regions are formed inside and outside the first and second gate electrodes, respectively, and impurities are formed in the N well on one side of the first gate electrode and the other side of the second gate electrode. Implanting ions to form a P + well for applying a bias voltage; And (c) 상기 P+웰 각각에 제 1 비트라인 콘택을 형성하는 단계(c) forming a first bitline contact in each of said P + wells 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 (c)단계 이후에 상기 제 1 게이트 전극 및 상기 제 2 게이트 전극과 접촉하는 제 2 비트라인 콘택을 각각 형성하고, 상기 소스 영역 및 상기 드레인 영역에 제 3 비트라인 콘택을 각각 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein after the step (c), a second bit line contact is formed to contact the first gate electrode and the second gate electrode, and a third bit line contact is formed in the source region and the drain region. Method for manufacturing a semiconductor device characterized in that it further comprises the step of forming each.
KR1020050134860A 2005-12-30 2005-12-30 Manufacturing method of semiconductor device KR20070071436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050134860A KR20070071436A (en) 2005-12-30 2005-12-30 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050134860A KR20070071436A (en) 2005-12-30 2005-12-30 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR20070071436A true KR20070071436A (en) 2007-07-04

Family

ID=38506567

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050134860A KR20070071436A (en) 2005-12-30 2005-12-30 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR20070071436A (en)

Similar Documents

Publication Publication Date Title
TW201730794A (en) Layout pattern for SRAM and manufacturing methods thereof
US8093664B2 (en) Non-volatile semiconductor memory device and depletion-type MOS transistor
US10748913B2 (en) SRAM cell with T-shaped contact
US20070146008A1 (en) Semiconductor circuit comprising vertical transistor
KR20080083802A (en) Latch structure and bit line sense amp having the same
JP2008028055A (en) Semiconductor device and manufacturing method thereof
KR980006413A (en) NAND CELL ARRAY
JP4775352B2 (en) Manufacturing method of semiconductor memory device
KR100805434B1 (en) Semiconductor memory device
US6791200B2 (en) Semiconductor memory device
US6445041B1 (en) Semiconductor memory cell array with reduced parasitic capacitance between word lines and bit lines
JP5486172B2 (en) Semiconductor memory device
JP2007323770A (en) Sram
CN100530639C (en) System-in-package type static random access memory device and manufacturing method thereof
US8134213B2 (en) Static random access memory and method for manufacturing the same
US7626855B2 (en) Semiconductor memory device
KR20070071436A (en) Manufacturing method of semiconductor device
US20060088964A1 (en) Method of forming SRAM cell
TWI505270B (en) Memory cell and memory array utilizing the memory cell
KR101387689B1 (en) Semiconductor device
JP2008135169A (en) Semiconductor storage device
JP5715716B2 (en) Semiconductor memory device
KR20090022779A (en) Semiconductor device
JPH01253264A (en) Semiconductor integrated circuit
KR19980037350A (en) Semiconductor Memory Structure with Improved Operational Stability and Manufacturing Method Thereof

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid