KR20070069781A - Fabricating method of thin film transistor array substrate - Google Patents

Abstract

A fabricating method of a thin film transistor array substrate is provided to carry out baking by additionally doping second photoresist after depositing a transparent conductive film for changing a structure of the transparent conductive film on first photoresist differently from the transparent conductive film of any other areas to control etching selection rates differently, thereby simplifying the etching and patterning the transparent conductive film without short or open failure. A fabricating method of a thin film transistor array substrate includes a first conductive pattern forming step, a hole forming step, a second conductive pattern forming step, and a third conductive pattern forming step. The first conductive pattern includes gate lines(120) connected to gate electrodes and gate and data pad lower electrodes(181,191) formed on a substrate(110) through a first mask. In the hole forming step, a gate insulating film and a semiconductor layer are formed on the substrate in sequence, first and second contact holes are formed by penetrating the gate insulating film and the semiconductor layer to expose the gate and data pad lower electrodes by using a first photoresist pattern formed through a second mask, wherein pixel holes are formed by exposing the substrate through the gate insulating film and the semiconductor layer. The second conductive pattern includes pixel electrodes(160), and gate and data pad upper electrodes(182,192) formed by exposing and removing a transparent conductive film formed on the first photoresist pattern by using a second photoresist pattern, which is formed by etching, after forming the transparent conductive film on the first and second contact holes, the pixel holes and the first photoresist pattern. The third conductive pattern includes a semiconductor pattern for forming channels, data lines(130) connected to source electrodes(132), and drain electrodes(133) facing the source electrodes via the channels, which are through a third mask.

Description

Manufacturing Method of Thin Film Transistor Substrate {FABRICATING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE}

1 is a plan view of a thin film transistor substrate forming a conventional liquid crystal display panel.

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along lines II ′, II-II ′, and III-III ′ of FIG. 1.

3A to 3L are manufacturing process diagrams of a thin film transistor substrate using a conventional three mask process.

4 and 5 are diagrams for explaining the failure of the pattern design (pattern design) generated in the conventional three mask process.

6 is a plan view of a thin film transistor substrate constituting a liquid crystal display panel according to the present invention;

FIG. 7 is a cross-sectional view of the thin film transistor substrate taken along line IV-IV ′ and V-V ′ of FIG. 6.

8A and 8B are plan and cross-sectional views of a thin film transistor substrate on which a first conductive pattern is formed through a first mask process according to the present invention.

9A to 9C are manufacturing process diagrams of a thin film transistor substrate having a first conductive pattern according to the present invention.

10A and 10B are plan and cross-sectional views of a thin film transistor substrate on which a second conductive pattern is formed through a second mask process according to the present invention.

11A to 11I are manufacturing process diagrams of a thin film transistor substrate having a second conductive pattern according to the present invention.

12A and 12B are plan and cross-sectional views of a thin film transistor substrate on which a third conductive pattern is formed through a third mask process according to the present invention.

13A to 13I are manufacturing process diagrams of a thin film transistor having a third conductive pattern according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100 thin film transistor substrate 110 substrate

120: gate line 122: gate electrode

130: data line 132: source electrode

133: drain electrode 134: active layer

135 ohmic contact layer 140 thin film transistor

145: channel protection film 151: first contact hole

152: second contact hole 153: third contact hole

160: pixel electrode 161: pixel area

170: storage capacitor 180: gate pad

181: gate pad lower electrode 182: gate pad upper electrode

190: data pad 191: data pad lower electrode

192: data pad upper electrode 195: data pad link portion

200: first mask 300: second mask

350: first photoresist pattern 380: second photoresist pattern

400: third mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate, and more particularly, to a method of manufacturing a thin film transistor substrate capable of satisfactorily forming a pattern design (PD) through a three mask process.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a thin film transistor substrate and a color filter substrate bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display device, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel.

In order to solve the problems described above, the thin film transistor substrate is developing in a direction of reducing the number of mask processes, which means that one mask process includes a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection. It is closely related to the inclusion of many processes, such as processes.

Therefore, in recent years, a three-mask process using a lift-off method or a passiless method that reduces one mask process in a five-mask or four-mask process, which is a standard mask process of a thin film transistor substrate, has emerged. have.

First, the structure and operation of a thin film transistor substrate manufactured through a conventional three mask process will be described with reference to FIGS. 1 and 2. 1 is a plan view of a thin film transistor substrate manufactured by a conventional three mask process, and FIG. 2 is a thin film transistor cut along the lines I-I ', II-II', and III-III 'of FIG. 1. Sectional view of the substrate.

Referring to FIGS. 1 and 2, a thin film transistor substrate manufactured by a conventional three mask process may include a gate line 20 having a gate line 20 and a gate insulating layer 25 formed therebetween. A data line 30 intersecting with 20 to define a pixel region 61, a thin film transistor 40 formed at each intersection thereof, and a pixel electrode 60 connected to the thin film transistor 40 and formed in the pixel region 61. The storage capacitor 70 formed at an overlapping portion of the gate line 20 and the storage electrode 65, the gate pad 80 connected to the gate line 20, and the data pad 90 connected to the data line 30. It is provided.

Here, the thin film transistor 40 is responsible for charging the pixel signal of the data line 30 to the pixel electrode 60 in response to the gate signal of the gate line 20, and is connected to the gate line 20. A gate electrode 22, a source electrode 32 connected to the data line 30, and a source electrode 32 opposite to the source electrode 32 with a channel interposed therebetween, and a drain electrode 33 laterally connected to the pixel electrode 60. do.

The thin film transistor 40 is formed to overlap the gate electrode 22 with the gate insulating layer 25 interposed therebetween to form the channel between the source electrode 32 and the drain electrode 33. 32 and an ohmic contact layer 35 formed on the active layer 34 except for the channel portion for ohmic contact with the drain electrode 33.

In this case, the active layer 34 and the ohmic contact layer 35 are formed to overlap the data line 30, the data pad lower electrode 91, and the storage electrode 65.

The passivation layer 50 covers the thin film transistor 40 formed on the gate insulating layer 25 and protects the active layer 34 forming the channel from moisture or scratches that may occur during subsequent processes. do.

The pixel electrode 60 is formed in the pixel hole 61 of the pixel region defined by the intersection of the gate line 20 and the data line 30, and is in side contact with the drain electrode 33 of the thin film transistor 40. And is formed in a boundary with the passivation layer 50.

More specifically, the pixel electrode 60 is laterally connected to the partially etched drain electrode 33 when the pixel hole 62 penetrating the passivation layer 50 and the gate insulating layer 25 is formed. A portion of the active layer 34 exposed by the electrode 33 overlaps or is formed in contact with the side surface of the gate insulating layer 25.

In this case, an electric field is formed between the pixel electrode 60 supplied with the pixel signal through the thin film transistor 40 and a common electrode (not shown) supplied with the reference voltage.

Accordingly, the electric field formed between the pixel electrode 60 and the common electrode rotates the liquid crystal molecules filled between the thin film transistor substrate and the color filter substrate by dielectric anisotropy and transmits the pixel region 61 according to the degree of rotation of the liquid crystal molecules. The gray scale is realized by varying the light transmittance.

The storage capacitor 70 includes a gate line 20, and a storage electrode 65 overlapping the gate line 20 with the gate insulating layer 25, the active layer 34, and the ohmic contact layer 35 therebetween. do. Here, the pixel electrode 60 formed in the pixel hole 61 bordering the passivation layer 50 is connected to the side surface of the storage electrode 65. The storage capacitor 70 allows the pixel signal charged in the pixel electrode 60 to remain stable until the next pixel signal is charged.

The gate pad 80 is connected to a gate driver (not shown) to supply a gate signal to the gate line 20. The gate pad 80 is formed through the inner surface of the gate pad lower electrode 81 extending from the gate line 20 and the first contact hole 51 passing through the gate insulating layer 25 and the passivation layer 50. The gate pad upper electrode 82 is connected to the lower electrode 81.

The data pad 90 is connected to a data driver (not shown) to supply a data signal to the data line 30. The data pad 90 may be connected to the data pad lower electrode 91 through the inner surface of the data pad lower electrode 91 extending from the data line 30 and the second contact hole 53 passing through the passivation layer 50. The data pad upper electrode 92 is connected.

In this case, the data pad upper electrode 92 is formed by etching the ohmic contact layer 35 and the active layer 34 constituting the data pad lower electrode 91 when the second contact hole 52 is formed. ) Or in contact with the remaining active layer 34.

Hereinafter, a method of manufacturing a thin film transistor substrate using a conventional three mask process will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 3A, a first conductive pattern including a gate line 20, a gate electrode 22, and a gate pad lower electrode 81 is formed on the lower substrate 10 through a first mask process. Form.

In more detail, the gate metal layer is formed on the lower substrate 10 through a deposition method such as a sputtering method.

Subsequently, after the photoresist is entirely coated on the gate metal layer, a photolithography process using a first mask is performed, whereby the gate electrode 20 connected to the gate line 20 and the gate line 20 on the lower substrate 10. 22) and a first conductive pattern including the gate pad lower electrode 81.

As described above, after the first conductive pattern is formed on the lower substrate 10, the semiconductor pattern and the second conductive pattern for forming the channel are formed on the gate insulating layer 25 through the second mask process.

More specifically, as illustrated in FIG. 3B, the gate insulating layer 25, the amorphous silicon layer 34a, and n + may be deposited on the lower substrate 10 on which the first conductive pattern is formed through a deposition method such as PECVD or sputtering. The amorphous silicon layer 35a and the data metal layer 30a are sequentially formed.

Here, the metal forming the data metal layer 30a may be a metal in which the exposed portions of the passivation layer 50 may be etched together in a subsequent process, for example, Mo, Cu, Al, or the like, which may be dry etched. Cr series etc. are used.

Thereafter, the photoresist is entirely coated on the data metal layer 30a, and then a photolithography process using a second mask, which is a diffraction exposure mask, is performed to have a step on the data metal layer 30a, as shown in FIG. 3C. The photoresist pattern PR is formed.

In this case, a photoresist pattern formed in the channel region is lower than a photoresist pattern formed in the other region by using a diffraction exposure mask (Half Tone Mask) corresponding to the diffraction exposure portion in the channel region of the thin film transistor 40 as the second mask. Formed to a height.

After forming the photoresist pattern having a deviation on the data metal layer 30a as described above, as shown in FIG. 3D, the wet etching of the data metal layer 30a exposed by the photoresist pattern is performed. Remove through.

Thereafter, the n + amorphous silicon layer 35a and the amorphous silicon layer 34a exposed as the data metal layer 30a is removed through wet etching are sequentially removed through dry etching.

As described above, after the n + amorphous silicon layer 35a and the amorphous silicon layer 34a are sequentially removed, as shown in FIG. 3E, the photoresist pattern is subjected to an ashing process using an oxygen (O ₂ ) plasma. By removing the data, the data metal layer 30a formed in the channel region is exposed.

In this case, the photoresist pattern corresponding to the blocking portion of the diffraction exposure mask is partially removed by an ashing process using an oxygen (O ₂ ) plasma, thereby partially exposing the data metal layer 30a formed in the blocking region.

Thereafter, the data metal layer 31 exposed to the channel region and the blocking region is removed by dry etching, thereby as shown in FIG. 3F, the source electrode 32 connected to the data line 30 and the data line 30. The source electrode 32 is separated to form a drain electrode 33 and a storage electrode 65 facing each other.

In this case, the storage electrode 65 is formed to overlap the gate line 20 with the gate insulating layer 25 and the semiconductor pattern interposed therebetween, and the source electrode 32 and the drain electrode 33 are separated from each other. The formed n + amorphous silicon layer 35a is opened.

By removing the n + amorphous silicon layer 35a opened in the channel region through dry etching as described above, as shown in FIG. 3G, the ohmic contact layer 35 and the active layer forming the channel of the thin film transistor 40 are formed. 34 are formed sequentially.

Then, by removing the photoresist pattern remaining on the gate insulating film 25, as shown in Figure 3h, by removing the photoresist pattern remaining on the gate insulating film 25, the data line 30, data line ( A semiconductor pattern comprising a source electrode 32 connected to the source 30, a drain electrode 33 corresponding to the source electrode 32 with a channel interposed therebetween, an active layer 34 forming a channel, and an ohmic contact layer 35; A second conductive pattern including the storage electrode 65 is formed.

After the semiconductor pattern and the second conductive pattern are formed on the gate insulating film 25 as described above, the protective film 50 and the gate insulating film 25 on the gate insulating film 25 through a lift-off process using a third mask. A third conductive pattern is formed.

In more detail, by performing a photolithography process using a third mask after depositing the passivation layer 50 on the gate insulating layer 25 on which the semiconductor pattern and the second conductive pattern are formed, as shown in FIG. 3I. Similarly, photoresist patterns for forming the first and second contact holes 51 and 52 and the pixel holes 61 are formed on the passivation layer 50.

After the photoresist pattern is formed on the protective film 50 as described above, the photoresist pattern is reduced in height by performing an ashing process on the photoresist pattern, and at the same time, the photoresist pattern is formed into an inverted tape shape. . As shown in FIG. 3J, the first and second contact holes 51 and 52 and the pixels are sequentially removed by dry etching of the passivation layer 50 and the gate insulating layer 25 exposed by the photoresist pattern. The pixel hole 61 on which the electrode is to be deposited is formed.

In this case, the first contact hole 51 passes through the passivation layer 50 and the gate insulating layer 25 to expose the gate pad lower electrode 81, and the second contact hole 53 forms the lower portion of the passivation layer 25 and the data pad. The lower substrate 10 is exposed through the electrode 91.

The pixel hole 61 passes through the passivation layer 50 and the gate insulating layer 25 formed in the pixel region 60 to expose the lower substrate 10. In this case, when dry etching is performed to form the pixel hole 62, the side surfaces of the exposed drain electrode 33 are etched, so that the ohmic contact layer 35 and the active layer 34 overlapping the drain electrode 33 may also be formed. Etched sequentially.

As described above, after the first and second contact holes 51 and 52 and the pixel hole 61 are formed using the photoresist pattern on the passivation layer 50, as shown in FIG. 3K, a sputtering method or the like is illustrated. The entire surface of the transparent conductive film 60a is deposited on the lower substrate 10 on which the photoresist pattern is formed.

In this case, the undercut region “A” is formed between the transparent conductive film 60a formed on the protective film 50 and the transparent conductive film 60b formed in the pixel hole 61 region due to the protective film 50 formed in the reverse tape shape. ") Occurs.

Thereafter, the photoresist pattern formed on the passivation layer 50 is removed through the strip process using the undercut region “A”, and then the transparent conductive layer 60a formed on the photoresist pattern is removed through the lift off process. As illustrated in FIG. 3L, a third conductive pattern including the pixel electrode 60, the gate pad upper electrode 82, and the data pad upper electrode 92 is formed.

In this case, the pixel electrode 60 is formed in the pixel hole 61 to form a boundary with the passivation layer 50 and is connected to the side surface of the drain electrode 33.

The gate pad upper electrode 82 forms a side boundary with the passivation layer 50 and the gate insulating layer 25 patterned in the first contact hole 51 and is connected to the gate pad lower electrode 81.

In addition, the data pad upper electrode 92 forms a boundary with the passivation layer 50 in the second contact hole 52 and is laterally connected to the data pad lower electrode 91.

However, when the thin film transistor substrate is manufactured through the lift-off process using the conventional third mask as described above, as shown in FIG. 4, since the protective film 50 is not formed in an inverted tape shape, the protective film ( Often, undercutting does not occur between the transparent conductive film 60a formed on the 50 and the transparent conductive film 60b formed in the pixel hole 62. As a result, the transparent conductive film 60a formed on the passivation film 50 and the transparent conductive film 60b formed in the pixel hole 62 are mutually shorted ("B"), thereby closing the space where the strip liquid penetrates. As a result, the protective film 50 and the transparent conductive film 60a to be removed remain, causing a PD defect.

In addition, in the case where the transparent conductive film 60b is formed in the state where the foreign material is introduced into the pixel hole 62, as shown in FIG. 5, the strip liquid for stripping the photoresist pattern is formed along the region where the foreign material exists. By penetrating, a part of the transparent conductive film 60b formed in the pixel hole 62 is lost ("C" portion) during the lift-off process.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor substrate that can be satisfactorily patterned through a three mask process.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention includes a gate line, a gate electrode connected to the gate line, a gate pad lower electrode, and a data pad lower electrode on a substrate through a first mask process. Forming a first conductive pattern comprising; After sequentially forming a gate insulating film and a semiconductor layer on the substrate on which the first conductive pattern is formed, the gate pad is penetrated through the gate insulating film and the semiconductor layer using a first photoresist pattern formed through a second mask process. Forming first and second contact holes exposing a lower electrode and the data pad lower electrode, and forming a pixel hole through the gate insulating layer and the semiconductor layer to expose the substrate; After the transparent conductive layer is entirely formed on the formed first and second contact holes and the pixel hole and the first photoresist pattern, the second photoresist pattern is formed on the first photoresist pattern using the second photoresist pattern formed through the ashing process. Forming a second conductive pattern including the pixel electrode, the gate pad upper electrode, and the data pad upper electrode by exposing and removing the transparent conductive film; After depositing the data metal layer on the substrate on which the second conductive pattern is formed, the source electrode is interposed between the semiconductor pattern for forming the channel, the data line, the source electrode connected to the data line, and the channel through a third mask process. And forming a third conductive pattern including a drain electrode opposite to the drain electrode.

The forming of the first conductive pattern may include depositing a gate metal layer on a substrate; Forming a photoresist pattern on the gate metal layer and then partially exposing the gate metal layer through a photolithography process using a first mask; Etching and patterning the gate metal layer exposed by the photoresist pattern; And removing the photoresist pattern remaining on the patterned gate metal layer through a strip process.

The forming of the second conductive pattern may include sequentially forming a semiconductor layer including a gate insulating layer, an active layer forming a channel, and an ohmic contact layer on a substrate on which the first conductive pattern is formed; Forming a first photoresist pattern by exposing the entire surface of the photoresist on the semiconductor layer and exposing a region where the first and second contact holes and the pixel hole are to be formed through a photolithography process using a second mask; ; Etching the regions exposed by the first photoresist pattern to form first and second contact holes and pixel holes; After forming a transparent conductive film over the first and second contact holes, the pixel hole and the first photoresist pattern, and forming a photoresist covering the transparent conductive film, the second photoresist pattern is formed through an ashing process. Exposing a transparent conductive film formed on the first photoresist pattern; Etching the transparent conductive film formed on the exposed first photoresist pattern; And removing the remaining first and second photoresist patterns through a strip process.

The forming of the third conductive pattern may include forming a data metal layer on the entire surface of the substrate on which the second conductive pattern is formed; Forming a photoresist pattern on the formed data metal layer by exposing the entire surface of the photoresist and then exposing a portion where the pixel electrode is formed through a photolithography process using a third mask but having a step in the channel portion; Etching the data metal layer on the pixel electrode exposed by the photoresist pattern and then exposing the data metal layer formed on the channel portion through an ashing process; Sequentially etching and patterning the exposed data metal layer and an ohmic contact layer below the exposed data metal layer; And removing the photoresist pattern remaining on the patterned data metal layer through a strip process.

The method may further include forming a storage capacitor between the gate line and the data metal layer, wherein the storage capacitor includes a gate insulating layer and a semiconductor layer, wherein the storage capacitor is formed so that the semiconductor layer is laterally connected to the pixel electrode.

After the entire surface of the photoresist covering the transparent conductive film is formed, a step of performing a heat treatment to polyimide the transparent conductive film deposited in the pixel region before forming the second photoresist pattern through an ashing process Characterized in that.

The forming of the third conductive pattern may include etching a patterned data metal layer and an ohmic contact layer of the channel part, patterning the exposed active layer to form a channel, and then forming a channel passivation layer on the exposed active layer to secure the channel. It characterized in that it further comprises the step of forming.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure and operation of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 6 and 7. 6 is a plan view of a thin film transistor substrate according to the present invention, and FIG. 7 is a cross-sectional view of the thin film transistor substrate taken along lines IV-IV ′ and V-V ′ of FIG. 6.

6 and 7, the thin film transistor substrate according to the present invention includes a data line crossing the gate line 120 with the gate line 120 formed on the lower substrate 110 and the gate insulating layer 125 interposed therebetween. 130, the thin film transistor 140 formed at each intersection of the gate line 120 and the data line 130, the pixel electrode 160 formed in the pixel region 161 having the crossing structure, the pixel electrode 160, The storage capacitor 170 is formed adjacent to the gate line, the gate pad 180 extending from the gate line 120, and the data pad 190 extending from the data line 130.

Here, the gate line 120 transfers a gate signal supplied from a gate driver (not shown) connected to the gate pad 180 to the gate electrode 122 constituting the thin film transistor 140.

The data line 130 is a source electrode 132 constituting the thin film transistor 140 by interlocking a data signal supplied from a data driver (not shown) connected to the data pad 190 with the on / off of the gate electrode 122. ) And the drain electrode 133.

The thin film transistor 140 charges the pixel electrode 160 of the data line 130 to the pixel electrode 160 in response to the gate signal of the gate line 120, and is connected to the gate line 120. A source electrode 132 connected to the data line 130 and a drain electrode 133 connected to the pixel electrode 160 while facing the source electrode 132 with the channel interposed therebetween.

In addition, the thin film transistor 140 may be formed to overlap the gate electrode 122 with the gate insulating layer 125 therebetween to form a channel between the source electrode 132 and the drain electrode 133. An ohmic contact layer 135 is formed on the active layer 134 except for the channel region for ohmic contact between the source electrode 132 and the drain electrode 133.

In addition, the thin film transistor 140 further includes a channel passivation layer 145 for protecting the active layer from moisture or scratches that may be generated during a subsequent process by covering the exposed active layer of the channel portion.

In this case, the active layer 134 and the ohmic contact layer 135 are formed to overlap the data line 130.

In the pads 180 and 190, first and second contact holes 151 and 152 are formed through a photolithography process using a mask. Here, the first contact hole 151 penetrates through the gate insulating layer 125 and the active layer 134 to expose the gate pad lower electrode 181, and the second contact hole 152 has the gate insulating layer 125 and the active layer ( The data pad lower electrode 182 is exposed through the 134.

The pixel electrode 160 is formed as a transparent conductive film in the pixel region 161 and directly connected to the drain electrode 133 of the thin film transistor 140. In this case, an electric field is formed between the pixel electrode 160 supplied with the pixel signal through the thin film transistor 140 and a common electrode (not shown) supplied with the reference voltage.

Therefore, the liquid crystal molecules charged between the substrates are rotated by the dielectric anisotropy by the electric field formed between the pixel electrode 160 and the common electrode, and the light transmittance that passes through the pixel region 161 depends on the degree of rotation of the liquid crystal molecules. By changing, the gray scale is realized.

The storage capacitor 170 has a shape in which the gate line 120 and the pixel electrode 160 are adjacent to each other with the gate insulating layer 125 interposed therebetween. The storage capacitor 170 keeps the pixel signal charged in the pixel electrode 160 stable until the next pixel signal is charged.

The gate pad 180 is connected to a gate driver (not shown) to supply a gate signal to the gate line 120.

The gate pad 180 may be gated in the gate pad lower electrode 181 extending from the gate line 120, the first contact hole 151 passing through the gate insulating layer 125, and the first contact hole 151. The pad lower electrode 181 is connected to the gate pad upper electrode 182.

The data pad 190 is connected to a data driver (not shown) to supply a data signal to the data line 130.

The data pad 190 includes a data pad lower electrode 191 formed of a gate metal layer, a second contact hole 152 penetrating through the gate insulating layer 125, and a data pad lower electrode in the second contact hole 152. And a data pad upper electrode 192 connected to 191.

The data pad lower electrode 191 is electrically connected to the data line 130 through the data pad link unit 195. To this end, the data pad link unit 195 may include a data link lower electrode (not shown) connected to the data pad lower electrode 191, a data link upper electrode (not shown) connected to the data line 130, and And a link electrode (not shown) connecting the data link lower electrode 42 exposed through the three contact holes 153 and the data link upper electrode.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

First, a process of forming the first conductive pattern of the thin film transistor substrate according to the present invention will be described with reference to FIGS. 8A and 8B. 8A and 8B are a plan view and a cross-sectional view of a thin film transistor substrate on which a first conductive pattern according to the present invention is formed.

8A and 8B, a method of manufacturing a thin film transistor substrate according to the present invention may include a gate line 120, a gate electrode 122, and a gate pad lower electrode on a lower substrate 110 using a first mask process. A first conductive pattern including 181 and the data pad lower electrode 191 is formed.

In more detail, as illustrated in FIG. 9A, the gate metal layer 120a is formed on the lower substrate 110 through a deposition method such as a sputtering method. Here, the gate metal layer 120a is made of aluminum (Al) -based metal, copper (Cu), chromium (Cr), molybdenum, or the like.

At this time, when the gate metal layer 120a forming the first conductive pattern is formed of an aluminum (Al) -based metal, which is a low resistance wiring, to improve contact resistance with the transparent conductive film ITO forming the third conductive pattern. It may be formed in a dual structure such as AlNd / Mo.

Subsequently, after the photoresist is applied to the gate metal layer 120a, a photolithography process using the first mask 200 is performed, so that a predetermined photoresist pattern on the gate metal layer 120a is formed as shown in FIG. 9B. 250).

In this case, by performing wet etching on the gate metal layer 120a exposed by the photoresist pattern 250, as shown in FIG. 9C, the gate line 120 on the lower substrate 110 is formed. A first conductive pattern including a gate electrode 122, a gate pad lower electrode 181, and a data pad lower electrode 191 connected to the gate line 120 is formed.

After the first conductive pattern is formed on the lower substrate 110 as described above, as shown in FIGS. 10A and 10B, the first conductive pattern is formed on the lower substrate 110 through the second mask process. A second conductive pattern is formed. 10A and 10B are a plan view and a cross-sectional view of a thin film transistor substrate on which a second conductive pattern according to the present invention is formed.

10A and 10B, after the gate insulating layer 125 is coated on the lower substrate 110 on which the first conductive pattern is formed, the active layer 134 and the ohmic contact layer through a photolithography process using a second mask. A second conductive pattern including the semiconductor layer 135 on which the 135 is stacked, the pixel electrode 160, the gate pad upper electrode 182, and the data pad upper electrode 192 is formed.

More specifically, as illustrated in FIG. 11A, the gate insulating layer 125 is entirely deposited on the lower substrate 110 on which the first conductive pattern is formed through a deposition method such as PECVD or sputtering.

Here, the gate insulating layer 125 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Subsequently, as shown in FIG. 11B, the amorphous silicon layer 134a and the n + amorphous silicon layer 135a are sequentially deposited on the gate insulating layer 125 by a deposition method such as PECVD or sputtering.

Subsequently, the photoresist is entirely coated on the n + amorphous silicon layer 135a and then the photolithography process using the second mask 300 is performed on the n + amorphous silicon layer 135a, as shown in FIG. 11C. A first photoresist pattern 350 having a step is formed.

Subsequently, as shown in FIG. 11D, wet etching of the n + amorphous silicon layer 135a, the amorphous silicon layer 134a, and the gate insulating layer 125 exposed by the first photoresist pattern 350 is sequentially performed. To remove).

Accordingly, a pixel hole 161 is formed through the gate insulating layer 125 and the semiconductor layers 134a and 135a to expose the lower substrate 110. The gate insulating layer 125 and the semiconductor layers 134a and 135a are formed. First and second contact holes 151 and 152 are formed to penetrate and expose the gate pad lower electrode 181 and the data pad lower electrode 191. Although not shown in the cross-sectional view, a third contact hole (not shown in FIG. 10A) exposing the data link lower electrode (not shown) through the gate insulating layer 125 and the semiconductor layers 134a and 135a by the wet etching process. ) Is formed.

Subsequently, as illustrated in FIG. 11E, the first photoresist pattern 350, the exposed lower substrate 110, the exposed gate pad lower electrode 181, the exposed data pad lower electrode 191, and the exposed data link. The transparent conductive film 160a is entirely deposited on the lower electrode through a deposition method such as PECVD or sputtering.

Subsequently, as illustrated in FIG. 11F, a photo is formed on the first photoresist pattern 350, the lower substrate 110, the pad lower electrodes 181 and 191, and the link lower electrode (not shown) on which the transparent conductive film 160a is formed. After the resist 380a is deposited on the entire surface, heat treatment is performed.

The transparent conductive film 160a deposited on the first photoresist pattern 350 by the heat treatment is maintained in an amorphous structure, while the transparent conductive film 160a deposited in other areas is amorphous. It is changed from amorphous structure to poly structure.

Subsequently, as illustrated in FIG. 11G, the second photoresist pattern 380 is formed by performing an ashing process on the photoresist 380a using oxygen (O ₂ ) plasma, thereby forming the first photoresist. The transparent conductive film 160a formed on the resist pattern 350 is exposed.

After exposing the transparent conductive film 160a formed on the first photoresist pattern 350 as described above, as shown in FIG. 11H, the transparent conductive film exposed on the first photoresist pattern 350 ( 160a) is removed by wet etching.

In this case, the transparent conductive layer 160a having a poly structure among the transparent conductive layer 160a covered by the second photoresist 380 has an amorphous structure formed on the first photoresist pattern 350. It may not be removed due to the etching selectivity with the transparent conductive film 160a.

As described above, in the present invention, when the pixel electrode is formed by patterning the transparent conductive film 160a, the first and second photoresist patterns 350 and 380 are sequentially formed without using a conventional lift-off method to bake. As a result, the structure of the transparent conductive film 160a deposited on the first photoresist pattern 350 is different from that of the transparent conductive film 160a deposited in other regions, thereby controlling the etching selectivity. Although the undercut does not occur between the two through the difference in the etching selectivity, the conventional short generated during the patterning of the transparent conductive film 160a by easily etching only the transparent conductive film 160a deposited on the first photoresist pattern 350. Open defects caused by defects or foreign objects can be solved.

Subsequently, the remaining first and second photoresist patterns 350 and 380 are removed through a strip process, so that the pixel electrode 160, the gate pad upper electrode 182, and the data pad upper electrode (as shown in FIG. 11I) are removed. 192 and a second conductive pattern including a link electrode (not shown).

In this case, the pixel electrode 160 is formed to be adjacent to the gate line 120 with the gate insulating layer 125 and the semiconductor layers 134a and 135a interposed therebetween, thereby forming the storage capacitor 170.

The gate pad upper electrode 182 is connected to the gate pad lower electrode 181 through the first contact hole 151 passing through the semiconductor layers 134a and 135a and the gate insulating layer 125.

The data pad upper electrode 192 is connected to the data pad lower electrode 191 through the second contact hole 152 penetrating through the semiconductor layers 134a and 135a and the gate insulating layer 125.

In addition, the link electrode (not shown) is a data link lower electrode (not shown) extending from the gate pad lower electrode 191 through the third contact hole 153 penetrating through the semiconductor layers 134a and 135a and the gate insulating layer 125. And the data link upper electrode to be formed in a subsequent process.

After the second conductive pattern is formed as described above, as shown in FIGS. 12A and 12B, the third conductive pattern is formed through the third mask process. 12A and 12B are plan and cross-sectional views of a thin film transistor substrate on which a third conductive pattern is formed.

12A and 12B, semiconductor patterns 134 and 135, data lines 130, and data lines forming a channel on a substrate 110 on which a second conductive pattern is formed through a photolithography process using a third mask. A third conductive pattern including a source electrode 132 connected to the 130 and a drain electrode 133 facing the source electrode 132 with a channel interposed therebetween is formed.

More specifically, as illustrated in FIG. 13A, the data metal layer 130a is entirely deposited on the lower substrate 110 on which the second conductive pattern is formed.

Subsequently, the photoresist 450 is entirely deposited on the deposited data metal layer 130a, and then a photolithography process using a third mask 400, which is a diffraction exposure mask, is performed, thereby as shown in FIG. 13B. Photoresist patterns 450a and 450b having steps are formed.

Here, the third mask 400 includes a transflective portion 430 in a region where a channel portion is to be formed, a transmissive portion in a region where the pixel electrode 160 is formed and a region where the first and second contact holes 151 and 152 are to be formed. 410, and the other area is a diffraction exposure mask having a blocking portion 420.

As a result, the photoresist pattern 450b corresponding to the diffraction exposure portion of the third mask 400 is formed at a height lower than that of the photoresist pattern 450a formed in the other area.

After forming the photoresist pattern 450 having a step on the data metal layer 130a as described above, as shown in FIG. 13C, the pixel electrode (wet etching) is performed by performing wet etching on the exposed data metal layer 130a. 160, portions of the semiconductor layers 134 and 135 forming the storage capacitors, and portions of the semiconductor layers 1345 and 135 forming the gate pads and the data pads are exposed.

Subsequently, dry etching is performed on the exposed semiconductor layer as shown in FIG. 13D.

After performing dry etching on the exposed semiconductor layer as described above, as shown in FIG. 13E, an ashing process is performed on the photoresist pattern 450 using oxygen (O ₂ ) plasma. The photoresist pattern 450b covering the region to be opened is removed. In this case, as the photoresist pattern 450b is removed, the data metal layer 130 formed in the channel region of the thin film transistor is exposed.

In this case, a portion of the photoresist pattern 450a covering the region where the data line 130 is to be formed and the region where the storage capacitor 170 is to be formed is also removed by an ashing process using an oxygen (O ₂ ) plasma. .

Thereafter, the data metal layer 130 exposed by the ashed photoresist pattern 450a is removed by dry etching, so that the data metal layer 130 is removed from the source electrode 132 as shown in FIG. 13F. The n + amorphous silicon layer 135 formed in the channel region is exposed while separating the drain and drain electrodes 133.

As described above, the exposed n + amorphous silicon layer 135 is removed by dry etching to open the amorphous silicon layer 134, so that the source electrode 132 and the drain electrode are shown in FIG. 13G. An ohmic contact layer 135 and an active layer 134 for setting channels are formed between the 133.

At this time, in order to ensure the safety of the formed channel, as shown in Figure 13h, the exposed active layer of the channel portion is oxidized to form a channel protective film. This channel protection layer protects the active layer from moisture or scratches that may occur during subsequent processing.

Subsequently, by removing the remaining photoresist pattern 450a through the strip process, as shown in FIG. 13I, a semiconductor pattern forming a channel, a source electrode connected to the data line 130, and the data line 130 is formed. 132, a third conductive pattern including a drain electrode 133 facing the source electrode 132 and a data link upper electrode (not shown) with a channel interposed therebetween.

As described above, in the method of manufacturing a thin film transistor substrate according to the present invention, a second photoresist is additionally coated and baked after the transparent conductive film is deposited on the entire surface without using a conventional lift-off method during the transparent conductive film patterning. In addition, the structure of the transparent conductive film deposited on the first photoresist pattern is different from that of the transparent conductive film deposited in other regions, thereby controlling the etching selectivity. Through the difference in etching selectivity, even if there is no undercut between the transparent conductive film to be removed and the transparent conductive film to be retained, only the transparent conductive film to be removed is easily etched so that the pattern can be satisfactorily without short or open defects during patterning of the transparent conductive film. You can design.

In addition, the manufacturing method of the thin film transistor substrate according to the present invention can improve the manufacturing yield of the thin film transistor substrate by preventing short or open defects during the patterning of the transparent conductive film.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

Forming a first conductive pattern including a gate line, a gate electrode connected to the gate line, a gate pad lower electrode, and a data pad lower electrode on a substrate through a first mask process; After sequentially forming a gate insulating film and a semiconductor layer on the substrate on which the first conductive pattern is formed, the gate pad is penetrated through the gate insulating film and the semiconductor layer using a first photoresist pattern formed through a second mask process. Forming first and second contact holes exposing a lower electrode and the data pad lower electrode, and forming a pixel hole through the gate insulating layer and the semiconductor layer to expose the substrate; After the transparent conductive layer is entirely formed on the formed first and second contact holes and the pixel hole and the first photoresist pattern, the second photoresist pattern is formed on the first photoresist pattern using the second photoresist pattern formed through the ashing process. Forming a second conductive pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode by exposing and removing the transparent conductive film; After depositing the data metal layer on the substrate on which the second conductive pattern is formed, the source electrode is interposed between the semiconductor pattern for forming the channel, the data line, the source electrode connected to the data line, and the channel through a third mask process. And forming a third conductive pattern including a drain electrode opposite to the drain electrode. The method of claim 1, Forming the first conductive pattern, Depositing a gate metal layer over the substrate; Forming a photoresist pattern on the gate metal layer and then partially exposing the gate metal layer through a photolithography process using a first mask; Etching and patterning the gate metal layer exposed by the photoresist pattern; Removing the photoresist pattern remaining on the patterned gate metal layer through a strip process. The method of claim 1, Forming the second conductive pattern, Sequentially forming a semiconductor layer including a gate insulating layer, an active layer forming a channel, and an ohmic contact layer on the substrate on which the first conductive pattern is formed; Forming a first photoresist pattern by exposing the entire surface of the photoresist on the semiconductor layer and exposing a region where the first and second contact holes and the pixel hole are to be formed through a photolithography process using a second mask; Wow; Etching the regions exposed by the first photoresist pattern to form first and second contact holes and pixel holes; After forming a transparent conductive film over the first and second contact holes, the pixel hole and the first photoresist pattern, and forming a photoresist covering the transparent conductive film, the second photoresist pattern is formed through an ashing process. Exposing a transparent conductive film formed on the first photoresist pattern; Etching the transparent conductive film formed on the exposed first photoresist pattern; Removing the remaining first and second photoresist patterns through a strip process. The method of claim 1, Forming the third conductive pattern, Forming a data metal layer on the entire surface of the substrate on which the second conductive pattern is formed; Forming a photoresist pattern on the formed data metal layer by exposing the entire surface of the photoresist and then exposing a portion where the pixel electrode is formed through a photolithography process using a third mask but having a step in the channel portion;  Etching the data metal layer on the pixel electrode exposed by the photoresist pattern and then exposing the data metal layer formed on the channel portion through an ashing process; Sequentially etching and patterning the exposed data metal layer and an ohmic contact layer below the exposed data metal layer; Removing the photoresist pattern remaining on the patterned data metal layer through a strip process. The method of claim 1, And forming a storage capacitor between the gate line and the data metal layer to have a gate insulating layer and a semiconductor layer, wherein the storage capacitor is formed so that the semiconductor layer is laterally connected to the pixel electrode. Method of manufacturing a transistor substrate. The method of claim 3, wherein After the entire surface of the photoresist covering the transparent conductive film is formed, a step of performing a heat treatment to polyimide the transparent conductive film deposited in the pixel region before forming the second photoresist pattern through an ashing process A method of manufacturing a thin film transistor substrate, characterized in that. The method of claim 4, wherein After etching and patterning the data metal layer and the ohmic contact layer of the channel portion and exposing the active layer to form a channel, forming a channel passivation layer on the exposed active layer to secure the channel. Method of manufacturing a thin film transistor substrate.

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