KR20070069441A - Apparatus and method for real-time image reduction - Google Patents

Abstract

An apparatus and a method for reducing an image in real time are provided to process images within a short period by using a single line memory functioning as an accumulator. An apparatus for reducing an image includes a first line memory(430), an image reduction unit(410), a sub-sampling unit(420), and a second line memory(440). The first line memory accumulates and stores inputted images. The image reduction unit accumulates an inputted image in the first line memory such that the inputted image is reduced at a predetermined rate and outputs the reduced image. The sub-sampling unit interpolates the image output from the image reduction unit at a predetermined rate to reduce the image. The second line memory stores the output of the sub-sampling unit.

Description

Apparatus and method for real-time image reduction

1 is a block diagram of a conventional video reduction apparatus;

2 is an exemplary view for explaining a conventional image reduction apparatus to reduce an image;

3A is a conceptual diagram illustrating the operation of a general line memory;

3B is a conceptual diagram for explaining the operation of the line memory used in the conventional LPF;

4 is a structural diagram of an embodiment of a real-time image reduction apparatus according to the present invention;

FIG. 5 is a schematic diagram illustrating that the sub-sampling unit of FIG. 4 performs sampling;

6 is an exemplary view for explaining that an image reduction apparatus of the present invention reduces an image;

7 is a structural diagram of another embodiment of a real-time image processing apparatus of the present invention;

7 and 8 are structural diagrams of another embodiment of the real-time image processing apparatus of the present invention.

<Explanation of symbols for the main parts of the drawings>

410: Image reduction unit 420: Sub sampling unit

430, 440: line memory

The present invention relates to a real-time image reduction apparatus and method, and more particularly to a real-time image reduction apparatus and method for use in an image processing system.

In general, the real-time image reduction method refers to a technique for continuously reducing the image received from the sensor.

1 is a block diagram of a conventional image reduction apparatus.

As shown in the figure, a conventional image reduction apparatus includes a low pass filter (hereinafter, simply referred to as 'LPF') 110, a sub-sampling 120, and an LPF 110. It includes a line memory 130 to 160 for storing data passing through) and a line memory 170 for storing data passing through the sub-sampling unit 120.

In the conventional image reduction apparatus, in order to reduce deterioration of image quality of the reduced image, the sub-sampler 120 reduces the image that has passed through the LPF 110 through interpolation.

In order to obtain a good quality image in this way, a sufficient polynomial LPF 110 must be used, and a large number of multipliers are used when implementing a logic circuit, and also LPF 110 does not distort the screen. In order to use a finite impulse response (FIR) LPF 110 using coefficients of {1, 3, 8, 3, 1}, etc., at least four or more line memories are required, which increases the volume of the system. There is a problem in that power consumption increases.

The present invention has been proposed to solve the above problems, and by using a single line memory that serves as an accumulator, a real-time image reduction apparatus and method for processing an image in a short time with less data bus occupancy The purpose is to provide.

In order to achieve the above object, according to a preferred embodiment of the present invention, a first line memory for accumulating and storing the input image; An image reduction unit for accumulating the input image in the first line memory to reduce the input image at a predetermined ratio and outputting the reduced image; And a subsampling unit for interpolating and reducing the image output from the image reducing unit according to a predetermined ratio, and further comprising a second line memory for storing the output of the subsampling unit.

In this case, the first and second line memories are preferably vertical line static memories (SRAMs), and a predetermined ratio of the image reduction unit is reduced to 2 ⁿ (n is an integer of 1 or more). It is preferable.

Further, according to another embodiment of the present invention, accumulating and storing the input image in the line memory to be reduced to a predetermined ratio; Outputting a reduced image; And interpolating and reducing the reduced image according to a predetermined ratio.

Here, it is preferable that the line memory is a vertical line SRAM, and the predetermined ratio of reducing the video is 2 ⁿ (n is an integer of 1 or more).

On the other hand, according to another embodiment of the present invention, in the image processor of the imaging device for reducing the image in real time, the input image is accumulated in the first line memory to be reduced to a predetermined ratio, and output the reduced image An image reduction unit for interpolating and reducing the output image according to a predetermined ratio; And a line memory for accumulating and storing an input image.

Prior to the description of the present invention, the operation of the general line memory and the operation of the line memory of FIG. 1 will be described first.

2 is an exemplary diagram for explaining a conventional image reduction apparatus to reduce an image.

As shown in the figure, when 210 image data is input to the image reduction apparatus of the present invention and the LPF 110 prevents deterioration of image quality, the filtered image is output as shown in 220. Thereafter, when the subsampling unit 120 reduces the image by interpolation, the reduced image data such as 230 is output.

3A is a conceptual diagram illustrating the operation of a general line memory, and FIG. 3B is a conceptual diagram illustrating the operation of a line memory used in a conventional LPF.

Referring to FIG. 3A, an image is input from A, and stored in 130, 140, 150, and 170 line memories, respectively, according to a direction indicated by a dotted line, and finally, 5 lines are input to the LPF 110. As shown in FIG. 1, when the 5-tap LPF {1, 3, 8, 3, 1} / 16 is applied in the vertical direction, the image processing may be performed in real time when the information has four lines.

At this time, the output at the current t is as follows in the system using the conventional four-line memory.

은 입력 함수이며,

은 출력함수이다. 이

이 LPF(110)의 입력이 된다. 이와 같은 종래의 기술에 따르면, 이전에 저장된 결과값이 현재에 적용될 수 없으므로, 이전 4라인을 저장하고 있어야 하며, 이에 따라 시스템의 부피가 커지고, 전력 소모량이 많아지게 된다. At this time,

Is an input function,

Is the output function. this

The LPF 110 is input. According to this conventional technique, since previously stored results cannot be applied at present, the previous four lines should be stored, thereby increasing the volume of the system and increasing power consumption.

 The present invention simplifies the system by using one line memory to act as an accumulator.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even if displayed on different drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a structural diagram of an embodiment of a real-time image reduction apparatus according to the present invention.

As shown in the figure, the image reduction apparatus of the present invention includes an image reduction unit 410, a sub sampling unit 420, a first line memory 430, and a second line memory 440.

The image reduction unit 410 reduces and outputs the input image to 2 ⁿ (n is an integer of 1 or more). This is possible by the first line memory 430 having a single line size that functions as an accumulator. In this case, the first line memory may be a vertical line static random access memory (hereinafter, simply referred to as 'SRAM').

In the case where the first line memory 430 is 8 bits x (line length), assuming that the input is Y (t) [7: 0], the input image is to be reduced by 2 times. Let's explain.

When the current time is called (t) and the previous time is (t-1), the first line memory 430 stores Y (t-1) [7: 1] in the (t-1) line. (I.e., save the half result) and add Y (t) [7: 1] to Y (t-1) [7: 1]. Then, a result value of 0.5Y (t) + 0.5Y (t-1) can be obtained, and the image reduction unit 410 can obtain a reduced image of 2 times.

For example, if the image is to be reduced 4 times, the first line memory 430 stores Y (t-3) [7: 2] in the (t-3) line (that is, 1/4 The result value (0.25Y (t-3)) and Y (t-2) [7: 2] in the (t-2) line. And store (0.25 Y (t-2) + 0.25 Y (t-3)). In the line (t-1), Y (t-1) [7: 2] is added to the stored result and stored (0.25Y (t-1) + 0.25Y (t-2) + 0.25Y (t-3). Save). Finally, in line (t), Y (t) [7: 2] is summed with the stored result. Finally, the result is 0.25Y (t) + 0.25Y (t-1) + 0.25Y (t-2) + 0.25Y (t-3), which is a 4x reduction of the image.

In addition, when the image is to be reduced by 8 times, Y (t-7) [7: 3] is stored in the (t-7) line in the first line memory 430 (that is, the result of 1/4) (Y25t [7: 3]) and Y (t-6) [7: 3] on the (t-6) line and save Y (t-7) [7: 3]. (Save 0.125Y (t-7) + 0.125Y (t-6)). In the (t-5) line, Y (t-5) [7: 3] is stored with the result stored (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) ) Save). In the (t-4) line, Y (t-4) [7: 3] is added to the stored result and stored (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) ) + 0.125Y (t-4) storage). In the (t-3) line, Y (t-3) [7: 3] is added to the stored result (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) ) + 0.125Y (t-4) + 0.125Y (t-3) storage). In the line (t-2), Y (t-2) [7: 3] is added to the stored result and stored (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) ) + 0.125Y (t-4) + 0.125Y (t-3) + 0.125Y (t-2) storage). In the (t-1) line, Y (t-1) [7: 3] is added to the stored result and stored (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) ) + 0.125Y (t-4) + 0.125Y (t-3) + 0.125Y (t-2) + 0.125Y (t-1)). Finally, in line (t), Y (t) [7: 3] is summed with the result stored (0.125Y (t-7) + 0.125Y (t-6) + 0.125Y (t-5) + 0.125 Y (t-4) + 0.125Y (t-3) + 0.125Y (t-2) + 0.125Y (t-1) + 0.125Y (t)).

In this manner, the image reduction unit 410 may reduce the image in multiples of 2 ⁿ .

Meanwhile, when the first line memory 430 is 12 bits x (line length), the image reduction unit 410 may perform image reduction in another manner.

Similarly, if the input is Y (t) [7: 0], and the image is to be reduced to 1/2, the line (t-1) stores Y (t-1) [7: 0] ( That is, the half value is stored), and Y (t) [7: 0] is added to Y (t-1) [7: 0] in the line (t), and then [8: 1] Outputs In this case, the output is {Y (t) + Y (t-1)} / 2. That is, a 2x reduced image is output.

In addition, when the image is reduced to 1/4, Y (t-3) [7: 0] is stored in the (t-3) line (that is, the 1/4 result is stored), and (t-2 In the line, Y (t-2) [7: 0] is added to the stored result (Y (t-2) + Y (t-3)). In the (t-1) line, Y (t-1) [7: 0] is added to the stored result (Y (t-1) + Y (t-2) + Y (t-3)). . In line (t), Y (t) [7: 0] is summed with the stored result and [9: 2] is output. This output is {Y (t) + Y (t-1) + Y (t-2) + Y (t-3)} / 4, which is 1/4 of the image.

In this way, if you want to reduce the image by 8 times, you can finally output [10: 3] and output {Y (t-7) + Y (t-6) + Y (t-5) + Y (t -4) + Y (t-3) + Y (t-2) + Y (t-1) + Y (t)} / 8 can be obtained.

According to the present invention, the image reduced in 2 ⁿ (n is an integer greater than or equal to 1) may be obtained and output to the sub-sampling unit 420.

The sub sampling unit 420 selects pixels to reduce the image. That is, the pixels are selected and stored according to the ratio in the input image.

FIG. 5 is a schematic diagram illustrating an example in which the sub-sampling unit of FIG. 4 performs sampling.

As shown in the figure, the sub-sampling unit 420 of the present invention performs interpolation on a predetermined ratio of pixels in an input image such as A to reduce an image. 5 shows that only six pixels are output for nine samples. The ratio of output pixels to input pixels may depend on the performance of the system.

The second line memory 440 stores a result of the sub sampling performed by the sub sampling unit 430. The second line memory 440 is also preferably a vertical line SRMA.

As described above, in the image reduction apparatus of the present invention, the image reduction unit 410 reduces the image according to a predetermined reduction ratio, and then causes the sub-sampling unit 420 to reduce the image according to the sub-sampling ratio. do.

6 is an exemplary view for explaining the reduction of the image by the image reduction device of the present invention.

As shown in the figure, the image data 610 input according to the present invention is reduced by the image reduction unit 410 according to a predetermined reduction ratio, so that data of 620 is output, and then the sub-sampling unit. The image 420 may further reduce the image according to the sub-sampling ratio, thereby obtaining the reduced image data 630.

7 and 8 are structural diagrams of another embodiment of the real-time image processing apparatus of the present invention.

Referring to FIG. 7, the order of the image reduction unit 410 and the sub-sampling unit 420 of FIG. 4 is changed. In the present invention, image reduction may be performed by changing the order of the two devices. will be.

In addition, referring to FIG. 8, two image reduction units 410 of FIG. 4 are used, and a plurality of image reduction units 410 may be arranged and used according to a reduction ratio.

It is a measure of the image reduction result that the information of the original image is not lost. In this regard, the conventional image reduction method as shown in FIG. 1 has a good result, but this method is not suitable for real-time image reduction method because it is processed using a frame memory due to the size limitation of hardware.

According to the present invention, since the method of reducing the image is simply implemented in two steps, and the frame memory does not need to be used, real-time image reduction may be possible.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention as described above, by reducing the line memory, there is an effect to reduce the cost by minimizing the logic circuit, there is an effect to reduce the power consumption through the simplification of the logic circuit. In addition, since the use of the frame memory is unnecessary, it is possible to reduce an image in real time and to obtain a reduced image of good quality.

Claims (8)

A first line memory for accumulating and storing an input image; An image reduction unit for accumulating the input image in the first line memory to reduce the input image at a predetermined ratio and outputting the reduced image; And And a sub-sampling unit for interpolating and reducing the image output from the image reduction unit according to a predetermined ratio. The image reduction device of claim 1, further comprising a second line memory for storing an output of the sub-sampler. The image reduction device according to claim 1 or 2, wherein the first and second line memories are vertical line static memory (SRAM). The image reduction device according to claim 1, wherein a predetermined ratio of the image reduction unit is 2 ⁿ (n is an integer of 1 or more). Accumulating and storing the input image in a line memory to reduce the input image at a predetermined ratio; Outputting a reduced image; And And reducing the interpolated image by the interpolation according to a predetermined ratio. The method of claim 5, wherein the line memory is a vertical line SRAM. The image reduction method according to claim 5, wherein the predetermined ratio of reducing the image is 2 ⁿ (n is an integer of 1 or more). An image processor of an imaging device that reduces an image in real time, An image reduction unit configured to accumulate an input image in the first line memory to reduce the input image at a predetermined ratio, output a reduced image, and reduce the output image by interpolating the output image according to a predetermined ratio; And An image processor including a line memory for accumulating and storing the input image.

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