KR20070068778A - Driver and liquid crystal display apparatus comprising the same - Google Patents

Abstract

A driver and an LCD(Liquid Crystal Display) device having the same are provided to reduce a manufacturing cost by determining the level of a gate-on voltage according to the voltage level of a pulse signal. A driver of an LCD device includes a voltage level adjusting unit, a gate-on voltage generator(740), and a gate-off voltage generator(760). The voltage level adjusting unit, which has a resistance divider including resistors(R1,R2), distributes a first voltage pulse signal(PULSE1), and supplies a second voltage pulse signal(PULSE2). The gate-on voltage generator outputs a gate-on voltage(Von) by shifting the voltage level of the second voltage pulse signal to a first input voltage level. The gate-off voltage generator outputs a gate-off voltage(Voff) by shifting the voltage level of the second voltage pulse signal to a second input voltage level.

Description

Driving device and liquid crystal display including the same

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a circuit diagram of the basic gray voltage generator of FIG. 1.

4 is a circuit diagram of a gate-on voltage generator of FIG. 1.

5 is a circuit diagram of the gate-off voltage generator of FIG. 1.

(Explanation of symbols for the main parts of the drawing)

10: liquid crystal display device 100: first display panel

150: liquid crystal layer 200: second display panel

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

700: driving device 720: basic gray voltage generator

740: gate-on voltage generator 760: gate-off voltage generator

800: gray voltage generator

The present invention relates to a driving apparatus and a liquid crystal display including the same, and more particularly, to a driving apparatus capable of reducing manufacturing costs and a liquid crystal display including the same.

The liquid crystal display device drives a first display panel including a pixel electrode, a second display panel including a common electrode, a liquid crystal layer having dielectric anisotropy injected between the first display panel and the second display panel, and a plurality of gate lines. A gate driver, a data driver for outputting a data signal, and a driving device for generating and outputting a basic gray voltage and gate turn-on and turn-off voltages.

The gate on and off voltage generators that generate the gate turn on and off voltages use a charge pump method using a pulse signal applied from the outside. A gate turn on voltage of 17V and a gate turn off of -5V are typically used. Generate voltage. However, when it is necessary to apply a larger gate turn on voltage and a lower gate turn off voltage, it is necessary to adjust the levels of the gate turn on and off voltages.

The level of gate turn on and off voltage is adjusted using a plurality of diodes and optional resistors. That is, when a forward voltage is applied to the diode, a voltage drop of about 0.7 V occurs. By using the plurality of diodes, a predetermined voltage level is dropped from the voltage of the external pulse signal, and a voltage drop pulse signal is applied. To generate gate on and off voltages. Here the optional resistor is connected in parallel to the diode to adjust the voltage drop level.

According to this prior art, the driving apparatus requires a plurality of diodes and optional resistors, thereby increasing the manufacturing cost of the driving apparatus or the liquid crystal display. Accordingly, there is a need to provide a driving device or a liquid crystal display device that can reduce manufacturing costs.

An object of the present invention is to provide a driving device and a liquid crystal display including the same, which can reduce manufacturing costs.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The driving device and the liquid crystal display according to an exemplary embodiment of the present invention provide a second voltage pulse signal by distributing a first voltage pulse signal by using a resistor divider having a plurality of resistors connected thereto. A voltage level adjusting unit, a gate on voltage generator for shifting the voltage level of the second voltage pulse signal at the voltage level of the first input voltage, and outputting a gate turn-on voltage, and a second voltage pulse signal at the voltage level of the second input voltage And a gate off voltage generator configured to output a gate turn off voltage by shifting a voltage level of the gate voltage.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. And a gray voltage generator 800 connected to the signal, and a signal controller 600 and a driver 700 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G1 -Gn and D1 -Dm and a plurality of pixels PX connected to the display signal lines G1 -Gn and D1 -Dm and arranged in a matrix form. 2, the liquid crystal panel assembly 300 includes a first display panel 100, a second display panel 200, and a liquid crystal layer 150 interposed therebetween.

The display signal lines G1 -Gn and D1 -Dm include a plurality of gate lines G1 -Gn for transmitting a gate signal and a plurality of data lines D1 -Dm for transmitting a data signal. The gate lines G1-Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend substantially in the column direction and are substantially parallel to each other.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays three primary colors over time (time division) so that the spatial or temporal matching of these three primary colors is performed. To recognize the desired color. Examples of primary colors include red, green and blue.

2 illustrates an equivalent circuit for one pixel of a liquid crystal display as an example of spatial division. The color filter CF may be formed in a portion of the common electrode CE of the second display panel 200 to face the pixel electrode PE of the first display panel 100. Each pixel, for example, a pixel connected to the i-th (i = 1, 2, ..., n) gate line Gi and the j-th (j = 1, 2, ..., m) data line Dj, is connected to the signal line Gi. , A first switching element Q connected to Dj, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The holding capacitor Cst can be omitted as necessary.

Meanwhile, the gate driver 400 of FIG. 1 is connected to the gate lines G1 -Gn, so that the gate-on voltage Von and the gate-off voltage Voff from the gate on / off voltages Von and Voff generator 770 are provided. ) Is applied to the gate lines G1 -Gn.

The gate driver 400 applies the gate-on voltage Von from the gate-on voltage generator 740 to the gate lines G1 -Gn according to the gate control signal CONT1 from the signal controller 600, thereby providing a gate line ( The first switching device Q of FIG. 2 connected to G1-Gn is turned on. Then, the data signal applied to the data lines D1 -Dm is applied to the pixel PX through the turned-on first switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is charged in the liquid crystal capacitor Clc to serve as the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage. Accordingly, the polarization of the light passing through the liquid crystal layer 150 changes, thereby displaying an image.

The data driver 500 is connected to the data lines D1 -Dm of the liquid crystal panel assembly 300 to select a gray voltage corresponding to data from the gray voltage generator 800, and uses the selected gray voltage as the data voltage. To apply. Here, when the gray voltage generator 800 does not provide all the voltages for all grays, but only the basic gray voltages, the data driver 500 divides the basic gray voltages to generate gray voltages for all grays. The data voltage can be selected from among them.

The gate driver 400 or the data driver 500 may be mounted directly on the liquid crystal panel assembly 300 in the form of a plurality of driving integrated circuit chips, or may be mounted on a flexible printed circuit film (not shown). The liquid crystal panel assembly 300 may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package. Alternatively, the gate driver 400 or the data driver 500 may be integrated in the liquid crystal panel assembly 300 together with the display signal lines G1 -Gn and D1 -Dm and the first switching element Q.

The signal controller 600 receives the input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsinc, a vertical sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input image signals R, G, and B and the input control signal, and generates the gate control signal CONT1 by the gate driver 400. ), The data control signal CONT2 and the video signal DAT are sent to the data driver 500.

Meanwhile, the driving apparatus 700 of FIG. 1 includes a basic gray voltage generator 720, a gate on voltage generator 740, and a gate off voltage generator 760.

The basic gray voltage generator 720 generates a basic gray voltage AVDD for generating a plurality of levels of gray voltage and provides the gray voltage to the gray voltage generator 800, and the gate on and off voltage generators 740 and 760. ) Receives the second pulse signal PULSE2 and outputs gate on and off voltages Von and Voff.

The resistors R1 and R2 connected in series are voltage dividers and are connected between the terminal to which the first pulse signal PULSE1 is applied and the ground. The gate on and off voltage generators divide the voltage levels of the first pulse signal PULSE1 generated by the basic gray voltage generator 720 according to the ratio of the resistors R1 and R2. 740, 760. Here, the voltage level of the gate on and off voltages is adjusted according to the voltage level of the second pulse signal PULSE2. The voltage level of the second pulse signal PULSE2 can be adjusted by the resistors R1 and R2 having low unit costs. The manufacturing cost of the driving device or the liquid crystal display device can be reduced. However, instead of using the voltage pulse signal PULSE1, the second voltage pulse signal PULSE2 may use a pulse signal having a predetermined voltage level applied from the outside.

Meanwhile, detailed operations and circuits of the basic gray voltage generator 720 and the gate on and off voltage generators 740 and 760 will be described later with reference to FIGS. 3 to 5.

The gray voltage generator 800 receives the basic gray voltage AVDD from the basic gray voltage generator 720 and generates a gray voltage. The gray voltage generator 800 includes a plurality of resistors connected in series between the node to which the basic gray voltage AVDD is applied and the ground, and distributes the voltage level of the driving voltage to generate the gray voltage, but not illustrated. Did. The internal circuit of the gray voltage generator 800 is not limited thereto, and may be variously implemented.

The common voltage generator (not shown) generates a common voltage Vcom and provides it to the liquid crystal panel assembly 300. The common voltage generator (not shown) may generate a common voltage by voltage-dividing the basic gray voltage AVDD through a voltage divider.

3 is a circuit diagram of the basic gray voltage generator 720 of FIG. 1.

Referring to FIG. 3, the basic gray voltage generator 720 includes an inductor L to which the first input voltage Vin1 is applied, an anode connected to the inductor L, and an output terminal of the basic gray voltage AVDD. The clock signal CLK is connected between the first diode D0 to which the cathode is connected, the first capacitor C0 connected between the first diode D0 and the ground, and the anode terminal of the first diode D0 to ground. A second switching device (SW) that is turned on / off according to.

Referring to the operation, when the second switching element SW is turned on by the clock signal CLK, the first input voltage is applied across the inductor L according to the current and voltage characteristics of the inductor L. In proportion to Vin1, the current I _L flowing in the inductor _L is gradually increased. In this case, the longer the time that the second switching device SW is on, the current I _L flowing through the inductor L increases. At this time, the basic gray voltage AVDD is outputted with the voltage charged in the first capacitor C0.

When the second switching device SW is turned off, the current I _L flowing through the inductor L flows through the first diode D0 and according to the current and voltage characteristics of the first capacitor C0. The voltage is charged to the capacitor C0. Therefore, the first input voltage Vin1 is boosted to a predetermined voltage and output as the basic gray voltage AVDD.

Here, the first voltage pulse signal PULSE1 is output, and when the second switching element SW is on, it is 0 volts, and when it is off, the first voltage pulse signal PULSE1 is a pulse signal having a voltage level of the basic gray level voltage AVDD. The first voltage pulse signal PULSE1 is provided to the resistor divider of FIG. 1.

4 is a circuit diagram of the gate-on voltage generator 740 of FIG. 1.

Referring to FIG. 4, the gate-on voltage generator 740 includes a second diode D1 having an anode connected to the first input voltage node N1 and a cathode connected to the first pulse input node N2, and a first diode. A third diode D2 having an anode connected to the pulse input node N2 and a cathode connected to the first output voltage node N3, and a second voltage pulse signal PULSE2 provided to the first pulse input node N2. It includes a third capacitor (C2).

Here, the second input voltage Vin2 is applied to the first input voltage node N1 and the first output voltage node N3 outputs the gate-on voltage Von.

If the operation is ignored while the voltage drop when the forward voltage is applied to the second and third diodes D1 and D2 is described, the voltage level of the second voltage pulse signal PULSE2 is equal to the voltage of the second input voltage Vin2. During the time higher than the level, that is, during the time when the second voltage pulse signal PULSE2 is at the high level, the second diode D1 is not connected with the reverse voltage applied, and the third diode D2 with the forward voltage applied is turned on. The voltage corresponding to the potential difference between the second input voltage Vin and the second voltage pulse signal PULSE2 is charged in the second capacitor C1 and the third capacitor C2.

Next, during the time when the voltage level of the second voltage pulse signal PULSE2 is lower than the voltage level of the second input voltage Vin2, that is, when the second voltage pulse signal PULSE2 is 0 volts, the third diode D2. The second diode D1 to which the reverse voltage is applied and not conducting, and the forward voltage is applied, is conducting to maintain the voltage charged in the second capacitor C1, and the second input voltage Vin is applied to the third capacitor C2. ) Is charged.

When the second voltage pulse signal PULSE2 becomes high again, the second diode D1 is not conductive and the third diode D2 is conductive so that the voltage level of the second voltage pulse signal PULSE2 and the third capacitor ( The voltage in which the voltage levels of the second input voltage Vin2 charged in C2 is added together is charged in the second capacitor C1.

Through this process, the voltage level of the first output voltage node N3 is shifted by the voltage level of the second voltage pulse signal PULSE2 at the voltage level of the second input voltage Vin2 to output the gate-on voltage Von. .

That is, the voltage level of the second voltage pulse signal PULSE2 determines the level of the gate-on voltage Von, and the voltage level of the second voltage pulse signal PULSE2 is the resistance R1 of FIG. R2). Therefore, the manufacturing cost of the driving device or the liquid crystal display device is reduced.

The second input voltage Vin2 may use a voltage divided by the basic gray voltage AVDD of FIG. 1 using a resistor divider or the like, or a separate voltage may be applied from the outside.

5 is a circuit diagram of the gate-off voltage generator of FIG. 1.

Referring to FIG. 5, the gate-off voltage generator 740 may include a fourth diode D3 having a cathode connected to the second input voltage node N4 and an anode connected to the second pulse input node N5, and a second A fifth diode D4 having a cathode connected to the pulse input node N5 and an anode connected to the second output voltage node N6, and a second voltage pulse signal PULSE2 provided to the second pulse input node N5. It includes a fifth capacitor (C4).

Here, the second input voltage node N2 is applied with the third input voltage Vin3 and the second output voltage node N6 outputs the gate off voltage Voff.

If the voltage drop in the case where the forward voltage is applied to the fourth and fifth diodes D3 and D4 is ignored and the voltage of the third input voltage Vin3 is 0 volts, the operation will be described as an example. During the time when the signal PULSE2 is at the high level, the fifth diode D4 is not conducting with the reverse voltage applied thereto, and the fourth diode D3 with the forward voltage applied is conducting to the second voltage pulse signal PULSE2. The voltage is charged in the fourth capacitor C3 and the fifth capacitor C4.

Next, during the time when the second voltage pulse signal PULSE2 is 0 volts, the fourth diode D3 and the fifth diode D4 are not conductive and the voltage charged in the fourth capacitor C3 is maintained.

When the second voltage pulse signal PULSE2 becomes high again, the fifth diode D4 is not conductive and the fourth diode D3 is conductive so that the voltage of the second voltage pulse signal PULSE2 becomes the fourth capacitor C3. ) Is charged.

Through this process, the voltage level of the second output voltage node N6 is shifted by the voltage level of the second voltage pulse signal PULSE2 from 0V, which is the voltage level of the third input voltage Vin2, so that the gate-off voltage Voff is increased. Is output.

That is, the voltage level of the second voltage pulse signal PULSE2 determines the level of the gate-off voltage Voff, and the voltage level of the second voltage pulse signal PULSE2 is the resistors R1 and R2 of FIG. Is adjusted. Therefore, the manufacturing cost of the driving device or the liquid crystal display device is reduced.

Although one embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the driving apparatus and the liquid crystal display including the same, the manufacturing cost may be reduced.

Claims (9)

A voltage level adjusting unit configured to distribute a first voltage pulse signal to provide a second voltage pulse signal by using a resistor divider having a plurality of resistors connected thereto; A gate-on voltage generator for outputting a gate-on voltage by shifting the voltage level of the second voltage pulse signal at a voltage level of a first input voltage; And And a gate off voltage generator configured to shift a voltage level of the second voltage pulse signal at a voltage level of a second input voltage to output a gate off voltage. The method of claim 1, The resistor divider includes a plurality of resistors connected in series between a node to which the first voltage pulse signal is applied and ground. The method of claim 1, The gate-on voltage generator includes a first diode having an anode connected to a first input voltage node and a cathode connected to a first pulse input node, and an anode connected to the first pulse input node and a cathode connected to a first output voltage node. A second diode, a first capacitor connected between the first input voltage node and the first output voltage node, and a second capacitor providing the second voltage pulse signal to the first pulse input node; The first input voltage node is a driving device of the liquid crystal display device to which the first input voltage is applied. The method of claim 1, The gate-off voltage generator includes a third diode having a cathode connected to a second input voltage node and an anode connected to a second pulse input node, a cathode connected to a second pulse input node, and an anode connected to a second output voltage node. A fourth diode, a third capacitor connected between the second input voltage node and the second output voltage node and a fourth capacitor providing the second voltage pulse signal to the second pulse input node; The input voltage node is a driving device of the liquid crystal display device to which the second input voltage is applied. A basic gradation voltage generator for boosting a voltage level of the first input voltage according to an external clock signal to output a basic gradation voltage, and outputting a first voltage pulse signal whose voltage level changes according to the external clock signal; A voltage level adjuster configured to distribute the first voltage pulse signal to provide a second voltage pulse signal by using a resistor divider having a plurality of resistors connected thereto; A gate-on voltage generator for outputting a gate turn-on voltage by shifting a voltage level of the second voltage pulse signal at a voltage level of a second input voltage; And And a gate off voltage generator configured to shift a voltage level of the second voltage pulse signal at a voltage level of a third input voltage to output a gate turn-off voltage. The method of claim 5, The resistor divider includes a plurality of resistors connected in series between a node to which the first voltage pulse signal is applied and ground. The method of claim 5, The gate-on voltage generator includes a first diode having an anode connected to a first input voltage node and a cathode connected to a first pulse input node, and an anode connected to a first pulse input node and a cathode connected to a first output voltage node. A second diode, a first capacitor coupled between the first input voltage node and the first output voltage node and a second capacitor providing the second voltage pulse signal to the first pulse input node; An input voltage node is a driving device of a liquid crystal display device to which the first input voltage is applied. The method of claim 5, The gate-off voltage generator includes a third diode having a cathode connected to a second input voltage node and an anode connected to a second pulse input node, a cathode connected to a second pulse input node, and an anode connected to a second output voltage node. A fourth diode, a third capacitor connected between the second input voltage node and the second output voltage node and a fourth capacitor providing the second voltage pulse signal to the second pulse input node; The input voltage node is a driving device of the liquid crystal display device to which the second input voltage is applied. A liquid crystal panel assembly in which a plurality of gate lines and data lines are formed to display a predetermined image; A drive device according to any one of claims 1 to 8; A gate driver configured to receive gate turn on and turn off voltages from the driving device to drive the plurality of gate lines; And And a data driver for applying data voltages to the plurality of data lines.

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