KR20070055289A - Semiconductor device with improved refresh properties and method of forming the same - Google Patents

Abstract

Provided are a semiconductor device having improved refresh characteristics and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate having an active region defined by an isolation region, a gate electrode formed in an active region of the semiconductor substrate, a first impurity region formed in the semiconductor substrate and adjacent to one side of the gate electrode, and positioned below the first impurity region And a barrier layer formed in the semiconductor substrate and a second impurity region adjacent to the other side of the gate electrode and formed in the semiconductor substrate.

Refresh, Barrier Layer, Recess

Description

Semiconductor device with improved refresh properties and method of forming the same}

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment of the present invention.

4A through 6 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

 (Explanation of symbols for the main parts of the drawing)

120 device isolation layer 121 active region

160: barrier layer 130: first impurity region

140, 141: second impurity region

211: gate oxide film on recessed semiconductor substrate

325 sidewall spacer 330 epitaxial layer

340 structure of the recessed semiconductor substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having improved refresh characteristics and a manufacturing method thereof.

Recently, as the degree of integration of semiconductor devices increases, problems such as driving force of the device decreases and power losses increase during the operation process, thus increasing the need for semiconductor devices having excellent static refresh characteristics.

The main reason for the necessity of the refresh operation is the junction leakage current between the semiconductor substrate and the impurity region defined in the semiconductor substrate and connected to the storage node contact, and the leakage in such a junction profile. The path causes a decrease in the refresh characteristics of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of obtaining more improved refresh characteristics by blocking a main generation path of leakage current or reducing the generation degree of leakage current.

Another object of the present invention is to provide a method of manufacturing such a semiconductor device.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with an aspect of the present invention, a semiconductor device includes a semiconductor substrate, a gate electrode formed in an active region of the semiconductor substrate, a first impurity region adjacent to one side of the gate electrode, and formed in the semiconductor substrate; The semiconductor device may include a barrier layer formed under the first impurity region and adjacent to the other side of the gate electrode, and a second impurity region formed in the semiconductor substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which provides a semiconductor substrate in which an active region is defined by an isolation region, and forms a trench in the active region of the semiconductor substrate. Forming a barrier layer on a bottom surface of the trench, forming an epitaxial layer filling the trench, forming a gate electrode adjacent to one side of the epitaxial layer on the semiconductor substrate, and forming impurities in the semiconductor substrate. Implanting a second impurity region into the epitaxial layer adjacent to one side of the gate electrode to form a second impurity region in the semiconductor substrate facing the first impurity region and the first impurity region and adjacent to the other side of the gate electrode. .

Specific details of other embodiments related to the present invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are to make the disclosure of the present invention complete, and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings in order to describe the present invention in more detail.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1. 1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. As illustrated in FIG. 1, the semiconductor device 1 may include a semiconductor substrate 110, a gate electrode 220, a first impurity region 130, a barrier layer 160, and a second impurity region 140. Include.

The semiconductor substrate 110 may be a p-type or n-type type in which an active region 121 is defined and electrically separated by a device isolation region 120 (STI).

A structure in which the gate oxide layer 210, the gate electrode 220, and the hard mask layer 230 are stacked is formed on the semiconductor substrate 110, and the spacer 240 is formed on the side of the stacked structure. The gate electrode 220 may use polysilicon, silicon implanted with impurities, or a metallic conductive film. Here, as the metallic conductive film, for example, a material made of W, WN, TaN, RuO, NiTa, Co, Pt, Cr, Mo ₂ N, and a combination thereof may be used. For example, silicon nitride (SiN) may be used for the hard mask layer 230 and the spacer 240.

The first impurity region 130 is defined at one side of the gate electrode 220, and the barrier layer 160 is positioned under the first impurity region 130. The barrier layer 160 blocks a path in which leakage current occurs from the first impurity region 130 connected to the storage node contact (not shown) during the operation of the semiconductor device 1 to the active region 121 of the semiconductor substrate. To improve the refresh characteristics. Meanwhile, the second impurity region 140 is disposed in the semiconductor substrate facing the first impurity region and adjacent to the other side of the gate electrode.

2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 2, a semiconductor device 2 according to another embodiment of the present invention may include a gate oxide film 211, a gate electrode 220, and a hard mask film 230 formed on a recessed surface of a semiconductor substrate. Include. Since the recess structure increases the resistance of the channel, the degree of leakage current in the channel direction may be reduced in the first impurity region 130 connected to the storage node contact. Meanwhile, components of the remaining semiconductor devices, which are not described herein, are as described with reference to FIG. 1.

3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 3, the semiconductor device 3 according to another exemplary embodiment of the present inventive concept includes a second impurity region 141 having an impurity implantation stronger than the second impurity region 140 of FIGS. 1 and 2. . When the impurity region 141 is formed in an asymmetrical concentration and distribution region of the impurity region as compared to the first impurity region 130, the thickness of the channel region is increased to reduce the resistance of the channel during operation of the semiconductor device. The refresh characteristic is excellent. Meanwhile, components of the remaining semiconductor device, which are not mentioned herein, are substantially the same as the semiconductor device described with reference to FIG. 1.

The above-described semiconductor device of the present invention is only an embodiment, and the present invention is not limited thereto and may be variously modified according to the field to which the semiconductor device of the present invention is applied.

Hereinafter, a method of manufacturing a semiconductor device having the structure of FIG. 1 will be described with reference to FIGS. 4A to 4E. In the following description of the manufacturing method, a process that can be formed according to process steps well known to those skilled in the art will be briefly described in order to avoid obscuring the present invention. In addition, each component described in the above structure will be omitted or simplified in order to avoid duplication of description.

4A through 4E are cross-sectional views sequentially illustrating a process of manufacturing a semiconductor device having the structure of FIG. 1.

Referring to FIG. 4A, a semiconductor substrate in which an active region 121 is defined by a shallow trench isolation (STI) 120, which is an isolation region, is provided. The active region 121 may be defined by performing the process of forming the STI 120 on the semiconductor substrate 110. The semiconductor substrate 110 may be formed of a p-type or n-type silicon substrate.

Thereafter, the first oxide film 310 and the second oxide film 315 are formed on the semiconductor substrate 110. The first oxide film 310 may be formed by performing a thermal oxidation process, for example, as an intermediate temperature oxide (MTO). The second oxide film 315 may be formed of silicon oxynitride (SiON), silicon nitride (SiN), or the like, and may be about 30 to 100 kV by performing chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or the like. It may be formed in a thickness. Then, patterning (not shown) and dry etching of the photoresist may be performed to selectively etch the upper oxide films 310 and 315 of the active region 121 adjacent to the STI region 120. Dry etching may be anisotropically etched through, for example, reactive ion etching (RIE) processes.

Next, a trench 320 is formed in the active region 121 of the semiconductor substrate 110. The trench 320 is formed by dry etching (eg, reactive ion etching (RIE)) of the exposed surface of the semiconductor substrate using the oxide layers 310 and 315 remaining after the etching as an etch mask. can do. The trench 320 may be formed to a thickness of about 100 to 300Å. The deeper the trench, the wider the leakage current path from the trench side to the channel direction. In addition, the efficiency of the epitaxial gap-fill process performed in FIG. 4D is reduced. Therefore, the depth of the trench 320 is preferably formed to be shallow.

4B and 4C, the barrier layer 160 is formed on the bottom of the trench 320.

First, referring to FIG. 4B, an oxide film (not shown) may be formed on an exposed entire surface of the semiconductor substrate 110. Such an oxide film may be formed by a process such as thermal oxidation, CVD, LPCVD, and the like and may be provided with a thickness of about 10 to about 40 kPa. The oxide film is preferably formed thin so that it can be removed in the etching process according to Figure 4c. Thereafter, the oxide layer may be wet etched to form sidewall spacers 325 on both sides of the trench 320. The sidewall spacers 325 are intended to prevent the oxide film from growing on the side of the trench during the formation of the barrier layer according to FIG. 4C.

A barrier layer (not shown) is formed after the sidewall spacer 325 is formed. The barrier film may be formed by a process such as thermal oxidation, CVD, LPCVD, or the like. Since an oxide film is already formed on the top of the semiconductor substrate or on the side surface of the trench 320, the barrier film is formed relatively thick on the bottom surface of the trench 320. Thereafter, the exposed front surface of the semiconductor substrate 110 is wet and / or dry etched (eg, reactive ion etching (RIE)) to form a barrier layer 160 on the bottom of the trench 320. Be sure to The barrier layer 160 may be formed to a thickness of about 60 to about 100 microns. The barrier layer 160 is preferably formed to a thickness such that it is not physically destroyed by a voltage applied to a storage node contact (not shown). In addition, as the barrier layer 160 is thinner, a deposition process such as CVD for forming the layer may be more efficient.

Referring to FIG. 4D, an epitaxial layer filling the trench 320 is formed. The epitaxial layer 330 may be formed by a selective epitaxial growth process. For example, when the semiconductor substrate 110 is of p type, silicon tetrachloride (SiCl ₄ ) and SiH ₂ Cl ₂ (dichlorosilane) having higher selectivity to the trench side surface 335 than the oxide film 315 and the barrier layer 160 are provided. ) And the like may be made into a gaseous state and deposited on the surface of the barrier layer 160 at a temperature of about 1100 to 1300 ° C. Since materials such as SiCl ₄ and SiH ₂ Cl ₂ have relatively low selectivity with respect to the surfaces of the oxide layer 315 and the barrier layer 160, nucleation is generated and grown only in the trench side 335. In addition, the epitaxial layer 330 is allowed to grow until it reaches a height extending from the surface of the oxide film 315. Next, the epitaxial layer 330 may be selectively wet or dry etched back to remove the upper portion of the epitaxial layer 330 to a depth where the oxide layer 310 contacts the semiconductor surface. . Thereafter, the oxide layers 310 and 315 may be removed and the entire exposed surface may be planarized through a chemical mechanical polishing (CMP) process.

4E shows the structure of a semiconductor substrate obtained through such a CMP process. It can be seen that the barrier layer 160 is formed in the semiconductor substrate 110. By forming the barrier layer 160 in the semiconductor substrate, leakage current flowing into the semiconductor substrate 110 may be blocked.

On the other hand, in order to form the upper structure (210, 220, 230, 240) of the semiconductor substrate 110 shown in Figure 1 as a subsequent process to the structure obtained in Figure 4e, an oxide film (not shown), conductive film (not shown) and A mask layer (not shown) is formed and sequentially patterned to form the gate oxide layer 210, the gate electrode 220, and the hard mask layer 230 in order, and form a spacer 240. In this case, the first and second impurity regions 130 and 140 may be formed by performing impurity implantation before and / or after forming the spacer 240 according to characteristics of the device to be formed. In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

Hereinafter, a method of manufacturing a semiconductor device having the structure of FIG. 2 will be described.

First, the processes of FIGS. 4A to 4E described above are performed in the same manner. These processes are as described above and will not be described here.

Next, referring to FIG. 5, after obtaining the structure of FIG. 4E, the structure 340 of the recessed semiconductor substrate may be formed through a patterning and etching process. The depth of the recess may be variously formed according to the characteristics of the semiconductor device. Since the recessed structure 340 increases the resistance of the channel, the degree of leakage current in the channel direction may be reduced in the first impurity region 130 connected to the storage node contact (not shown).

Meanwhile, in order to form the upper structures 211, 220, 230, and 240 of the semiconductor substrate 110 shown in FIG. 2 as a subsequent process with respect to the structure obtained in FIG. 5, the gate electrode as described for obtaining the structure of FIG. The process of forming and the process of injecting 1st and 2nd impurity are performed similarly. In this manner, the semiconductor device shown in FIG. 2 can be manufactured.

Hereinafter, a method of manufacturing a semiconductor device having the structure of FIG. 3 will be described.

First, as described above, the processes of FIGS. 4A to 4E are performed, and then the process of forming the gate electrode and the process of injecting the first and second impurities are performed in the same manner. These processes are the same as described above in the manufacturing method of the semiconductor device shown in FIG. 1 and will not be described herein.

Next, referring to FIG. 6, the second impurity is formed by forming an inter layer dielectric (ILD) layer 345 on the entire surface of the semiconductor substrate 110 and sequentially performing a patterning and etching process of the photoresist (PR) 350. Only the upper portion of the region 140 may be selectively opened. Thereafter, an impurity is further injected into the second impurity region 140 to form a new second impurity region 141. In this manner, the semiconductor device 3 shown in FIG. 3 can be manufactured. When the asymmetrical impurity region 141 shown in FIG. 3 is formed, the thickness of the channel region is increased to reduce the resistance of the channel during the operation of the semiconductor device, thereby improving refresh characteristics such as driving force of the semiconductor device.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to significantly improve the refresh characteristics by forming a barrier layer under the impurity region of the semiconductor substrate to block the main generation path of the leakage current. In addition, the refresh characteristics of the semiconductor device can be improved by forming a recessed structure in the semiconductor substrate or by additionally injecting impurities into the impurity region.

Claims (6)

A semiconductor substrate in which an active region is defined by an element isolation region; A gate electrode formed in an active region of the semiconductor substrate; A first impurity region adjacent to one side of the gate electrode and formed in the semiconductor substrate; A barrier layer formed under the first impurity region and formed in the semiconductor substrate; And And a second impurity region adjacent to the other side of the gate electrode and formed in the semiconductor substrate. The method of claim 1, And a channel region disposed below the gate electrode is recessed into the semiconductor substrate. The method according to claim 1 or 2, And the second impurity region contains a higher concentration of impurities than the first impurity region. Providing a semiconductor substrate having an active region defined by an element isolation region, Forming a trench in an active region of the semiconductor substrate, Forming a barrier layer on the bottom of the trench, Forming an epitaxial layer filling the trench, Forming a gate electrode adjacent to one side of the epitaxial layer on the semiconductor substrate, Impurities are implanted into the semiconductor substrate, and a second impurity region is formed in the semiconductor substrate facing the first impurity region and the first impurity region adjacent to the one side of the gate electrode and adjacent to the other side of the gate electrode. Manufacturing method of a semiconductor device comprising forming a. The method of claim 4, wherein After forming the epitaxial layer filling the trench, And recessing the semiconductor substrate, which is a channel region under the gate electrode. The method according to claim 4 or 5, After implanting impurities into the semiconductor substrate And injecting additional impurities into the second impurity region.

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