KR20070053161A - Driver for an oled passive-matrix display - Google Patents

Abstract

OLED (organic light emitting diode) passive matrix display 26 includes a display portion 10 and a drive portion 28. Display portion 10 comprises a matrix of OLEDs 13 for displaying information. The drive portion 28 includes a monitor circuit 32 and a voltage adjust circuit 34. The voltage regulation circuit 34 has a power up portion 36 which generates a supply voltage VH based on the reference voltage VREF. In response to the instruction to switch modes, the voltage regulating circuit 34 switches to the operating mode in which the supply voltage VH is generated based on the maximum voltage drop read from the OLEDs 13.

Description

Driver for an OLED passive-matrix display

The present invention relates to displays, and more particularly to organic light emitting diode (OLED) passive matrix displays.

Liquid crystal displays (LCDs) are the most common type of flat panel displays used today. One drawback, however, is that LCDs require a separate light source, typically a fluorescent backlight, to illuminate the panel. In fact, the brightness of the LCD is solely dependent on the backlight, and it is this backlight that limits the lifetime of the LCD.

Because of these drawbacks, OLED displays are gaining popularity. Since OLED displays emit light, they do not require a separate backlight. Passive-matrix OLED displays have a simple structure, making them well suited for low-cost, low-information-content applications such as alphanumeric displays. Active matrix OLEDs include an integrated electronic backplane that drives high resolution, high information-content applications including video and graphics. In either case, OLED displays are very thin, compact design displays with wide viewing angles (up to 180 degrees) and fast response, high resolution, and good display quality.

The basic OLED cell comprises a stack of thin organic layers sandwiched between an anode and a metal cathode. Organic layers generally include a hole-injection layer, a hole-transport layer, an emissie layer, and an electron-transport layer. The light emitting layer is mainly capable of light generation or electroluminescence. Specifically, when a suitable voltage is supplied to the cell, the injected positive and negative charges recombine in the light emitting layer to produce light. The structure of the organic layers of the anode and the cathode is designed to maximize the recombination process in the light emitting layer, thus maximizing the light output from the OLED display.

The light output or brightness of an OLED display is directly proportional to the current. In addition, the impedance of OLEDs falls exponentially with increasing forward voltage (VF). Thus, when the impedance drops, the light output increases rapidly, so there is substantially no delay between the current generation and the light output generation.

One problem with OLED displays is that current-voltage (I-V) characteristics fluctuate over time, which leads to degradation in luminance efficiency and uniformity of luminance between pixels. Several factors affect the variation of these I-V characteristics, including operating temperature, external light (eg sunlight), and pixel location on the display. The driving method also affects the I-V characteristics. For example, in OLED passive matrix displays, one method used is called multiplexing line address (MLA), in which the average current required to bias the OLED is multiplied by the duty cycle of the row so that the equivalent multiplexing current , Which can be 50 to 200 times the average bias current (1 mA at 1 mA from faint to bright), depending on the number of columns and the material efficiency. Such high currents cause excessive voltage drops in OLEDs, which wastes power consumption.

International application WO 03 / 107313A2 of Cambridge Display Technology discloses a technique for reducing the power consumption of an active matrix display by controlling an adjustable power supply that uses current and voltage sensors and adjusts the voltage in response to the sensed voltage. However, this application only discloses indirectly measuring the voltage and current used by the display pixels, which is not very desirable. In addition, there is no well-defined technique disclosed for efficient power-up of OLED displays. That is, when the display is initially powered on, the pixels are off and the required voltage required in the OLED display is not very satisfactorily defined.

Thus, there is a need for a display that can efficiently experience OLEDs with respect to the power up mode and allow adjustment of the power level supplied to the OLEDs after the power up mode is implemented.

To overcome the drawbacks of the prior art, there is an OLED passive matrix display that gives not only efficient power, but also the ability to adjust the power (eg, voltage and / or current) supplied to the OLEDs based on the need during normal steady state. Is initiated.

According to the claimed invention, an OLED display and its driving method as defined in claims 1 and 11 are given.

In one embodiment, an OLED passive matrix display includes a monitor circuit that monitors real-time voltage levels used by the OLEDs, and a voltage regulation circuit that changes the supply voltage in response to signals received from the monitor circuit. During the power-up mode, the voltage regulation circuit uses a fixed reference voltage that is the base for generating the supply voltage when the power required by the OLEDs is not satisfactorily defined. However, after a predetermined time or as a response to an external signal, the voltage regulation circuit is switched from the fixed reference voltage reading to the variable voltage level reading supplied by the monitor circuit. This variable voltage is based on the voltage reading of the OLEDs, such as directly reading (reading) the voltage drop across the OLEDs. In response to this variable voltage level, the voltage regulation circuit changes the voltage supplied to the OLEDs. In this way, there is no wasted waste of power, and the circuit tracks all OLEDs in real time.

An embodiment of the present invention will now be described with reference to the following drawings:

1 is a circuit diagram of a display portion of an OLED passive matrix display.

2 is a high level block diagram of an OLED passive matrix display according to one embodiment of the invention.

FIG. 3 is a detailed circuit diagram showing further characteristics of the block diagram of FIG. 2.

4 is a flowchart of a method for driving an OLED passive matrix display.

1 shows a display portion 10 of an OLED passive matrix display. The matrix 12 of OLEDs 13 comprises parallel conductor rows 14 located orthogonally to the parallel conductor columns 16. Each row 14 contains an OLED of Dx1 to Dxm, where x is a row number and m is the number of columns, where each column 16 is an OLED of D1x to Dnx, where n is the number of rows x is a column number). Each column is biased with current generator 18 (1 to m) having its upper end connected to voltage source VH and its lower end connected to one of column switches SC1-SCm. Each row 14 comprises one of the row switches SR1-SRn with the upper end connected with the OLEDs and the lower end connected with the cathode 21. The column switches SC1-SCm and the row switches SR1-SRn can be independently switched such that each OLED can be individually selected independently of the other OLEDs. To directly measure the voltage across the OLEDs, voltage taps 20, denoted VFD1 -VFDm, are connected with the columns. These voltage taps 20 can be connected to the top or bottom of the switches SC1-SCm and the taps 20 can be used to read the OLED voltage from the outside.

The voltage source VH is at the OLED " ON " voltage, the voltage drop on the rows 14 and columns 16, the voltage saturation of the current generators 18, and the switches SC1-SCm and SR1-SRn. It must have a high enough voltage to account for the voltage drop. Although not shown in Fig. 1, a driving circuit to be described below is used to generate power supplied from the voltage source VH.

In operation, display portion 10 performs a scan operation in which one row is activated at a time through successive activations of switches SR1-SRn. However, the cycle is such that the activation and deactivation of OLEDs is not noticeable to the human eye. Since only one of the row switches SR1-SRn is active at a time, the voltage taps 20 are used to read the voltage drop across one OLED in one column at a time. This direct measurement is a very accurate way to determine the voltage used by each OLED in the display.

2 is a higher block diagram of an OLED passive matrix display 26, which includes a display portion 10 and a drive portion 26. As shown in FIG. The drive portion 28 includes a monitor circuit 32 and a voltage adjust circuit 34. The monitor circuit 32 is connected to the display portion 10 via voltage taps 20.

The voltage regulating circuit 34 includes two parts, a power-up part 36 (also called a power-up means) and an operation mode part 38 (also called an operation mode means).

The power up portion 36 is used by the voltage regulation circuit 34 when the OLED passive matrix display 26 is first powered on (when powered up). The reference voltage Vref is supplied to the power up portion, and during the first period, this reference voltage is used to generate the supply voltage VH. After a predetermined time or in response to an external signal, the voltage regulation circuit 34 switches from using the power up portion 36 to using the operation mode portion 38 to generate a supply voltage. The voltage regulation circuit 34 reads the voltage supplied from the monitor circuit 32 for the supply voltage generation during this secondary period. The power up portion 36 and the operation mode portion 38 are connected to each other at the supply node VH used to supply power to the display portion 10 shown in FIG.

3 is an embodiment showing a detailed circuit diagram of the driving portion 28 of the OLED passive matrix display 26. Voltage taps 20 (from FIG. 1) are connected to multiple input buffers 46, denoted VFD1 -VFDm, via direct connection or the like. The buffer 46 is a simple buffer that includes " m " differential stages (commonly having multiple gates with sources and drains) connected in a parallel manner. Diode 48, capacitor 50, and buffer 46 come together to operate as peak detector 51 to detect the maximum voltage drop across OLEDs 13 (FIG. 1). This maximum voltage drop is fed back to the multiple input buffer 46 for storage purposes (denoted 52). The voltage of capacitor 50 is named Vfmax and represents the maximum voltage across all pixels (ie OLEDs) of the display. The size of the capacitor depends on the design, but as an example the value can be in the range of 100-300nf. The voltage regulating circuit 34 has two parallel circuit loops 54, 56, inherent in the common switch 58 (the switch allows for the alternative selection of these circuit loops), the DC / DC converter 60, and Voltage supply node VH (connected to voltage generators 18 of FIG. 1).

The first circuit loop 54 corresponds to a power up portion 36 (FIG. 2) and has an operational amplifier connected to the switch 58 and an non-inverting input connected to the reference voltage VREF. 62). An example of the value of VREF is 1.25 volts, but this depends on the design. A divider circuit 64 comprising R1 and R2 is used to provide a percentage of the supply voltage VH to the inverting input of the op amp 62. The values of R1 and R2 depend on the design, but an example of the R1 / R2 ratio is between 10 and 20.

The second circuit loop 56 corresponds to the operation mode portion 38 (FIG. 2) and includes a non-inverting input connected to a capacitor 50 that supplies the maximum voltage read from the OLEDs 13. The op amp 66 also includes an inverting input connected to the voltage supply node VH via a voltage offset 68. The voltage offset 68 takes into account the saturation range of the current generators 18 of the display 26 and can be externally controlled through a digital-to-analog converter (not shown). Thus, the voltage supplied by the voltage regulation circuit 34 is proportional to the read maximum voltage plus voltage offset 68 across the OLEDs.

4 is a flowchart of a method of driving an OLED display. The voltage regulation circuit 34 generates the supply voltage using the reference voltage VREF during the power-up mode of operation (step 80). After the preliminary period, the voltage regulating circuit 34 switches the switch 58 to switch from the power up mode to the operation mode (step 82). As is well understood in the art, there are numerous ways to control such a switch 58. For example, an external processor may control the switch based on the display state, or a timer may provide some signal after a predetermined time to control the switch.

The monitor circuit 32 directly reads the voltage drop in the OLEDs (step 84). Such reading is performed in real time during the display operation. The peak voltages of the OLEDs are stored (step 86). Thus, the maximum voltage used by any OLED of the OLED display is stored in the capacitor 50. The peak voltage is used by the voltage adjusting circuit 34 to adjust or maintain the low voltage currently supplied to the supply node VH (step 88).

In view of the above description, it will be apparent that numerous changes and modifications may be made to the apparatus and methods described and illustrated herein, all of which may fall within the scope of the invention as defined in the appended claims. have.

For example, although a particular display portion is shown in FIG. 1, a monitor circuit may be used to read other types of display portions used in passive matrix OLED displays. Again, although certain types of peak detectors are used, those skilled in the art will appreciate that a wide variety of peak voltage detectors can be used. In addition, although the voltage is being monitored from the columns, circuitry for individually monitoring the voltage across each pixel can also be easily configured. Finally, although each OLED is being monitored through the design described above, it will be appreciated that less than all OLEDs may be monitored if desired.

Claims (16)

In OLED passive matrix display 26, A plurality of conductor rows 16 deployed in the first direction; A plurality of conductor rows 14 deployed in a second direction orthogonal to the first direction; A plurality of OLEDs 13 each associated with one column and one row to enable selection; A monitor circuit 32 connected to the OLEDs 13 for detecting a voltage drop across the OLEDs; A voltage regulation circuit 34 for supplying power to said OLEDs 13 and connected to a monitor circuit 32, The voltage regulation circuit 34 has two modes of operation: a power-up mode in which the reference voltage VREF is used by the voltage regulation circuit 34 to supply power to the OLEDs 13, And an operating mode in which a variable voltage supplied from the monitor circuit 32 by the voltage adjusting circuit 34 is used to supply power to the OLEDs 13. 2. The voltage adjusting circuit according to claim 1, wherein the voltage adjusting circuit receives power-up mode means (36) for receiving a reference voltage (VREF) to generate a first power supply amount, and for receiving the voltage drop to generate a second power supply amount. OLED passive matrix display characterized in that it comprises a mode means (34). The voltage regulating circuit (34) according to claim 1, wherein the voltage regulating circuit (34) has a first circuit loop (54) and a second circuit loop (of which voltages can be selected alternately). 56 a supply node (VH), which may be supplied to The first circuit loop 54 connects the reference voltage VREF to the supply node VH when selected, and the second circuit loop 56 connects the monitor circuit 32 when selected. OLED passive matrix display characterized in that the connection to VH). 4. OLED passive matrix display according to claim 3, characterized in that the first circuit loop (54) and the second circuit loop (56) are connected to a switch (58) to enable alternating selection of these circuit loops. 5. The first circuit loop (54) of claim 3 or 4, wherein the first circuit loop (54) is connected to a resistor divider (64), an input of one resistor divider and a reference voltage (VREF) to a second input stage. OLED passive matrix display, characterized in that it comprises an operational amplifier (62) connected to it. The second circuit loop (56) according to any one of claims 3 to 5, wherein the second circuit loop (56) has a second office with a first input connected to a monitor circuit (32) and a second input connected to a supply node (VH). OLED passive matrix display characterized in that it comprises an amplifier (66). The method of claim 6, And a voltage offset (68) connected between said second input and a supply node (VH). 8. The circuit of claim 3, wherein the first circuit loop 54 and the second circuit loop 56 comprise a DC-DC converter 60, a switch 58, and a supply node (VH). And a DC-DC converter (60) connected between the switch (58) and the supply node (VH). 9. The OLED passive matrix according to claim 1, wherein the monitor circuit 32 comprises a peak detector 51 for detecting the maximum voltage used in the OLEDs 13. display. 10. The peak detector 51 according to claim 9, wherein the peak detector 51 is connected to the OLEDs 13 so that the multiple input buffers 46 for reading the voltage drop across the OLEDs 13 and the OLEDs 13 OLED passive matrix display characterized by including a capacitor (50) connected to the multiple input buffer (46) output stage to store the maximum voltage used. A method of driving an OLED passive matrix display, Reading 84 the voltage drop across the OLEDs 13; Storing 86 the maximum voltage used by the OLEDs 13; During the mode of operation, adjusting 88 the voltage supplied to the OLEDs 13 based on the maximum voltage, During the power-up mode prior to switching (82) to the operating mode, the reference voltage (VREF) is used to generate (80) the voltage supplied to the OLEDs. 12. The method of claim 11, wherein storing (86) the maximum voltage is accomplished using a capacitor (50). 13. A method according to any one of claims 11 to 12, wherein said switching (82) takes place after a predetermined time. The method according to any one of claims 11 to 13, characterized in that the voltage supplied to the OLEDs (13) during the operating mode is proportional to the maximum voltage plus offset voltage (68). 15. The method of claim 14, wherein the offset voltage (68) is controlled by an external controller. 16. The method according to any one of claims 11 to 15, wherein said reading is performed using multiple input buffers (46).

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