KR20070048985A - Storage device of video decoder and method for controlling thereof - Google Patents

Abstract

The present invention relates to a storage device of a video decoder and a method of controlling the same. In particular, when any header information of video stream data is not in a register set during video decoding, other header information previously stored in the register set is stored in an external memory, and Among the information stored in the memory, the header information required for video decoding is found and stored in the register set, and then the header information stored in the register set is read and used for video decoding. Therefore, the present invention can store the header information for storing in the register set externally without storing all of the header information in the register set which is the decoder internal memory, thereby reducing the area and cost of the decoder chip.

Video decoder, header information, external memory, registers

Description

Storage device and control method of the video decoder {STORAGE DEVICE OF VIDEO DECODER AND METHOD FOR CONTROLLING THEREOF}

1 is a view showing a schematic structure of a conventional video decoder;

2 is a schematic structural diagram of a storage device of a video decoder according to the present invention;

3 is a flowchart sequentially illustrating a control method of a video decoder according to the present invention;

<Description of the code | symbol about the principal part of drawing>

100: video decoder 102: stream input unit

104: header parser 106: decoder

108 control unit 110 IT / IQ

112: deblocking filter 114: prediction unit

116: synthesis section 118: register set

120: CPU 122: external memory

The present invention relates to a storage technology of a video decoder, and more particularly, to a storage device and a method of a video decoder that can improve the storage efficiency of information to be temporarily stored when decoding video image data.

When video or sound is converted into digital data, the amount of data is so large that it takes up a lot of storage space if not compressed, which is inefficient. Therefore, a compression technique for reducing information of digital data is required, and the compression technique can improve storage utilization and transmission function through a network. For example, image compression methods include GIF and JPEG formats, and video and sound compression methods include MPEG, H.263, and H.264.

Among them, H.264 is a new video compression coding standard developed by the Joint Video Team (JVT) jointly formed by the ITU and the International Organization for Standardization / ISO (IEC). 14496 10 Advanced Video Coding 'is a video compression standard that considers error robustness and network-friendly method in consideration of rapidly changing wireless environment and Internet environment.

The H.264 video decoder performs decoding of video image data in units of macro blocks (MBs). In the case of a memory, there is a memory for storing an input video stream and frames for motion compensation.

The input video stream is divided into a series of pictures or groups of frames called a group of pictures (GOP). Each GOP includes a number of pictures, and each picture is divided into a number of slices. Each slice contains a number of macroblocks, each macroblock having four 8x8 brightness blocks and two 8x8 chrominance blocks. And two kinds of pictures may appear in one GOP, one is an intra mode picture (or I-picture) and the other is a predictive motion compensated picture (P-picture). In I-picture, all macro blocks are in intra mode and decoded without considering motion compensation. The P-picture is compressed using one previous frame, and each macroblock can be decoded in an INTER mode using motion compensation.

1 is a view showing a schematic structure of a video decoder according to the prior art.

Referring to FIG. 1, a conventional video decoder includes a stream input unit 10, a header parser 12, a decoder 14, a control unit 16, and an IT / IQ unit 18. ), A deblocking filter 20, a register set 22, a prediction portion 24, a synthesizer 26, and a CPU (Control Processor Unit) (28) and the like.

The stream input unit 10 converts the byte format of the input video stream MEM into SODB and transfers this data to the header parser 12 and the decoder 14.

The header parser 12 separates the video stream data of the stream input unit 10 into slice header information such as sequence parameter set (SPS), picture parameter set (PPS), macroblock header information, and the like, and registers the register set 22. Write to

The decoder 14 decodes the video stream data of the stream input unit 10 into an I-picture, a P-picture, and the like and stores the result in a memory (not shown) such as an SRAM.

The controller 16 controls to provide the header information or other information stored in the register set 22 to the internal component blocks of the video decoder or to store it in a memory (not shown) such as an SRAM.

The IT / IQ unit 18 reads decoded video data stored in a memory (not shown) such as an SRAM, performs an Inverse integer Transform (IT) and an Inverse Quantize (IQ), and then an SRAM. To a memory (not shown).

The deblocking filter 20 removes a phenomenon in which decoded video data output through the combiner 26 is blocked.

The register set 22 stores header information and other information of the header parser 12 and provides the information to other building blocks.

The predictor 24 predicts an intra mode picture (ie, an I-picture) or an inter mode picture (ie, a P-picture) based on the header information of the register set 22. .

The synthesis unit 26 decodes the video data from which the inverse transform and inverse quantization of the IT / IQ unit 18 are performed, and intra-prediction or inter-prediction information of the prediction unit 24. Synthesize and output it. That is, if the decoded video data is an I-picture, the prediction value of the intra mode picture is synthesized. If the decoded video data is the P-picture, motion compensated inter prediction information using the motion vector is synthesized with reference to the reference picture.

The control processor unit (CPU) 28 controls the H.264 format video decoder system as a whole, and controls the decoding operation by reading header information or other information stored in the register set 22.

However, the H.264 video decoder according to the related art should be able to store up to 32 SPS header information and up to 256 PPS header information in the register set 22.

However, the H.264 video decoder according to the prior art has a problem in that the cost of the decoder chip increases as the chip area increases when all the header information and the like used for decoding are stored in the register set which is the internal memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art, and to store in a register set by having an external memory separate from a decoder for storing header information such as SPS and PPS of video stream data. The present invention provides a storage device of a video decoder that can store header information and the like externally without storing the information in an internal memory, thereby reducing the area and cost of a decoder chip.

Another object of the present invention is to store header information such as SPS, PPS, etc. of video stream data in an external memory separate from a decoder, and then read from an external memory at decoding time and store the data in a register set. The present invention provides a control method of a video decoder, which can reduce the area and unit cost of a decoder chip because it can be stored externally without being stored in an internal memory.

In order to achieve the above object, the present invention provides a video decoder comprising: a header parser for separating header information of video stream data, a decoder for decoding video stream data, and inverse integer conversion of video data decoded using the header information. And an IT / IQ unit for performing inverse quantization, a prediction unit for predicting a video picture mode using header information, a synthesizer for synthesizing and outputting inverse integer transform and dequantized video data and a predicted value, and a header; Register set to store information, header information stored in the register set when there is no video decoding, external memory separate from the decoder to store the header information previously stored in the register set, and header information stored in the register set when the video is decoded. The header information stored in the register set Kimyeo find any header information required for decoding in an external memory and a CPU, which passes it to the register set.

In order to achieve the above another object, the present invention provides a method of controlling a video decoder, the method comprising: determining whether any header information of video stream data is in a register set when decoding a video; Storing other header information previously stored in the register set in an external memory, finding corresponding header information required for video decoding among information stored in the external memory, and storing the header information in the register set, and corresponding header information stored in the register set. Reading out and using the video for decoding.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

2 is a diagram illustrating a schematic structure of a storage device of a video decoder according to the present invention.

Referring to FIG. 2, in the storage device of a video decoder according to the present invention, the decoder 100 includes a stream input unit 102, a header parser 104, a decoder 106, a controller 108, and an IT. / IQ unit 110, deblocking filter 112, prediction unit 114, synthesis unit 116, register set 118 and the like.

The decoder 100 is connected to a CPU 120 that reads header information or other information stored in the register set 118 to control the decoding operation in order to generally control the H.264 format video decoder system.

In addition, the decoder 100 of the present invention is connected to an external memory 122 such as a flash through the CPU 120 in order to store header information used when decoding video stream data in a memory separate from the decoder.

In the video decoder 100 of the present invention, the stream input unit 102 converts the byte format of the input video stream MEM into SODB and passes this data to the header parser 104 and the decoder 106.

The header parser 104 separates the video stream data of the stream input unit 102 into slice header information such as SPS and PPS, macroblock header information, and writes them to the register set 118.

The decoder 106 decodes the video stream data of the stream input unit 102 into an I-picture, a P-picture, and the like and stores the result in a memory (not shown) such as an SRAM.

The controller 108 controls to provide the header information or other information stored in the register set 118 to the internal component blocks of the video decoder or to store it in a memory (not shown) such as an SRAM.

The IT / IQ unit 110 reads decoded video data stored in a memory (not shown) such as SRAM, performs inverse integer conversion and dequantization, and stores the decoded video data in a memory (not shown) such as SRAM.

The deblocking filter 112 removes a phenomenon in which decoded video data output through the combiner 116 is blocked.

The prediction unit 114 predicts an intra mode picture (ie, I-picture) or predicts an inter mode picture (ie, P-picture) based on the header information of the register set 118.

The synthesis unit 116 decodes the video data from which the inverse integer transformation and inverse quantization of the IT / IQ unit 110 are performed, and intra-prediction or inter-prediction information of the prediction unit 114. Synthesize and output it. That is, if the decoded video data is an I-picture, the prediction value of the intra mode picture is synthesized. If the decoded video data is the P-picture, motion compensated inter prediction information using the motion vector is synthesized with reference to the reference picture.

When the header information of the header parser 104 is found among the header information stored in the external memory 122, the register set 118 reads and stores the header information of the corresponding SPS and PPS, and stores the header information in other configuration blocks. Provide them.

The CPU 120 generally controls the video decoder system of the H.264 format, and stores the header information previously stored in the register set 118 in the external memory 122 by the interrupt signal of the decoder. In addition, the CPU 120 stores arbitrary header information among the header information stored in the external memory 122 by the interrupt signal of the decoder in the register set 118 so that the decoder internal components refer to and use the decoding information.

The external memory 122 is a memory such as a flash separate from the H.264 format video decoder. If the header information referred to when decoding the video stream data is not stored in the register set 118, the external memory 122 stores the register set 118. Receive pre-stored header information and save it. The header information stored in the external memory 122 is transferred to the register set 118 and stored.

Therefore, the storage device of the video decoder according to the present invention, if the header information such as any SPS, PPS, etc. of the video stream data does not exist in the register set 118, the decoder 100 pre-stores the header information stored in the register set 118. The header information is stored in the external memory 122 that is separated from the data, and the header information stored in the external memory 122 is found and stored in the register set 118 to be used in the internal configuration block of the decoder.

3 is a flowchart sequentially illustrating a control method of a video decoder according to the present invention.

2 and 3, a video decoder according to the present invention operates as follows.

First, the CPU 120 controls the stream input unit 102 to convert the byte format of the input video stream MEM to SODB and transfer this data to the header parser 104 and the decoder 106. The header parser 104 separates the video stream data of the stream input unit 102 into slice headers such as SPS and PPS, and macroblock header information. The decoder 106 decodes the video stream data of the stream input unit 102 into an I-picture, a P-picture, and the like, and stores the result in a memory (not shown) such as an SRAM (S100).

At this time, the control unit 108 of the decoder 100 determines whether the current slice header information of the header parser 104 refers to header information such as SPS and PPS that are not in the register set 118 (if none), and the determination result. If the header information is not in the register set 118, an interrupt signal is generated (S110 to S120).

The CPU 120 stores the header information of the header parser 104 previously stored in the register set 118 in the external memory 122 by the interrupt signal, and deletes the information stored in the register set 118. (S130 )

The CPU 120 reads header information such as SPS and PPS that are not present in the register set 118 from among header information stored in the external memory 122 and stores the header information in the register set 118 (S140).

The control unit 108 reads header information such as SPS and PPS newly stored in the register set 118 and provides the information to the IT / IQ unit 110 and the prediction unit 114 to inverse the constant of the IT / IQ unit 110. The decoded video data, which has been transformed and dequantized, and the intra-prediction or inter-prediction information of the prediction unit 114 are synthesized and output through the synthesis unit 116. (S160 )

The CPU 120 determines whether the input video stream MEM is the last end stream data by the stream input unit 102 (S170). If it is the last end stream data, the video decoding operation is terminated. . However, if not repeated from step S100.

On the other hand, as a result of the determination of S110, the control unit 108 of the decoder 100 registers when the current slice header information of the header parser 104 refers to header information such as SPS and PPS in the register set 118 (if none). Inverse integer conversion and dequantization of the IT / IQ unit 110 are performed by reading header information such as SPS and PPS previously stored in the set 118 and providing the same to the IT / IQ unit 110 and the prediction unit 114. The decoded video data and intra-prediction or inter-prediction information of the prediction unit 114 are synthesized and output through the synthesis unit 116 (S160).

Therefore, in the method of controlling a video decoder according to the present invention, when there is no header information such as any SPS, PPS, etc. of the video stream data in the register set 118, the register set 118 is interrupted by the interrupt signal of the decoder 100. ) Is stored in the external memory 122 separately stored from the decoder 100, and the corresponding header information is found among the information stored in the external memory 122 and stored in the register set 118 to store the header information. Used in an internal component block (for example, IT / IQ unit 110, predictor 114, etc.). If the header information such as any SPS, PPS, etc. of the video stream data is present in the register set 118 during decoding, the header information stored in the register set 118 is read and the internal component block of the decoder (eg, IT / IQ unit 110, prediction unit 114, etc.).

As described above, according to the present invention, when header information such as SPS or PPS of video stream data does not exist in the register set during decoding, the present invention stores the other header information previously stored in the register in an external memory separated from the decoder, By reading the header information and storing it in the register set, the header information for storing in the register set can be stored externally without storing the register set, which is the internal memory of the decoder, thereby reducing the area and cost of the decoder chip.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (4)

In a video decoder, A header parser that separates header information of the video stream data; A decoder for decoding the video stream data; An IT / IQ unit performing inverse integer conversion and dequantization on the decoded video data using the header information; A prediction unit for predicting the video picture mode using the header information; A synthesizer configured to synthesize the inverse transform and dequantized video data and the predicted value; A register set for storing the header information; An external memory separate from the decoder to store header information pre-stored in the register set when there is no header information stored in the register set during video decoding; When there is no header information stored in the register set when decoding the video, the header information previously stored in the register set is stored in the external memory, and any header information required for the decoding is found in the external memory and transferred to the register set. CPU Storage device of the video decoder comprising a. In the control method of the video decoder, Determining whether any header information of the video stream data is in the register set when decoding the video; As a result of the determination, when the header information is not in the register set, storing other header information previously stored in the register set in an external memory; Finding corresponding header information required for video decoding among information stored in the external memory, and storing the corresponding header information in the register set; Reading corresponding header information stored in the register set and using the same for decoding the video; Control method of a storage device of a video decoder comprising a. The method of claim 2, The method, And generating an interrupt signal at the video decoder if the header information is not in the register set. The method of claim 2, The method, And if the header information is present in the register set, reading the corresponding header information stored in the register set and using the same for decoding the video.

Images