KR20070047498A - Flash memory device and fabricating method thereof - Google Patents

Abstract

The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a new device structure for improving the miniaturization characteristics and performance of MOS-based flash memory devices and increasing memory capacity.

The present invention proposes a new device structure based on a recessed channel, which is compatible with existing processes and can be easily implemented with a high integration, high performance, and 2 bit implementation. The proposed device has a structure in which a node for charge storage is formed in the form of a spacer in a recessed channel, thereby greatly reducing the cell area of the two-dimensional phase and allowing 2 bits, and suppressing a short channel effect. In addition, if the insulating film around the recessed silicon surface is selectively removed, not only the surface of the recessed channel but also the side surface is exposed, and even in this state, the spacer is formed and used as a storage node to improve the control ability of the control electrode for the channel. The on / off characteristic of can be improved.

Silicon, Body, Recessed Channel, Spacer, Floating Node, SONOS, NFGM, Multiple Bit, Nano Floating Gate, Self-Aligned

Description

Flash memory device and fabrication method thereof

1 is a graph of a 2003 edition ITRS roadmap showing the gate length of a SONOS flash memory and the maximum number of storage bits per cell by year.

2 is a cross-sectional view of a conventional SONOS flash device structure in which the upper left is a conventional flat channel SONOS flash memory device, and the upper right is only under a control electrode formed of a spacer to improve integration while implementing 2 bits in the existing structure. A device structure formed by forming a nitride film, and below is a diagram schematically showing the density of charges stored in the nitride film.

3 is a cross-sectional view of a recessed channel type flash memory device proposed by the present invention, and FIG. 3 (a) is a cross-sectional view of a device including a region in which a storage electrode can store charge, and FIG. 3 (b) is a view of FIG. A three-dimensional perspective view to clearly show the main part of the vicinity of the body, including the steps from the cross-sectional view of before to the control insulating film of region 8.

Figure 4 (a) is a plan view of a device implemented by rounding the corners between the surface and the side of the recessed area in the device structure of the present invention, Figure 4 (b) is a cross-sectional view taken along the control electrode y-y '.

FIG. 5 (a) is a plan view of a device implemented by rounding an edge between a surface and a side of a recessed region in the device structure of the present invention, and FIG. 5 (b) is a cross-sectional view taken along a control electrode in a field oxide region. -z 'section.

6 (a) and 6 (b) are cross-sectional structural views of a modified flash memory device of the present invention.

7 is a plan view from above of a device implemented as an example for implementing the device structure of the present invention.

8 (a) and 8 (b) are plan views of the modified device structure of the present invention as viewed from above.

9 (a) and 9 (b) are plan views as viewed from above of the modified device structure of the present invention.

10 to 14 are various types of three-dimensional perspective views for clearly showing the main part of the vicinity of the body, including the steps up to the control insulating film in the modified device structure in the present invention.

FIG. 15 is a cross-sectional view illustrating an example in which a storage node is implemented as a dot having a nano size in a cross-sectional view of the device structure of the present invention. FIG.

16 (a) to 16 (c) illustrate profiles of various recessed areas formed in a body in the device structure of the present invention.

17 (a) to 17 (d) illustrate profiles of two recesses as profiles of various recessed regions formed in a body in the device structure of the present invention.

18 (a) to 20 (a) and FIGS. 18 (b) to 20 (b) show a doping range and Gaussian distribution to indicate body doping in the device cross-sectional structure of the present invention. The position of the peak concentration of is indicated by a dashed-dotted line.

21 (a) to 21 (f) are views showing the fabrication process sequence of main parts shown as one example for implementing the device structure of the present invention.

< Description of Symbols for Major Parts of Drawings >

1: Silicon Substrate 2: Wall-type Silicon Body

3: first insulating film 4: source / drain

5: second insulating film (field insulating film or insulating insulating film)

6 tunneling insulating layer 7 charge storage node

8: inter-electrode insulating film (or control insulating film)

9: control electrode 10: nano dot for charge storage

11: third insulating film 12: fourth insulating film

The present invention relates to a flash memory device and a method of manufacturing the same. More specifically, it relates to a new device structure for improving the miniaturization characteristics and performance of MOS-based flash memory devices and increasing memory capacity.

Recently, flash memory is rapidly growing in demand in consumer electronics and portable electronic devices, and is highly marketable. By 2007, it is expected to exceed the existing DRAM market. There is a continuing need for memory devices with high integration and fast write / erase times.

Existing flash memory devices with gate lengths of less than 60 nm face limitations in miniaturization. In the conventional flat channel device structure, to increase the write and read time, the capacitance between the control gate and the floating storage electrode needs to be large. The so-called coupling ratio must be increased, which requires thickening the floating gate in conventional device structures. In this case, even if the gate length of the device is reduced, the thickness of the floating gate cannot be reduced to maintain a coupling ratio of 0.6 or more. As the size of a device with a thick floating gate decreases, the capacitance between the devices increases, which in turn leads to cross-talk between cells, which increases obstacles to integration, such as an increase in the distribution of threshold voltages. It is becoming. As such, existing devices have a problem of miniaturization, write / erase speed improvement, and cross-talk.

One solution to this problem is to sink the channel region. As the depth of depression deepens, even if the corner region formed at the bottom of the recessed channel is rounded, the sensitivity of the threshold voltage is very high according to the doping concentration or profile of the corner region. In addition, these recessed devices have a large change in threshold voltage according to substrate bias compared to the conventional flat channel structure, and the effective channel length is increased according to channel depression, so that the current driving ability is greatly reduced if the channel width is narrowed. have. A general feature of the recessed channel device is that the control electrode has less control over the channel than the flat channel device, which is related to the large substrate bias effect. Weakness of control over the channel of the control electrode has the disadvantage of slowing the write / erase characteristics through the control electrode.

The case where the gate electrode has excellent control over the channel is a double / triple-gate MOS structure in which the gate surrounds the channel region. Body-tied double / triple-gate MOS structure by Applicant (application number: 2002-5325 (Korea), JP2003-298051 (Japan), 10/358981 (United States)) and its application to flash memory ( Korean Patent Registration No. 0420070 and US Patent Application No. 10/751860 have been published for the first time in the world, and the applicants call this structure bulk finFET. In this structure, the channel is not recessed, and the channel is formed on the top and both sides of the active body, or the channel is formed on both sides of the body, so the gate control over the channel is much better than the conventional flat channel device. There is almost no substrate bias effect. However, in order to suppress the short channel effect, the width of the body should be about 2/3 of the physical gate length, which means that the silicon body is narrower than the minimum gate length.

In order to improve the problem of miniaturization in miniaturization of a conventional flash memory device, a SONOS type flash memory or a nano floating gate memory (NFGM) may be applied. The characteristic of SONOS-type flash memory is that since the storage node is an insulating layer, one bit can be stored in each channel of the source and drain side, and two bits can be stored in one cell. For example, attempts have been made to store 2 bits per cell using SONOS in conventional flat channel device structures (B. Eitan et al., “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Devices). , vol. 21, no. 11, p. 543, 2000). However, to achieve 2 bits per cell, the physical length of the channel must be at least 100 nm. This is because as the device's channel length decreases, the distance between the source and drain gets closer, and memory information is easily lost if the charge stored on one side spreads to the other at a given temperature.

1 graphically depicts a typical ITRS roadmap. The number of bits that can be stored per cell is required from 2 bits to 4 bits around 2010 so that the charges that can be stored on the source and drain sides do not affect each other. will be. In FIG. 1, a general flash memory reduction has been performed at less than 100 nm since 2004, and in 2018, a gate length of about 20 nm is required. In particular, the gate length of SONOS technology requires about 170 nm in 2005 to 140 nm in 2018, as mentioned above, because the gate length needs to be kept long to store 2 bits per cell.

Basically, reducing the physical gate length greatly improves the integration of the device. In the SONOS flash technology, reducing the gate length to near or below 100 nm poses a problem for redistribution or spread of stored charge after programming. To solve this problem, a structure for charge storage separated on the source and drain sides has been proposed (M. Fukuda et al, “Scaled 2 bit / cell SONOS type nonvolatile memory technology for sub-90 nm embedded application using SiN sidewall trapping structure , ”In IEDM Tech. Dig., P. 909, 2003). This structure allows the reduction of SONOS flash memory devices to gate lengths of less than 100 nm. However, since the nitride spacer is used as a storage node on both sides of the control electrode (gate), the actual gate length including the spacer, which is the storage electrode, is simply longer than the length of the control electrode. In addition, since the storage node is a nitride film spacer, charge storage or removal is not performed smoothly by the control electrode.

To solve these problems, a structure as shown in FIG. 2 has been proposed (BY Choi et al., “Highly scalable and reliable 2-bit / cell SONOS memory transistor beyond 50 nm NVM technology,” in Symposium on VLSI Technology Dig., P. 118, 2005). Unlike the conventional gate forming process, this structure adopts a so-called inner sidewall scheme in which a gate electrode is formed first to form a gate, and the total gate length including the spacer sidewall is about 80 nm. The degree of integration of the device is being improved. Considering that the length of the nitride film formed under the spacer is about 20 nm on the source and drain sides, the length of the center control electrode is about 40 nm. However, to reduce the total gate length including spacers to 50 nm or less in this device, the length of the control gate and the length of the nitride, the storage node, must be further reduced, which reduces the voltage difference between programming and erasing the memory and flat channel structure. In this case, the short channel effect occurs due to the reduction of the gate length, which causes problems such as reducing the threshold voltage shift and increasing leakage current. Accordingly, there is a need for developing a new integrated high performance flash memory device that solves the problems of the existing devices.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to implement a micro flash device based on MOS, which has excellent miniaturization characteristics, reduces the spread of threshold voltage, and stores more than 2 bits per cell. It is possible to provide a flash memory device capable of improving the write / erase characteristics.

In addition, another object of the present invention includes an excellent reduction characteristics, which is an advantage of the recessed channel device, to improve the controllability of the channel of the control electrode by devising a multi-gate structure to compensate for the disadvantages of the recessed channel device, threshold voltage The present invention aims to provide a flash memory device that can solve problems, improve on-off characteristics, and improve write / erase speed.

The present invention as a technical idea for achieving the above object

A fence-like semiconductor body region is formed on the semiconductor substrate, a first insulating layer is formed on the surface of the substrate and the body region, and a second insulating layer for the field for isolation of the device is formed on the first insulating layer. It is formed up to near the surface, the body is formed to be recessed in a predetermined width and depth from the body surface for the portion to be formed recessed channel in the surface of the body region,

The first insulating film formed on the side of the body region and the second insulating film patterned together when the mask pattern is performed for the body depression are formed to be recessed to a predetermined depth from the surface along the portion where the control electrode is to be formed. A third insulating film for tunneling is formed on the surface and some side surfaces of the recessed fence-like semiconductor body,

In the recessed region, charge storage nodes are formed on the vertical surface and some side surfaces of predetermined positions, the charge storage nodes are formed to be isolated between the cells, and the fourth insulating film and the control electrode between the electrodes are sequentially formed. Source / drain is formed at a predetermined position of the fence-type body region,

A flash memory device having a structure in which a fifth insulating film, a contact, and a metal layer having a predetermined thickness are formed on the resultant material.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the configuration and operation of the preferred embodiment of the present invention.

The present invention proposes a new device structure that solves the problems of the existing two-bit cell. FIG. 3 (a) shows a cross section of the device proposed in the present invention, and FIG. 3 (b) shows the structure of the present invention by performing a process before forming an inter-electrode insulating film.

In FIG. 3B, the field insulating film region of the region 5 that is actually present is excluded to accurately show the recessed region, and shows the main structure near the fence body. In FIG. 3B, an elliptical region 1 is a symbolic representation of a silicon wafer substrate. Basically, the main part of the device including the storage node and channel is formed in the recessed area. The width of the fenced body is suitably formed in the range of 4 nm to 200 nm, and the height of the fenced body formed on the substrate of the region 1 is suitably formed in the range of 100 nm to 1000 nm. As shown in (b) of FIG. 3, the width of the fenced body may be formed to have the same width from the body surface to the substrate of the region 1, and in some cases, the body width gradually increases from the body surface to the region 1. It may be configured to increase, or may be formed on the substrate of the region 1 while maintaining a uniform thickness up to an appropriate depth at the surface of the body and gradually increasing the width of the body.

When the channel is formed in the recessed region, a channel length longer than the recessed region open width (d1) of the two-dimensional region viewed from the above can be realized, thereby greatly suppressing the so-called short channel effect. Suitable sizes of d1 indicated are suitably formed in the range between 10 nm and 200 nm. The depth to be recessed is the depth recessed from the surface of the fenced body of the region 2 as shown in FIG. Appropriate values of d2 indicated are formed in the range between 20 nm and 900 nm. In FIG. 3 (a), d3 is for indicating the height of the control electrode of the region 9 protruding at an arbitrary height from the surface of the fenced body, and suitably based on the surface of the fenced body of the region 2. It is formed between -100 nm and 900 nm. The depth of the source / drain of the region 4 is indicated by d4 because it is expressed based on the depth of the LDD (Lightly Doped Drain). Appropriate depths of the indicated d4 are formed in the range from 5 nm to 150 nm. There may be a higher concentration source / drain doping immediately next to the LDD, and the junction depth of the source / drain region with a higher concentration than LDD may be equal or deeper than d4. For NAND flash applications, LDD-only sources / drains can be used. For NOR flash applications, the concentration of LDD is increased so that hot carriers can be easily formed. The maximum impurity concentration of LDD for NAND flash applications is appropriately determined in the range of 1 × 10 ¹⁸ cm ^-3 to 8 × 10 ¹⁹ cm ^-3 and includes the source / drain regions overlapping the control electrode for NOR flash applications. maximum impurity concentration of the source / drain region is 5 × 10 ¹⁸ cm ^- is determined in the range between ^{3 - 3} 5 × 10 ²¹ cm.

In Figure 4 (a) d5 represents the distance between the storage node of the region (7) from the surface of the fence body, the distance of d5 is formed in the range of 1 nm to 100 nm. The storage node region 7 can be formed from the surface of the fenced body to an appropriate depth vertically, but in order to prevent unnecessary redistribution of the charge, it is necessary to control it appropriately for the memory operation. The length in the vertical direction of the region 7 for storing the charge can be suitably adjusted if necessary at 2 bits or more per cell, and the range is suitably formed between 2 nm and 300 nm. As a tunneling insulating film of the region 6, various high-k materials including a conventional silicon oxide film may be used. The thickness of the tunneling insulating film is suitably formed between 0.5 nm and 9 nm of EOT (equivalent oxide film thickness based on the silicon oxide film). The tunneling insulating film may be formed thicker near the recessed bottom than on the side of the recessed region.

In FIG. 3A, the tunneling insulating film of the region 6 except the tunneling insulating film of the region 6 in contact with the storage node of the region 7, that is, the region in the region not in contact with the region 7 ( The tunneling insulating film of 6) can be formed thicker, and the thickness of such a thick insulating film can be appropriately determined in the range of 1 nm to 20 nm. D6 denotes the length of the storage node of the region 7 formed as the channel region from the source / drain junction depth. The length in the vertical direction of the region 7 as the charge storage node is suitably formed between 2 nm and 300 nm. The thickness of the region 7 is suitably formed between 1 nm and 50 nm. The material for the storage node can be either a conductor or an insulator capable of storing charge. Conductors as storage nodes can be polysilicon, poly SiGe, amorphous silicon, amorphous SiGe, various metals. Insulators used as storage nodes include materials with high dielectric constants (or high-k materials), including nitride films that can capture charge.

In addition, the charge storage node may be composed of a plurality of nano-size dots. Nano-scale dot materials include semiconductors such as silicon, Ge, and SiGe that can store charges, metals of various work functions, and silicide materials of various work functions. The size of the nano-sized dot used as the charge storage node of the region 7 is formed in the size range between 1 nm and 40 nm, the shape of the dot is spherical, hemispherical, oval, rounded corners or corners Pyramid shape, rounded corners or corners, the upper part is hemispherical, the lower part is characterized by consisting of a rectangular shape of any shape. The predetermined vertical position at which the charge storage node of the region 7 in the recessed region ends is denoted by d6, and the marked d6 may be extended to the tunneling insulating film of the region 6 formed on the recessed bottom, 1 nm. At 150 nm. The region 8 is an insulating layer formed between the storage node of the region 7 and the control electrode of the region 9. The thickness of the region 8 is formed between 2 nm and 30 nm. The structure of the region 8 may be composed of a single layer insulating film, or may be composed of a multilayer insulating film such as oxide-nitride-oxide (ONO). In addition, a so-called high-k insulating material having a higher dielectric constant than a silicon oxide film may be used to increase the coupling ratio.

The region 9 is a control electrode of polysilicon (n type or p type), poly Ge (n type or p type), poly SiGe (p type or n type), various silicide materials, binary metals such as TiN or TaN, It may be composed of a single metal such as tungsten (W). In FIG. 3B, the region 7 as the storage node surrounds a part of the surface and side surfaces of the recessed fenced body. In this way, the on-off characteristic can be improved by increasing the controllability of the channel compared to the structure that does not surround the side. Of course, since the storage node is surrounded, the program window can be enlarged by increasing the shift of the threshold voltage according to the write operation. As such, the storage node of the region 7 may be formed only in the region necessary for the flash memory operation, thereby improving operation characteristics. A recessed region is formed in the fenced silicon body of the region 2, and lengths in the vertical direction of the charge storage node of the region 7 formed on the vertical surface and the side of the recessed region may be the same or different from each other. .

In FIG. 3B, d9 represents the inner width (or distance) of the storage node covering the side of the recessed region, and is suitably formed between 1 nm and 50 nm. There are two corners near the bottom of the recessed area and the shape of the corners may be formed at right angles or obtuse angles, and may be appropriately rounded as shown in FIG. In FIG. 3 (b), the region 3 represents a thermally oxidized film that is thinly formed after the formation of the fence body, and is appropriately formed at a thickness between 0.5 nm and 50 nm. In an actual manufacturing process, after forming the insulating film of the area | region 3, the field insulating film of the thick area | region 5 is formed. In addition, after forming the insulating film of the region 3, a silicon nitride film having an appropriate thickness in the thickness range of 1 nm to 100 nm is formed to remove defects that may occur after the field film of the region 5 is formed, or It can be used in process steps to effectively reveal the side.

In FIG. 4, a plan view is shown in FIG. 4 (a) to more clearly show the device structure of the present invention, and a cross section taken along the line y-y 'is shown in FIG. 4 (b). A cross section taken along line x-x 'in FIG. 4A is shown in FIG. 3A. When the channel of the device is formed in the recessed region compared to the flat channel device structure, the control electrode of the device has a lack of ability to control the channel, thereby degrading on-off characteristics (or sub-threshold swings) for the same substrate doping concentration. . This reduces the current in the on state and increases the current in the off state. Therefore, when the side of the recessed surface is exposed to form the control electrode of the region 9, the controllability of the control electrode for the channel can be improved, thereby improving the characteristics of the device. As an example of such a structure, as shown in (b) of FIG. 4, the control of the region 9 on both sides of the bottom surface of the recessed region where the storage node of the region 7 becomes a channel and becomes a channel is not formed. The electrodes are formed to improve on-off characteristics compared to the conventional simple recessed channel structure. The part indicated by d11 in FIG. 4 (b) corresponds to the length of the side surface exposed after the depression, and the range of the value is suitably formed between 1 nm and 50 nm. Simply d 0 means that no side channel is formed.

D7 shown in FIG. 4A is the sum of the thicknesses of the tunneling insulating film of the region 6 and the storage node of the region 7 formed on the side of the recessed region. The indicated d8 represents the width of the fenced body of the region 2 and can be appropriately formed in the range of 2 nm to 200 nm. The marked d9 represents the length of the storage node of the region 7 covering the side of the region recessed to be the same as the d9 indicated in FIG. 3 (b). The marked d10 is a length defined to extend the storage node of the region 7 so that the side of the recessed region in one cell is sufficiently covered. Adequate self-alignment techniques in the manufacturing process can almost eliminate the length of d10. In some cases, the storage node of the region 7 may be connected between the cell in the longitudinal direction of the control electrode of the region 9. In FIGS. 4A and 4B, edges existing between the surface and the side surfaces of the recessed region formed in the fenced body of the region 2 may be rounded to suppress formation of possible parasitic channels. In FIG. 3 (b), the edges are displayed at right angles for convenience of the three-dimensional drawing configuration, and it is necessary to round them as in FIG. 4 (a).

FIG. 5 is a view for explaining a brief method of forming the charge storage node of the region 7 shown in FIG. 5A by forming an example self-aligning method and forming only around the cell while reducing one mask. That is, the so-called self-alignment method of FIG. 5 (a) shows a method of almost eliminating d10, which is the length of the extended charge storage node corresponding to the margin. In order to briefly explain this, FIG. 5B is prepared. FIG. 5B shows the upper portion of the cross-sectional view of cutting the control electrode across the field oxide film region of the region 5 after forming the control electrode of the region 9 approximately. Of course, the cross-sectional view taken along line x-x 'in FIG. 5B is as shown in FIG. The height of d3 protruding over the fenced body of the region 2 can be used to form a spacer as indicated by the dotted lines in FIG. 5B, and selectively selects the charge storage node of the region 7 that is revealed after formation of the spacer. It is possible to form a charge storage node only around the cell by almost eliminating d10 without using an additional mask by etching.

6 (a) and 6 (b) are constituted by a slight modification of FIG. 3 (a), which is the structure of the present invention, and there is a change only in the structure of the charge storage node of the region 7. In FIG. 3A, when d5 is almost removed, the configuration becomes FIG. 6A. In FIG. 3A, when the charge storage node is increased from the source / drain junction to the bottom of the recessed region, the charge storage node is increased to the height of d3 corresponding to the height of the control electrode protruding from the surface of the fence body. The structure as shown in 6 (b) can be obtained. Such formation can be achieved through slight changes in the manufacturing process.

FIG. 7 is basically similar to the top view shown in FIG. The only difference is that the edges between the surface and the side of the recessed area remain almost perpendicular. Even in this structure, the charge storage node of the region 7 can be formed only around the cell without the addition of a mask in the self-aligned form described with reference to FIG. 5.

8 shows a plan view of a modified structure of the present invention. 8 (a) almost eliminates d9, which is a length covering a part of the side surface of the region where the charge storage node of the region 7 is recessed, and the charge storage node of the region 7 is connected between the cell and the cell along the control electrode. It is configured to be possible. In this case, when the charge storage node is a conductor, since the cell and the storage nodes between the cells are connected to each other, conductive charge storage materials cannot be used, and an insulating material or a plurality of nano-sized dots that can store charges can be used as the charge storage node. It can be utilized. FIG. 8B is basically similar to FIG. 8A, but in order to limit the charge storage node of the region 7 to only the periphery of the cell, a mask is added to define the storage nodes and the storage nodes are connected between the cells. It was not. Therefore, in this case, as the material of the storage node, nano dots of conductive, insulating, and various materials may be used.

9 (a) and 9 (b) are basically the same as FIGS. 8 (a) and 8 (b), respectively. The difference is that the corners between the surface and the side of the recessed area are rounded.

FIG. 10 is limited to the periphery of the fenced body of the region 2 in order to clearly show the modified structure of the present invention, the field insulating film of the region 5 is omitted to show the recessed region well, and the charge of the region 7 is shown. Three-dimensional perspective view showing the structure immediately after the storage node is formed. The charge storage node of the region 7 is formed only on the side in the recessed region. That is, the storage node is formed from the surface of the fence-like body of the region 2 to the vicinity of the recessed bottom.

11 is a three-dimensional perspective view prepared to clearly show the structural features of the charge storage node as shown in FIG. In the recessed region, the charge storage node of the region 7 is formed only on a part of the side of the recessed region from the fenced body surface of the region 2 to a certain depth of the recessed region.

12 is a three-dimensional perspective view prepared to clearly show the structural features of the charge storage node as shown in FIG. The charge storage node is configured to cover along an edge the inner side surface of the recessed area except the bottom in the recessed area and a part of the outer sidewall of the recessed area in contact with the recessed area. The length covering the outer side of the recessed area is indicated by d9.

FIG. 13 is a three-dimensional perspective view prepared to clearly show the structural features of the charge storage node as shown in FIG. 10. The charge storage node of the region 7 is configured to cover only the vertical side of the side surface in the recessed region and a part of the outer sidewall of the recessed region in contact with the recessed region. The length covering the side walls of the fenced body of the recessed area 2 is indicated by d9. The charge storage node of the region 7 is not formed at the bottom of the recessed area and the side facing the bottom.

14 is a three-dimensional perspective view prepared to clearly show the structural features of the charge storage node as shown in FIG. 3B is a perspective view of the device structure similar to FIG. 3B of the present invention, but the distance between the surface of the fence-like body corresponding to d5 in FIG. 3B and the charge storage node is nearly zero. to be.

FIG. 15 illustrates a cross-sectional structure of a nano-sized dot capable of storing charge as mentioned in the description of FIG. 3 in the structure of FIG. The dot material of the region 10 may be formed of an insulating material capable of storing charge, various metals, Si, Ge, SiGe, and various silicides.

16 shows only three representative profiles of the recessed channel region in the present invention. In FIG. 15A, corners near the bottom of the recessed area are formed at right angles to increase the sensitivity of the threshold voltage to the variation of the substrate voltage and to increase the nonuniformity of device characteristics. 15 (b) is intended to solve the problems such as electric field dispersion or threshold voltage sensitivity increase in the corner by forming a corner near the bottom of the recessed area. Appropriately, by making a semi-circular round profile as shown in FIG. 16C, the corner problem mentioned above can be reduced.

FIG. 17 shows the depression profile of the recessed channel region in the present invention. As shown in FIG. 3A, when the storage node of the region 7 is to be formed only near the source / drain junction with a depth smaller than the depression depth, it is necessary to form the recessed region by etching in two steps. 17 (a) and 17 (b) show a case in which there is almost no change in the width of the depression in the depression depth direction even when etching is performed for the depression in two steps. Both have rounded corners near the recessed floor. However, in the case of (b), a semicircle was formed near the bottom of the recessed area. Figure 17 (c) is to implement by forming a depression width of the first step etching is performed larger than the second step depression width performed later. In FIG. 17D, the recess width of the two-step etching is formed to be greater than the depression width of the one-step etching, as opposed to the case of FIG. 17C. Each of these profiles is applicable to the structure of the present invention.

18 to 20 are prepared to show the channel or body doping formed in the recessed region in the device structure of the present invention as shown in Figure 3 (a). Doping plays a very important role in the recessed channel structure. To indicate the body doping, the doping range and the position of the peak concentration when the Gaussian distribution is assumed are indicated by a dashed dotted line.

In FIG. 18A, three dopings are added to a uniformly doped body. Uniform dough body is in the range of Ping ^{10 15 cm -3 5 × 10 18} cm - is determined to an appropriate value between ^3. Appropriately determined between (ion implantation depth Projected Range) to the dough a dough according to ping peak concentration of the ping is 10 2 × 10 ¹⁹ cm ^-3 cm ^-3 at ¹⁶ the source / drain junction of the ion implantation at R _p DR _p (standard deviation) is changed according to the energy and heat treatment conditions given by ion implantation. The distance at which the peak concentration of body doping formed near the source / drain junction at the fenced body surface of region 2 is formed is represented by d13. The doping profile by ion implantation is usually expressed in ginsian function form or similar function form. In FIG. 18A, the doping is selectively performed only on the channel region under the bottom of the recessed region. The threshold voltage of the device depends largely on the doping level of the bottom channel region, including the corners near the bottom of the depression region. The peak concentration range of the doping, which is formed only below the recessed bottom, is determined between 10 ¹⁵ cm ⁻³ and 5 × 10 ¹⁸ cm ⁻³ . D14 shown in (a) and (b) of FIG. 18 increases the doping concentration below the bottom of the recessed area at the surface of the fence-shaped body of the area 2, and the peak value of the concentration is 10 ¹⁵ cm ^{− It} is determined between ³ and 2 × 10 ¹⁹ cm ⁻³ , and the depth of the peak concentration point from the surface of the body is appropriately determined at less than 500 nm.

In the case of FIG. 18B, the rest is the same except for channel doping formed under the bottom of the recessed area in FIG. 18A. In the structure of the present invention, it is possible to implement a highly integrated device capable of storing one bit, two bits, or more bits in one cell. The bias applied to the control electrode and the source and the drain can be adjusted to generate so-called channel hot carriers, and to the charge storage node of the region 7 formed near the source or drain junction according to a given bias condition. Stored. One bit can be stored near the source / drain, enabling two bits per cell. Therefore, the threshold voltage is preferably determined by the channel near the source / drain junction rather than the channel near the bottom of the recessed region. Threshold voltage is mainly determined by channel doping, so proper design of the doping profile according to the position of the channel formed in the recessed area is very important. In FIG. 18, the body doping deeply formed below the recessed region may be consistent with increasing the impurity concentration under the field insulating layer of the region 5 in some cases, thereby increasing the threshold voltage of the field oxide region. .

FIG. 19A shows that impurities are implanted to form R _p near the source / drain junction depth from the fenced body surface of the region 2 and channel doping is not performed near the recessed bottom. In this case, the threshold voltage is mainly determined by channel doping near the source / drain junction. FIG. 19B shows that the selective doping is formed deep under the bottom of the region recessed in the channel doping profile of FIG. 19A. As mentioned in FIG. 18, the channel doping profile near the source / drain junction is high and the channel doping near the source / drain junction is maintained as the channel doping concentration is kept low while descending near the bottom of the recess. It is desirable to be able to determine by the ping concentration. In FIG. 19B, the doping formed in the channel under the bottom of the recessed channel is deeply formed so that the punch-through that may be between the source and the drain may not be significantly affected by the threshold voltage of the channel near the bottom of the recessed region. may contribute to suppressing punchthrough. The distance from the fenced body surface of the region 2 to the optionally doped peak concentration can be properly determined at less than 500 nm, and the value of the peak concentration is from 10 ¹⁵ cm ⁻³ to 2 × 10 ^19. is determined between cm ^-3 .

20 shows channel doping based on the surface of the recessed area (including side and bottom surfaces). In the case of FIG. 20A, since the doping profile formed on the surface of the recessed sidewall and the surface of the bottom is similar, the threshold voltage is the highest in the channel near the recessed bottom, thereby determining the threshold voltage of the entire device. . There is a rounded corner near the recessed bottom. In this corner region, the threshold voltage increases because the electric field from the control electrode of the region 9 spreads in the corner region channel region. The peak concentration of the body doped along the surface of this recessed region is determined between 10 ¹⁶ cm ⁻³ and 1 × 10 ¹⁹ cm ⁻³ . A suitable way to implement such a profile is to apply plasma immersion doping. It is also possible to make the threshold voltage of the device mainly determined by channel doping near source / drain in FIG. 19 (a), which is a method of increasing the channel doping near source / drain junction introduced in FIG. 19 (a). To (a) of FIG. 20.

In (b) of FIG. 20, as shown by a dashed line to lower the threshold voltage near the bottom of the recessed channel, doping impurities of a type opposite to the channel doping type to lower the threshold voltage are shown. It is shown. The threshold voltage is then controlled by the channel doping concentration or profile formed on the sidewalls of the recessed region, which is similar to the threshold voltage determined by the channel doping near the source / drain junction mentioned above. The voltage can be adjusted. When doping the opposite type of impurity to lower the threshold voltage below the bottom of the recessed channel, adjusting the concentration of the opposite type impurity reduces the original channel doping slightly or the opposite type impurity concentration. Can be made higher than the original channel doping to form impurity regions of the same type as the source / drain regions below the bottom. The depth of the region doped with such an opposite type impurity is indicated by d 16 in FIG. 20B, and is appropriately formed in the range of 0 nm to 100 nm. In FIGS. 20A and 20B, impurities may be formed in a Gaussian profile below the bottom of the region recessed from the fenced body surface of the region 2. Marked d14 raises the doping concentration further below the bottom of the recessed area at the surface of the fenced body of the area (2). The peak value of the concentration is 10 ¹⁵ cm ^-3 to 2 x 10 ¹⁹ cm- ^{. It} is determined between ³ and the depth of the peak concentration point from the surface of the body is appropriately determined at less than 500 nm.

 Figure 21 shows the main process steps as an example of a process for implementing the device structure of the present invention. First, as shown in Fig. 21A, the device isolation process (field insulation film formation) is formed, and then the insulation film of the region 11 is formed. By masking the recessed area, the region 11 is first removed and the fenced body of the exposed region 2 is etched to an appropriate depth. This stage of etching is referred to as first stage etching, and the etching depth is appropriately formed in a range smaller than the final recessed depth. A surface treatment process of the recessed fenced silicon body is performed and an insulating film of the region 12 is formed.

Subsequently, when the charge storage node of the region 7 is formed and anisotropic etching is performed, a charge storage node in the form of a spacer may be formed as shown in FIG. Subsequently, the insulating layer of the exposed region 12 is removed, and further etching is performed on the exposed silicon body in a second step. As shown in (c) of FIG. 21, the corners formed near the bottom of the final recessed area after the second step etching are rounded. An appropriate surface treatment process is performed to form the tunneling insulating film of the region 6. In fact, any of the insulating films of the region 12 formed before forming the storage node of the region 7 and left to the left and right of the storage node without being etched becomes a tunneling insulating film of the region 6. The thicknesses of the insulating film of the region 12 and the insulating film of the region 6 that are finally tunneling insulating films may be the same or different. Preferably, the thickness of the tunneling insulating layer formed after the second step etching is made thicker, so that tunneling of a follower node, Fowler-Nordheim, etc. from the channel region except for the channel region in which the charge storage node is formed, to the control electrode of the region 9. Current can be reduced. After the tunneling insulating film is formed, the inter-electrode insulating film in the region 8 is formed and the step is shown in Fig. 21D.

Subsequently, a control electrode of the region 9 is formed and the step is shown in Fig. 21E. FIG. 21F illustrates a cross-sectional view of the storage node of the region 7 exposed by removing the insulating layer 11 from the region 11 by an appropriate length through etching. The inter-electrode insulating film of the region 8 on the sidewall of the control electrode of the region 9 protruding above the fence-like body surface of the region 2 can also be partially removed depending on the situation.

As described above, the multi-bit flash memory device according to the present invention has both the recessed channel structure and the triple-gate structure, and thus has both the advantages of the existing double / triple-gate and the recessed channel structure. In addition to these advantages, there are the following additional advantages.

First, the existing bulk FinFET requires an active body width corresponding to 2/3 of the gate length. The structure of the present invention has no problem in implementing a body width equal to the gate length in two dimensions, and the advantages intended in the present invention. Can be obtained. Fast erase through the body, improved write / erase through improved control of the channel of the control electrode, reduced threshold voltage due to substrate bias, threshold voltage due to change in impurity concentration at the corner of the recessed channel Change can be reduced.

Second, in the present invention, the channel is formed on the surface and side surfaces of the recessed channel, thereby reducing the distribution of the threshold voltage in the flash memory device due to the high current driving capability and the increase of the effective channel area. Increasing the effective channel area can greatly reduce the distribution of threshold voltage when using nitride or high-k dielectrics as storage nodes, or when nano-scale dots are used as floating storage nodes. There is a characteristic.

Third, since the present invention can deepen the junction depth of the source / drain, the erase speed through the source, the drain, or both can be greatly improved compared to the conventional flat channel structure. By forming charge storage nodes only on the vertical surfaces and sides except near the bottom of the recessed areas, the charge storage nodes are separated from each other around the bottom of the recessed area, resulting in reduced redistribution of stored charges through the program. Memory characteristics can be improved.

Fourth, when the material of the storage node capable of storing charge is an insulator or a nano size dot, one bit may be stored on each of the source and drain sides, thereby enabling two bits per cell. When the storage electrode is completely separated in the form of a spacer, two bits may be realized even if the material of the storage node is conductive.

Claims (41)

A fence-like semiconductor body region is formed on the semiconductor substrate, a first insulating layer is formed on the surface of the substrate and the body region, and a second insulating layer for the field for isolation of the device is formed on the first insulating layer. It is formed up to near the surface, the body is formed to be recessed in a predetermined width and depth from the body surface for the portion to be formed recessed channel in the surface of the body region, The first insulating film formed on the side of the body region and the second insulating film patterned together when the mask pattern is performed for the body depression are formed to be recessed to a predetermined depth from the surface along the portion where the control electrode is to be formed. A third insulating film for tunneling is formed on the surface and some side surfaces of the recessed fence-like semiconductor body, In the recessed region, charge storage nodes are formed on the vertical surface and some side surfaces of predetermined positions, the charge storage nodes are formed to be isolated between the cells, and the fourth insulating film and the control electrode between the electrodes are sequentially formed. Source / drain is formed at a predetermined position of the fence-type body region, And a fifth insulating layer having a predetermined thickness, a contact, and a metal layer formed on the resultant. The method according to claim 1, The control electrode formed in the recessed region of the fence-type semiconductor body, and the control electrode formed in the first insulating film and the second insulating film for the field recessed to a predetermined depth are formed in alignment with the control electrode formed in the body recessed region. Flash memory device, characterized in that the width of the control electrode formed below and different from each other, the width or height of the control electrode protruding above the surface is formed to be the same. A fence-like semiconductor body region is formed on the semiconductor substrate, a first insulating layer is formed on the surface of the substrate and the body region, and a second insulating layer for the field for isolation of the device is formed on the first insulating layer. It is formed up to near the surface, the body is formed to be recessed in a predetermined width and depth from the body surface for the portion to be formed recessed channel in the surface of the body region, The first insulating film formed on the side of the body region and the second insulating film for the pattern patterned together when the mask pattern performed for the body depression is removed is formed by being removed only near the control electrode and the fence-like semiconductor body. A third insulating film for tunneling is formed on the surface and some side surfaces of the fence-type semiconductor body, In the recessed region, charge storage nodes are formed on the vertical surface and some side surfaces of predetermined positions, the charge storage nodes are formed to be isolated between the cells, and the fourth insulating film and the control electrode between the electrodes are sequentially formed. Source / drain is formed at a predetermined position of the fence-type body region, And a fifth insulating layer having a predetermined thickness, a contact, and a metal layer formed on the resultant. The method according to claim 1 or 3, When the charge storage node is formed on the vertical surface of the recessed region of the fence-like semiconductor body and the side of the vertical surface, the width of the charge storage region formed on the side is formed in the range of 1 nm to 50 nm Flash memory devices. The method according to claim 1 or 3, A recessed region is formed in the fence-type semiconductor body region, and the charge storage node formed on the recessed vertical surface and sidewalls is formed in the range of -100 nm to 200 nm based on the source / drain junction depth. Flash memory devices. A fence-like semiconductor body region is formed on the semiconductor substrate, a first insulating layer is formed on the surface of the substrate and the body region, and a second insulating layer for the field for isolation of the device is formed on the first insulating layer. It is formed up to near the surface, the body is formed to be recessed in a predetermined width and depth from the body surface for the portion to be formed recessed channel in the surface of the body region, The first insulating film formed on the side of the body region and the second insulating film patterned together when the mask pattern is performed for the body depression are formed to be recessed to a predetermined depth from the surface along the portion where the control electrode is to be formed. A third insulating film for tunneling is formed on the surface of the recessed fence-like semiconductor body, A charge storage node is formed only on a vertical surface of a predetermined position in the recessed region, and a charge storage node is formed to isolate the cell from the cell. A fourth insulating film and a control electrode between the electrodes are sequentially formed. The source / drain is formed at a predetermined position of the body region, And a fifth insulating layer having a predetermined thickness, a contact, and a metal layer formed on the resultant. A fence-like semiconductor body region is formed on the semiconductor substrate, a first insulating layer is formed on the surface of the substrate and the body region, and a second insulating layer for the field for isolation of the device is formed on the first insulating layer. It is formed up to near the surface, the body is formed to be recessed in a predetermined width and depth from the body surface for the portion to be formed recessed channel in the surface of the body region, The first insulating film formed on the side of the body region and the second insulating film patterned together when the mask pattern is performed for the body depression are formed to be recessed to a predetermined depth from the surface along the portion where the control electrode is to be formed. A third insulating film for tunneling is formed on the surface and some side surfaces of the recessed fence-like semiconductor body, Charge storage nodes are formed on the surface and side surfaces of the recessed region except for the bottom surface, and the charge storage nodes are formed to be isolated between the cells, the fourth insulating film and the control electrode between the electrodes are sequentially formed, and the fence A source / drain is formed at a predetermined position of the body region. And a fifth insulating layer having a predetermined thickness, a contact, and a metal layer formed on the resultant. The method according to claim 7, The width of the charge storage node formed on the side surface of the bottom surface in the recessed body region covering the side is formed of any one of the structure of the same, smaller or larger than the width covering the side surface of the vertical surface in the recessed region Flash memory devices. The method according to claim 7 or 8, And a charge storage node formed on the side of the bottom surface in the recessed region by anisotropic etching. The method according to any one of claims 1, 3, 6, and 7, The width of the fence-like semiconductor body is formed in the range of 4 nm to 200 nm, the height from the semiconductor substrate is formed in the range of 100 nm to 1000 nm. The method according to any one of claims 1, 3, 6, and 7, In the structure of the fence-like semiconductor body, the width of the body to be formed from the surface of the body to the substrate is made constant, the upper portion is narrow and the width is increased while going down, or formed in a uniform thickness from the body surface to an appropriate position And a body configured to increase the width from below the body surface to the substrate. The method according to any one of claims 1, 3, 6, and 7, The width of the recessed region is formed between 10 nm to 200 nm, the depth is formed between 20 nm to 900 nm flash memory device. The method according to any one of claims 1, 3, 6, and 7, And a profile of the recessed region of the fence-like semiconductor body is formed at the same width or different from the bottom of the recessed region. The method according to any one of claims 1, 3, 6, and 7, The edge between the surface and the side surface of the recessed region of the fence-like semiconductor body is formed of any one of a right angle, an obtuse angle, rounded, flash memory device, characterized in that to increase the durability of the device. The method according to any one of claims 1, 3, 6, and 7, The corner formed near the bottom of the recessed region in the fence-like semiconductor body is formed of any one of a right angle, an obtuse angle, rounded, flash memory device, characterized in that to increase the durability of the device. The method according to any one of claims 1, 3, 6, and 7, The third insulating film for tunneling is formed between 0.5 nm and 9 nm on the basis of EOT (equivalent oxide film thickness based on silicon oxide film), and the tunneling insulating film is formed to be thicker except for the tunneling insulating film contacting the charge storage node. A flash memory device characterized by the above-mentioned. The method according to any one of claims 1, 3, 6, and 7, The tunneling material of the third insulating film is a flash memory device, characterized in that using the silicon oxide film or an insulating film having a high dielectric constant. The method according to any one of claims 1, 3, 6, and 7, The thickness of the charge storage node is a flash memory device, characterized in that formed in the range of 1 nm to 50 nm. The method according to any one of claims 1, 3, and 6, A recessed area is formed in the fence body and a tunneling insulating film is formed, and the charge storage node formed on the surface of the tunneling insulating film is formed to have a finite length on a vertical surface, but the length of the charge storage node in the vertical direction is A flash memory device, characterized in that formed between 2 nm and 400 nm, wherein the vertical center portion of the storage node is formed in the range of -200 nm to 200 nm relative to the body surface which is not recessed. The method according to any one of claims 1, 3, and 7, The recessed region is formed in the fence-type semiconductor body, the vertical length of the charge storage node formed on the vertical surface and the side surface of the recessed region is the same or different from each other formed. The method according to any one of claims 1, 3, and 7, When the charge storage node is formed, it is formed to surround the channel formed on the vertical surface of the recessed body and the side channel formed on the side, the distance (or width) surrounding the side channel is formed in the range of 1 nm to 50 nm Flash memory device, characterized in that. The method according to any one of claims 1, 3, 6, and 7, The charge storage node is formed of any one of polysilicon, amorphous silicon, poly SiGe, poly Ge, amorphous Ge, mono and binary metals, and silicide as a conductive material, and a nitride film or a high dielectric constant capable of storing charge as an insulating material. A flash memory device, characterized in that an insulating film having is applied. The method according to any one of claims 1, 3, 6, and 7, The charge storage node is implemented by applying a nano-sized dot, and the material of the dot is formed of any one of conductive polysilicon, amorphous silicon, poly SiGe, poly Ge, amorphous Ge, mono- and binary metals, and silicides. And an insulating material having an insulating film having a high dielectric constant or a nitride film capable of storing charge. The method according to claim 23, The size of the nano-sized dot used as the charge storage node is formed in the range of 1 nm to 40 nm, the shape of the dot is spherical, hemispherical, oval, pyramidal rounded corners or corners, corners or corners The flash memory device of claim 1, wherein the upper portion is hemispherical and the lower portion is formed in any one of a rectangular shape. The method according to any one of claims 1, 3, 6, and 7, In forming the charge storage node, when applying an insulating material capable of storing charge or applying a plurality of nano-sized dots that are electrically isolated from each other, it is possible to resist 1 bit on the source and drain sides, thereby allowing 2 per cell. Flash memory device, characterized in that a bit or more bits can be stored. The method according to any one of claims 1, 3, 6, and 7, When forming the charge storage node, an additional mask is applied to isolate the storage node between the cell and the cell along the word line to form only the charge storage node around the cell, or a mask using a self-aligning method. A flash memory device comprising a charge storage node formed only around a cell without use. The method according to any one of claims 1, 3, 6, and 7, The thickness of the inter-electrode insulating film is formed between 2 nm to 30 nm, the flash memory device, characterized in that the insulating material having different dielectric constants, band gaps, and insulating properties is composed of a single layer or multiple layers. The method according to any one of claims 1, 3, and 7, When the control electrode is formed, it is formed to surround the channel formed on the surface of the recessed body and the side channel formed on the side, the distance (or width) surrounding the side channel is characterized in that formed in the range of 1 nm to 50 nm Flash memory device. The method according to any one of claims 1, 3, 6, and 7, When the control electrode is formed in the recessed body region, it is formed to surround the channel formed in the bottom of the recessed body and the side channel formed on both sides near the bottom of the recessed body, and the vertical distance (or width) surrounding both sides. ) Is a flash memory device, characterized in that formed in the range from 1 nm to 50 nm. The method according to any one of claims 1, 3, 6, and 7, A recessed region is formed in the fence body, and a control electrode formed in the recessed region is formed at a predetermined height within -100 nm to 900 nm based on the surface of the body not recessed. The method according to any one of claims 1, 3, 6, and 7, As the material of the control electrode, polysilicon, poly SiGe, poly Ge doped with n ⁺ and p ⁺ are used, or a monometal such as tungsten, a binary metal such as TiN or TaN, or silicide (polysilicon or poly Flash memory device, characterized in that formed of any one of SiGe) material completely silicided with Ni, Co, Hf and the like. The method according to any one of claims 1, 3, 6, and 7, The source / drain formed in the fence-like semiconductor body can reduce the doping and junction depth in the form of LDD near the recessed region, the depth of the junction is formed in the range of 5 nm to 150 nm. The method according to any one of claims 1, 3, 6, and 7, Doping the source / drain, the maximum impurity concentration of the LDD for NAND flash applications is formed in the range of 1 × 10 ¹⁸ cm ^-3 to 8 × 10 ¹⁹ cm ^-3 , overlapping with the control electrode for NOR flash applications and a maximum impurity concentration of the included source / drain region of the overlapping source / drain region is formed in a range of 5 × 10 ¹⁸ cm ⁻³ to 5 × 10 ²¹ cm ⁻³ . The method according to any one of claims 1, 3, 6, and 7, A recessed region is formed in the fence-type semiconductor body, and the channel doping of the device formed in the recessed region is a uniform basic doping or source / drain junction formed in a range of 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁸ cm ^-3. A flash memory device comprising a Gaussian type doping having a value in the range of 10 ¹⁶ cm ^-3 to 2 × 10 ¹⁹ cm ^{-3 in the} vicinity of a peak concentration. The method of claim 34, wherein In addition to the above-mentioned channel doping, selectively dope only the channel formed near the bottom of the recessed area, but the peak concentration is between 10 ¹⁵ cm ^-3 and 5 x 10 ¹⁸ cm ^-3 , and the position of the peak concentration is not depressed. A flash memory device characterized in that it is doped with a Gaussian function profile of at least 500 nm or less from the body surface. The method according to any one of claims 1, 3, 6, and 7, A recessed region is formed in the fence-type semiconductor body, and the channel doping of the device formed in the recessed region is performed in a uniform basic doping or recessed region formed in a range of 10 ¹⁵ cm ^-3 to 5 × 10 ¹⁸ cm ^-3 . Channel doping is performed on the silicon surface or in the channeled area along the surface and the side, and the peak concentration near the surface is between 10 ¹⁶ cm ^-3 and 1 × 10 ¹⁹ cm ^-3 and composed of Gaussian doping profile. A flash memory device having doping. The method of claim 36, Based on the above doping, since the threshold voltage of the device is high near the bottom of the recessed region, the source / drain type is only near the bottom of the recessed region to prevent the shift of the threshold voltage according to the program. Flash memory device, characterized in that to improve the memory characteristics by doping the impurities to lower the threshold voltage. The method according to claim 35 or 37, In order to suppress possible punchthrough between the source and drain of the device in addition to the dopings given above, the peak concentration is 5 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁹ at a depth within 500 nm from the body surface. A flash memory device having a doping represented by a profile in the form of a Gaussian function formed between cm ⁻³ . The method according to any one of claims 1, 3, 6, and 7, After forming a barrier-type body on the semiconductor substrate, a thin insulating film having a thickness in the range of 0.5 nm to 50 nm may be formed, and a nitride film having a thickness in the range of 1 nm to 100 nm may be formed on the insulating film to form the field insulating film. A flash memory device comprising a nitride film for use in a process for removing a defective defect or for revealing a side of a recessed area in the future. Forming a first insulating film and a second insulating film for a field insulating film on the fence-type semiconductor body region connected to the substrate on the semiconductor substrate; Forming a third insulating film for forming the recessed area and etching the fenced body so as to be smaller than the final recessed depth by removing the third insulating film through a mask operation; Performing a surface treatment process of the recessed fence-like semiconductor body and forming a fourth insulating film; Forming a charge storage node on the resultant but performing anisotropic etching to form a charge storage node in the form of a spacer; Removing the fourth insulating layer and etching the exposed semiconductor body to form round corners formed near the bottom of the region to be finally recessed; Performing a surface treatment process of the recessed semiconductor body and forming a fifth insulating film for tunneling; Forming a sixth insulating film between electrodes on the resultant and forming a control electrode; Removing the third insulating layer to form the exposed charge storage node by a predetermined depth from the surface of the non-dented body; And sequentially forming a source / drain, an interlayer insulating film, a contact, and a metal layer on the fenced body region. The method of claim 40, The tunneling current of the tunneling fifth insulating layer which is formed to be the same or different from each other in thickness of the tunneling fifth insulating layer and the fourth insulating layer, but the thickness of the tunneling fifth insulating layer is thicker than the thickness of the fourth insulating layer so as not to contact the charge storage node. Flash memory device manufacturing method comprising the step of reducing.

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