KR20070042699A - Clock generating apparatus - Google Patents

Abstract

A clock generator for generating a clock signal having a large pulse width and a narrow band clock signal using an external clock is provided.

Clock generation apparatus according to an embodiment of the present invention is output from a clock buffer for adjusting the level of the external clock signal, a clock repeater and a clock repeater for compensating the level of the internal clock signal is output by adjusting the level in the clock buffer, And a narrowband clock generator for shaping and outputting the clock repeater signal passing through the transmission line into a narrowband signal having a narrow pulse width.

According to the present invention, the reliability of the narrowband clock signal can be ensured, and as a result, the error occurrence rate of a device using such a clock signal can be reduced.

Clock, Narrowband Clock

Description

Clock Generator {Clock Generating Apparatus}

1 is a view for explaining the configuration of a general clock generator;

2 is a view for explaining the configuration of a clock generator according to the present invention;

3 is a detailed circuit diagram illustrating an embodiment of a clock buffer and a clock repeater shown in FIG. 2;

FIG. 4 is a detailed circuit diagram illustrating an example embodiment of the narrowband clock generation unit illustrated in FIG. 2.

<Description of the symbols for the main parts of the drawings>

20: clock generator 210: clock buffer

220: clock repeater 230: transmission line

240: narrowband clock generation unit 30, 32: control block

I1, I2: inversion means 242: inversion delay means

244 logic elements

The present invention relates to a clock generator, and more particularly, to a clock generator for generating a clock signal having a large pulse width and a narrowband clock signal using an external clock in a semiconductor memory device.

In general, a device operating in synchronization with a clock signal forms a clock signal applied from the outside for stable operation, and generates and uses an internal clock having a specified level and pulse width.

1 is a view for explaining the configuration of a general clock generator.

As shown in the drawing, the clock generator 10 may pulse the internal clock signal ctd_gen output by adjusting the level of the clock buffer 110 and the clock buffer 110 to adjust the level of the clock signal applied from the outside. Compensating the level of the internal clock signal clk_in that is level-adjusted by the narrowband clock generator 120 and the clock buffer 110 for shaping the narrow narrowband signal to generate a clock signal having a wide pulse width. And a clock repeater 130.

Here, the signals ctd_gen and clk_in output from the clock buffer 110 are the same signals, but are separately displayed because the paths after the output are different.

Meanwhile, the narrowband clock signal ctdb output from the narrowband clock generator 120 is input to the corresponding control block 30 through the transmission line 140 and the clock repeater signal (outputted from the clock repeater 130). clk_in_rpt) is input to the corresponding control block 32 via the transmission line 150.

The narrowband clock signal ctdb is a signal used for a data input / output pin strobe signal and the like, and may be generated to have a positive or negative pulse shape depending on how the narrowband clock generator is implemented.

However, since the narrowband clock signal ctdb is input to the corresponding control block 30 through the long transmission line 140, the level of the pulse decreases or noise interferes while passing through the transmission line 140. There is. This problem causes a logic error of the device using the clock generation device, which degrades the reliability of the device.

In addition, in order to solve this problem, the size of the narrowband clock generation unit must be increased. In this case, power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and disadvantages. The present invention provides a narrowband clock signal immediately before inputting a narrowband clock signal to a control block, thereby securing reliability of a narrowband clock signal. There is.

Another technical problem of the present invention is to improve the slew rate of the narrowband clock signal and reduce the current consumption without increasing the power consumption of the device.

In order to achieve the above technical problem, the present invention buffers an external clock, outputs it through a clock repeater, and inputs a clock signal to a corresponding control block through a transmission line. In this case, when the control block requires the narrowband clock signal, the narrowband clock signal is generated from the clock passing through the transmission line and input to the control block, so that the reliability of the narrowband clock signal through the transmission line is high. The problem of deterioration can be solved.

Clock generation apparatus according to an embodiment of the present invention for this purpose includes a clock buffer for adjusting the level of the external clock signal; A clock repeater for compensating the level of the internal clock signal that is level-adjusted in the clock buffer; And a narrowband clock generator for outputting the clock repeater signal output from the clock repeater and passing through the transmission line into a narrowband signal having a narrow pulse width.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view for explaining the configuration of the clock generator according to the present invention.

As shown in the drawing, the clock generator 20 according to the present invention includes a clock buffer 210 for adjusting a level of a clock signal applied from the outside, and an internal clock signal clk_in that is level-adjusted and output from the clock buffer 210. Narrower for shaping and outputting the clock repeater signal clk_in_rpt outputted from the clock repeater 220 and the clock repeater 220 through the transmission line 230 into a narrow-band signal having a narrow pulse width. The band clock generator 240 is included.

Here, the signal output from the transmission line 230 is input to the corresponding control block 30 so that the control block 30 operates in synchronization with the clock signal, and the narrowband output from the narrowband clock generator 240. The clock signal ctdb is also input to the corresponding control block 32 so that the control block 32 operates in synchronization with the narrowband clock signal ctdb.

As described above, in the present invention, the narrowband clock signal ctdb is not generated in advance and provided to the control block 32 through the transmission line. Instead, the clock repeater signal clk_in_rpt having a wide pulse width through the transmission line is used. By generating the narrowband clock signal ctdb, the slew rate of the narrowband clock signal ctdb can be improved. In addition, it is not necessary to increase or consume power for this purpose, and the current consumption can be reduced because the clock signal is transmitted through one transmission line 230.

FIG. 3 is a detailed circuit diagram illustrating an example of the clock buffer and the clock repeater illustrated in FIG. 2.

In the clock generator 20, the clock buffer 210 serves to change the level of an external clock signal to be used by an internal device. As illustrated in FIG. 3, the clock buffer 210 delays an input signal in to output an output signal. can be implemented by a plurality of inverting means (I1, I2).

In addition, the clock repeater 220 compensates the pulse level so that the internal clock signal output from the clock buffer 210 does not attenuate during the transfer process. As shown in FIG. can be implemented by a plurality of inverting means (I1, I2).

Of course, the size of the circuit illustrated in FIG. 3 may be varied depending on whether the circuit shown in FIG. 3 is used as the clock buffer 210 or the clock repeater 220.

FIG. 4 is a detailed circuit diagram illustrating an example embodiment of the narrowband clock generation unit illustrated in FIG. 2.

In order to generate the narrowband clock signal from the clock signal having the wide pulse width passing through the transmission line, the narrowband clock generator 240 uses the output signal of the transmission line as the first input signal and inverts the transmission line output signal. The delay signal may be implemented as a logic element 244 that outputs a signal having a narrower pulse width than the output signal of the transmission line.

Here, the logic element 244 is preferably implemented with a NAND gate, and the transmission line output signal may be inverted and delayed by, for example, an inversion delay means 242 comprising an odd number of inversion means. In addition, the inversion delay means 242 may of course change the delay time according to the pulse width to be generated.

In the clock generation apparatus of the present invention described above, in generating a clock signal having a large pulse width and a narrow band clock signal from an external clock signal, the clock signal having a large pulse width is transferred through a transmission line, and then the narrow band clock is generated. A narrowband clock signal is generated at the front of the control block that needs the signal.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, high power consumption for maintaining the slew rate of the narrowband clock signal is not required, and current consumption can be reduced because the clock signal is transmitted through one transmission line.

In addition, it is possible to ensure the reliability of the narrowband clock signal, and as a result, it is possible to reduce the error occurrence rate of the device using such a clock signal.

Claims (5)

A clock buffer for adjusting a level of an external clock signal; A clock repeater for compensating the level of the internal clock signal that is level-adjusted in the clock buffer; And A narrowband clock generator for outputting the clock repeater signal output from the clock repeater and passing through the transmission line into a narrowband signal having a narrow pulse width; Clock generating apparatus comprising a. The method of claim 1, The narrowband clock generator comprises a logic element configured to output a signal having a pulse width equal to the inversion time by inputting an output signal of the transmission line and an inverted delayed signal of the transmission line output signal. Device. The method of claim 2, The logic device is a clock generator, characterized in that the NAND gate. The method of claim 1, And the clock buffer comprises a plurality of inverting means. The method of claim 1, And the clock repeater comprises a plurality of inverting means.

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