KR20070042318A - Semiconductor device having dummy active layer and layout therefor - Google Patents

Abstract

A semiconductor device having a dummy active layer connected to each other and a layout thereof are disclosed. According to the layout of the semiconductor device of the present invention, the upper and lower portions of the dummy active region are connected to each other by the connecting trench region. Therefore, in the semiconductor device of the present invention, substantial shrinkage of the dummy active region is remarkably alleviated. In particular, according to the semiconductor device of the present invention, space generation and eccentricity in the recess channel array trench are significantly alleviated.

Semiconductor, Layout, Dummy Active, Space Generation, Shrink

Description

Semiconductor device having a dummy active layer connected to each other and its layout {SEMICONDUCTOR DEVICE HAVING DUMMY ACTIVE LAYER AND LAYOUT THEREFOR}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a part of the layout of a conventional semiconductor device.

FIG. 2 is a diagram for describing a semiconductor device after a predetermined process is performed according to the layout of FIG. 1.

3 is a cross-sectional view taken along line AA ′ in the layout of the semiconductor device of FIG. 2.

4 is a diagram illustrating a part of a layout of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram for describing a semiconductor device after a manufacturing process is performed according to the layout of FIG. 4.

FIG. 6 is a cross-sectional view taken along line BB ′ in the layout of the semiconductor device of FIG. 5.

Explanation of symbols on the main parts of the drawings

111: main active area 113: dummy active area

114: connection active region 115: gate electrode region

117, 118a, 118b: recess channel array trench region

TECHNICAL FIELD The present invention relates to a semiconductor device and its layout, and more particularly, to a semiconductor device having a dummy active layer and an area and a layout thereof.

In general, in the layout of a semiconductor device, a cell block including cells used for actually storing data is arranged. In addition, for stable patterning of cells disposed at the outermost side of the cell block, a dummy cell block is disposed at the outer side of the cell block. Dummy cells are formed in the dummy cell block. In the present specification, in order to distinguish the dummy cell and the dummy cell block, a cell actually used for storing data may be referred to as a 'main cell', and a cell block including the main cells may be referred to as a 'main cell block'. Can be.

On the other hand, the line width of the pattern actually formed on the semiconductor substrate tends to shrink than the line width of the pattern laid out on a reticle that selectively passes the exposure light. That is, the pattern formed on the semiconductor substrate is inclined at a positive inclination due to the limitation of the resolution of the exposure light. As a result, the line width of the pattern shrinks somewhat. The shrinkage phenomenon of the pattern line width is intensified toward the edge of one semiconductor device. Further, it is deepened in the semiconductor device disposed at the edge of the wafer.

1 is a view showing a part of a layout of a conventional semiconductor device, and shows a part of a main cell block and a dummy cell block. 2 is a diagram for describing a semiconductor device after a predetermined process is performed according to the layout of FIG. 1. 1 and 2, in the main cell block BLK1, a plurality of main active regions 11 are formed on a matrix structure in which main cells (not shown) that are actually used for storing data are formed. In addition, the dummy active regions 13 in which dummy cells (not shown) which are not used for storing data are formed outside the main cell block BLK1 are arranged. In addition, the gate electrode regions 15 are formed to extend in the horizontal direction to penetrate the main active region 11 and the dummy active region 13. According to the semiconductor device of FIG. 1, as the dummy cells are arranged, the main cells disposed at the outermost portion of the main cell block BLK1 may be stably patterned, and thus, the loading effect and the structure vehicle may be affected. The difficulty of the process can be alleviated.

However, in the layout of FIG. 1, the dummy active regions 13 are separated from each other. In this case, in the manufacturing process of the semiconductor device, the shrinkage phenomenon of the pattern occurs in all the boundary surfaces of the left and right dummy active regions 13 (see t1 to t4 in FIG. 2). The shrinkage phenomenon of the dummy active regions 13 may act as a factor that prevents formation of other patterns formed in the semiconductor device. For example, when the pattern of the dummy active region 13 is severely shrunk, as shown in FIG. 3, a recess channel array trench formed in the dummy active layer 13 ′ along the dummy active region 13 ( The inlet exposed surface of 18a ') may be significantly retracted. In this case, a phenomenon occurs in which the gate electrode layer 15 'blocks the inlet of the recess channel array trench 18a'. As a result, the interior of the recess channel array trench 18a 'may not be sufficiently buried, and a void may be formed (see TR1 in FIG. 3). Reference numerals in FIG. 3 are added with a subscript '' to the reference numerals of the components involved in FIGS. 1 and 2. In addition, in FIG. 3, the separation layer may be performed by a LOCOS or a trench process, but is illustrated in a simple plane for clarity of the present invention.

As described above, in the conventional semiconductor device and its layout, the shrinkage of the pattern of the dummy active region 13 is very serious, which causes the problem of disturbing other patterns.

Accordingly, an object of the present invention is to solve the problems of the prior art, and to provide a semiconductor device and its layout which can alleviate shrinkage of the pattern of the dummy active region in the manufacturing process of the semiconductor device.

One aspect of the present invention for achieving the above technical problem relates to the layout of a semiconductor device. The layout of the semiconductor device of the present invention includes a main cell block and a dummy cell block disposed at an edge of the main cell block, a plurality of main active regions arranged in a matrix structure having rows and columns on the main cell block, and the dummy cell. A plurality of dummy active regions disposed in a block, the dummy active regions having a length of each long axis smaller than or equal to a length of the long axis of the main active region, the main active regions and the dummy active regions along the rows; And a plurality of gate electrode regions formed in one direction to traverse and connection active regions connecting the dummy active regions.

Another aspect of the present invention for achieving the above technical problem relates to a semiconductor device. The semiconductor device of the present invention includes a semiconductor substrate having a main cell block and dummy cell blocks disposed at an edge of the main cell block, and a respective main body disposed on a semiconductor substrate of the main cell block and formed of a matrix structure consisting of rows and columns. A plurality of main active layers in which cells are formed, a plurality of dummy active layers disposed on a semiconductor substrate of the dummy cell block, wherein a plurality of dummy active layers in which respective dummy cells are formed, the main active layers and the dummy active layer along the rows And a plurality of gate electrode layers formed in one direction while crossing the gap, and connection active layers connecting the dummy active layers to each other.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the technical spirit of the present invention to be thoroughly and completely posted, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

4 is a diagram illustrating a part of a layout of a semiconductor device according to an embodiment of the present invention. In FIG. 4, the main cell block BLK1 and the dummy cell block BLK2 are shown. In this case, the dummy cell block BLK2 is disposed at an edge of the main cell block BLK1. In FIG. 3, for convenience of explanation, only the dummy cell block BLK2 disposed at one edge of the main cell block BLK1 is representatively shown. And, for the sake of clarity, only the gate electrode region, the active region and the recess channel array trench region are shown.

A plurality of main active regions 111 are disposed in the main cell block BLK1. In this case, the main active region 111 is arranged in a matrix structure consisting of rows and columns. In addition, a plurality of main cells (not shown) are formed in the main active region 111. As mentioned above, the main cell herein refers to the cell that is actually used to store the data.

A plurality of dummy active regions 113 are disposed in the dummy cell block BLK2. In the dummy active region 113, dummy cells (not shown) that are not actually used to store data are formed. The length k1 of the long axis of each of the dummy active regions 113 is equal to or smaller than the length k2 of the long axis of the main active region 111.

In the present embodiment, the main active region 111 and the dummy active region 113 are formed in a diagonal direction. When the main active region 111 and the dummy active region 113 are formed in a diagonal direction, the effect according to the embodiment of the present invention is more remarkable.

A plurality of gate electrode regions 115 cross the main active regions 111 and the dummy active regions 113 along the rows, in one direction (in the horizontal direction, in the embodiment of FIG. 4). Is formed.

In the layout of the semiconductor device of the present invention, the connection active regions 114 are further provided. The connection active regions 114 connect the dummy active regions 113 to each other. That is, the dummy active regions 113 form one active region by the connection active regions 114.

Preferably, the connection active region 114 connects the dummy active region 113 to each other in a direction crossing the gate electrode regions 115.

Each of the main active region 111 and the dummy active region 113 includes recess channel array trench regions 117 and 118 corresponding to each other. In addition, the recess channel array trench regions 117 and 118 are included in the corresponding gate electrode region 115.

In the embodiment of FIG. 4, the main active regions 111, the dummy active regions 113, and the connection active regions 114 are the same layout layer that is performed simultaneously in a semiconductor manufacturing process. Is preferably. In this case, the dummy active regions 113 and the connection active regions 114 are not substantially divided. In this case, a boundary between the dummy active region 113 and the connection active region 114 may be a virtual line.

In addition, the connection active regions 114 may be layout layers separate from the main active regions 111 and the dummy active regions 113.

FIG. 5 is a diagram for describing a semiconductor device after a manufacturing process is performed according to the layout of FIG. 4. Referring to FIG. 5, when the manufacturing process of the semiconductor device is actually performed, the interface of the dummy active region 113 may be significantly contracted. In this case, the shrinkage width t11 of the outer boundary surface of the dummy active region 113 is generally larger than the shrinkage width t12 of the other boundary.

However, in the semiconductor device of the present invention, the upper or lower boundary surface is connected to the connection active region 114. Therefore, the contraction phenomenon of the interface above and below the dummy active region 113 does not occur substantially.

Accordingly, it can be seen that the shrinkage phenomenon of the recess channel array trench region 118a is also significantly reduced compared to the shrinkage phenomenon of the recess channel array trench region 18a in the related art shown in FIG. 2.

FIG. 6 is a cross-sectional view taken along line BB ′ in the layout of the semiconductor device of FIG. 5. In FIG. 6, only the dummy active layer 113 ′, the connection active layer 114 ′, the gate electrode layer 115 ′, and the recess channel array trench layers 118a ′ and 118b ′ are shown for a clear understanding of the present invention. do. However, it will be apparent to those skilled in the art that a base oxide film or the like may be formed between the semiconductor substrate 110 and the gate electrode layer 115 '. It will be apparent to those skilled in the art that various protective films may be formed in the recess channel array trench layers 118a 'and 118b' and the gate electrode layer 115 '.

In addition, the dummy active layer 113 ′, the connection active layer 114 ′, and the gate electrode layer 115 ′ each include the dummy active region 113, the connection active region 114, and the gate electrode region (FIG. 5). 115). The recess channel array trench layers 118a 'and 118b' are formed along the recess channel array trench regions 118a and 118b of FIG. 5. In addition, although not shown in FIG. 6, the main active region 111 of FIG. 5 may be formed as a main active layer.

Referring to FIG. 6, as described above, the dummy active layer 113 ′ is connected to the connection active layer 114 ′. Therefore, shrinkage of the upper and lower portions of the dummy active layer 113 'is prevented. Therefore, the blockage of the inlet of the recess channel array trenches 118a 'and 118b' is significantly alleviated. In particular, according to the semiconductor device of the present invention, space generation and eccentricity in the recess channel array trenches 118a 'and 118b' can also be reduced as compared with the related art of FIG. 3.

According to the layout of the semiconductor device of the present invention as described above, the upper and lower portions of the dummy active region are connected to each other by the connection trench region. Therefore, in the semiconductor device of the present invention, substantial shrinkage of the dummy active region is remarkably alleviated. In particular, according to the semiconductor device of the present invention, space generation and eccentricity in the recess channel array trench are significantly alleviated.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

For example, in this specification, the embodiment in which the main active region is formed in the diagonal direction is shown and described. However, it will be apparent to those skilled in the art that the present invention can produce significant effects even in embodiments in which the main active region is formed in a rectangular or other form.

Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (9)

A dummy cell block disposed at an edge of a main cell block and the main cell block; A plurality of main active regions arranged in a matrix structure consisting of rows and columns in the main cell block; A plurality of dummy active regions disposed in the dummy cell block, each of the dummy active regions having a length of each long axis smaller than or equal to a length of the long axis of the main active area; A plurality of gate electrode regions formed in one direction across the main active regions and the dummy active region along the rows; And And connection active regions connecting the dummy active regions. The method of claim 1, wherein the dummy active regions are formed. A layout of the semiconductor device, wherein the connection active regions are connected in a direction crossing the gate electrode regions. The method of claim 2, The main active region and the dummy active region And a corresponding recess channel array trench region. The method of claim 1, wherein the main active area is A layout of a semiconductor device, characterized in that the major axis is in a diagonal direction. The method of claim 1, wherein the main active regions, the dummy active regions and the connection active regions are formed. A layout of a semiconductor device, characterized in that the same layout layer for simultaneous processes. A semiconductor substrate having a main cell block and dummy cell blocks disposed at an edge of the main cell block; A plurality of main active layers disposed on the semiconductor substrate of the main cell block, each main cell being formed in a matrix structure consisting of rows and columns; A plurality of dummy active layers disposed on the semiconductor substrate of the dummy cell block, each dummy cell being formed; A plurality of gate electrode layers formed in one direction across the main active layers and the dummy active layer along the rows; And And connecting active layers connecting the dummy active layers to each other. The method of claim 6, wherein the dummy active layer And the interconnection active layer is connected to each other in a direction crossing the gate electrode layers. The method of claim 7, wherein The main active layer and the dummy active layer Forming recess channel array trenches under the corresponding gate electrode layer. The method of claim 6, wherein the dummy active layer A semiconductor device comprising both ends in the end direction of each of said gate electrodes.

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