KR20070038673A - Repair circuit for semiconductor memory device - Google Patents

Abstract

A repair circuit of a semiconductor memory device capable of outputting a repair signal of a memory cell at high speed is provided.

The repair circuit of the semiconductor memory device of the present invention receives a pre-decoded address signal as the active signal is enabled, checks whether the input address matches the address of the blocked fuse circuit, and receives a high or low level signal. An address comparison unit outputting to the first node; If the address signal inputted to the enable signal generator and the address comparator for outputting the repair signal according to the potential applied to the first node does not match at least one of the address signals of the blocked fuse circuit, it is applied to the first node. And a level compensation unit for inducing the current to the ground terminal.

According to the present invention, a repair signal instructing to detect a redundancy address can be generated at high speed, and the overall operation speed of the memory element can be improved.

Memory, Repair

Description

Repair Circuit for Semiconductor Memory Devices

1 is a circuit diagram showing a repair circuit of a general semiconductor memory device;

2 is an operation timing diagram of the repair circuit shown in FIG. 1;

3 is a block diagram illustrating a repair circuit of a semiconductor memory device according to the present invention;

4 is a detailed circuit diagram of the repair circuit shown in FIG. 3;

5 is an operation timing diagram of the repair circuit shown in FIG. 4.

<Description of the symbols for the main parts of the drawings>

100: address comparison unit 200: enable signal generation unit

300: level compensator 110: fuse circuit

120: switch circuit

The present invention relates to a semiconductor memory device, and more particularly, to a repair circuit of a semiconductor memory device capable of outputting a repair signal of a memory cell at a high speed.

In general, a memory device is composed of a large number of cells. If a defect occurs in any of these cells, the memory device malfunctions and is treated as a defective product. Accordingly, a repair circuit for recognizing a defect in a cell in advance and then switching a connection to a cell included in a redundancy circuit is used instead of the defective cell when a request for access to the cell is received. Here, the redundancy circuit is a set of extra memory cells provided separately in the memory cells, and is used as a replacement cell of a cell in which a defect has occurred.

FIG. 1 is a circuit diagram of a repair circuit of a general semiconductor memory device, and searches for a redundancy address by combining output signals of the repair circuit for each address group. The operation of the repair circuit shown in FIG. 1 will be described with reference to the timing chart shown in FIG. 2 as follows.

First, a general repair circuit includes an address comparator 10 and an enable signal generator 20. Here, the address comparison unit 10 may be connected to the switch circuits 12 and the switch circuits 12 depending on whether the plurality of switch circuits 12 and the memory cells are driven according to the pre-decoded address signal lax, respectively. A plurality of fuse circuits 14 to be connected or disconnected are included. Here, the switch circuit 12 may be configured using a transistor, and configured to correspond to each of the pre-decoded address signals.

In the memory device having such a repair circuit, for example, after the active signal RACTV is applied at the first time t1 for an active operation, a delay signal (bact) and a pre-decoded address signal of the active signal are applied. (lax) is applied to the repair circuit. Here, the pre-decoded address signal lax is a result of pre-decoding A2 to A12 excluding A0 and A1 for use in bank selection when the input address group is A0 to A12, for example, lax2 < 0: 1>, lax34 <0: 3>, lax56 <0: 3>, lax78 <0: 3>, lax9A <0: 3>, and laxBC <0: 3>.

The repair circuit shown in FIG. 1 includes the first bit of lax2 (lax4 <0>), the first bit of lax34 (lax34 <0>), the first bit of lax56 (lax56 <0>), and the first bit of lax78 ( The fuse circuit connected to the switch circuit driven by lax78 <0>, the second bit of lax9A (lax9A <1>), and the first bit of laxBC (laxBC <0>), respectively, is cut off.

In this state, when the address signal pre-decoded and input to the repair circuit coincides with the address of the interrupted fuse circuit (input address is 010000), the output node n1 of the address comparison section 10 sets a high level. Will be maintained. Thereafter, as the delay signal bac of the active signal is applied, the first P-type transistor P1 of the enable signal generator 20 is turned off and the inverting element 22 which inverts the level of the node n1. The second P-type transistor P2, driven by the output signal of &lt; RTI ID = 0.0 &gt; 1, &lt; / RTI &gt; is turned on, resulting in node n1 maintaining a high level.

On the other hand, as the reset signal tm_xyrst of the repair circuit is applied at a low level, the output signal of the inverted delay element 24 and the level of the node n1 are used as input signals, and only low when both input signals are high level. The output signal of the logic element 26 that outputs the signal, that is, the repair signal hitb <0> is at a low level.

As described above, when the input address and the address of the blocked fuse circuit coincide with each other, it can be seen that the repair signal hitb <0> is at a high level.

On the other hand, a case where the input address and the address of the blocked fuse circuit is inconsistent will be described as follows.

First, the operation of the repair circuit for the case where most of the input address signal is inconsistent with the address signal of the cut off fuse circuit will be described. For convenience of explanation, the second bit of lax2 (lax2 <1>), the second bit of lax34 (lax34 <1>), the second bit of lax56 (lax56 <1>), and the second bit of lax78 (lax78 <1>) For example, a case where the first bit lax9A <0> of lax9A and the first bit laxBC <0> of laxBC are input as an address signal will be described.

In this case, since the switch circuit driven by an address signal other than laxBC is in a state of being connected with the fuse circuit, the current applied to the node n1 is quickly induced to the ground terminal, and the node n1 transitions to the low level. Accordingly, the second P-type transistor P2 is turned off, a low level signal is input to the logic element 26, and the repair signal hitb <0> becomes a high level. As shown in FIG. 2, it can be seen that the potential of the node n1 starts to drop at the second time t2 and drops completely to the ground potential when the third time t3 is reached.

However, when only a part of the input address signals are inconsistent with the address signals of the blocked fuse circuits, it takes a long time for the potential of the node n1 to drop to the ground potential. For example, if the other address signal matches the address signal of the blown fuse circuit, and only the second bit lax2 <1> of lax2 is inconsistent, the current of the node n1 is driven by the second bit signal of lax2. Since it is induced to the ground terminal only by the switch circuit, it takes a long time to output the repair signal hitb <0>.

Referring to FIG. 2, after the active signal RACTV is input at the fourth time t4 and the delay signal bact of the active signal is applied, the potential of the node n1 is applied at the fifth time t5. It starts to fall and becomes fully ground potential at the sixth time t6, which is compared to the time difference from the second time t2 to the third time t3 from the fifth time t5 to the sixth time t6. It can be seen that the time difference is quite large.

As such, when only a part of the input address signal coincides with the address signal of the cut-off fuse circuit, it takes a long time to output the repair signal, which slows the overall operation of the device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described disadvantages, and has a technical problem to provide a repair circuit capable of outputting a repair signal at high speed during an active operation of a memory device.

In order to achieve the above technical problem, the repair circuit of the present invention receives a pre-decoded address signal as the active signal is enabled, and checks whether the input address matches the address of the blown fuse circuit, thereby making it high or low. An address comparator for outputting a level signal to the first node; An enable signal generator for outputting a repair signal according to a potential applied to the first node; And a level compensator for inducing a current applied to the first node to a ground terminal when the address signal inputted to the address comparator and at least one address signal of the cutoff fuse circuit do not coincide with each other.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a repair circuit of a semiconductor memory device according to the present invention.

As shown, the repair circuit of the present invention receives a pre-decoded address signal lax and outputs a high or low level signal according to whether the input address matches the address of the blocked fuse circuit. ), An enable signal generator 200 and an address comparer 100 for outputting a repair signal hitb <0> according to a potential applied to the first node n11. And a level compensator 300 for guiding the current applied to the first node n11 to the ground terminal when the address signal inputted to the at least one address of the blocked fuse circuit does not match.

4 is a detailed circuit diagram of the repair circuit shown in FIG. 3, and FIG. 5 is an operation timing diagram of the repair circuit shown in FIG. 4. Referring to this, the operation of the repair circuit according to the present invention will be described below.

As shown in FIG. 4, the address comparison unit 100 may be connected to the switch circuit 110 and the switch circuit 110 depending on whether the plurality of switch circuits 110 and memory cells are driven according to the pre-decoded address signal lax. A plurality of fuse circuits 120 to be connected or disconnected. Here, the switch circuit 110 may be configured to correspond to the pre-decoded address signals using transistors, respectively.

In addition, the enable signal generator 200 is connected between the power supply terminal VDD and the first node n11 to drive the first P-type transistor P11 and the first driven by a delay signal of the active signal. A first inverting element 210 for inverting the signal applied to the node n11, a second terminal connected between the power supply terminal VDD and the first node n11 and driven by an output signal of the first inverting element 210; 2 P-type transistor P12, an inversion delay element 220 for inverting and delaying the reset signal tm_xyrst, and a signal applied to the first node n11 and an output signal of the inversion delay element 220 as inputs. And a logic element 230 that outputs a low level signal as a repair signal hitb (<0>) only when both input signals are high level, where the inversion delay element 220 has an odd number of inverting elements. Can be configured in series and the logic element 230 is configured as a NAND gate, for example. Can.

In addition, the level compensator 300 is connected between the second inversion element 310, the first node n11, and the ground terminal to invert the potential applied to the first node n11 to output to the second node. A second N-type transistor N1 driven by a signal applied to the second node n12 and a second node connected between the second node n12 and the ground terminal and driven by an inversion delay signal bk_cmd of the active signal. And an N-type transistor N2. Here, the inversion delay signal bk_cmd of the active signal preferably has a delay time shorter than that of the delay signal bact of the active signal.

In the memory device having the repair circuit, since the delay signal bact of the active signal is at the low level in the precharge state, the first node n11 maintains a high level and inverts the signal applied to the first node n11. The second node n12 is turned low by the signal, and the first N-type transistor N1 is turned off, and the second N-type transistor N2 is turned on by the inversion delay signal bk_cmd of the active signal. Thus, the first node n11 still maintains a high level.

Meanwhile, after the active signal RACTV is applied at the first time t11 for the active operation, the delay signal bact and the pre-decoded address signal lax of the active signal are applied to the repair circuit. Here, the pre-decoded address signal lax is a result of pre-decoding A2 to A12 excluding A0 and A1 for use in bank selection when the input address group is A0 to A12, for example, lax2 < 0: 1>, lax34 <0: 3>, lax56 <0: 3>, lax78 <0: 3>, lax9A <0: 3>, and laxBC <0: 3>.

The repair circuit shown in FIG. 4 includes the first bit of lax2 (lax4 <0>), the first bit of lax34 (lax34 <0>), the first bit of lax56 (lax56 <0>), and the first bit of lax78 (lax78 <0>). ), the fuse circuit connected to the switch circuit driven by the second bit lax9A <1> of lax9A and the first bit laxBC <0> of laxBC is broken.

In this state, when the address signal pre-decoded and input to the repair circuit coincides with the address of the blocked fuse circuit (the input address is 010000), the first node n11 maintains a high level. Thereafter, as the delay signal bac of the active signal is applied, the first P-type transistor P11 of the enable signal generator 200 is turned off and the first node inverting the level of the first node n11 is performed. The second P-type transistor P12 driven by the output signal of the inverting element 210 is turned on, and as a result, the first node n11 maintains a high level.

On the other hand, the first N-type transistor N1 is turned off by the output signal of the second inverting element 310 which inverts the high level signal applied to the first node n11, and the inversion delay signal of the active signal. Since bk_cmd is at the low level, the second N-type transistor N2 driven thereby is turned off so that the first node n11 maintains the high level.

In addition, since the reset signal tm_xyrst is at a low level, the low signal is applied only when both input signals are at a high level by using the output signal of the inversion delay element 220 and the signal applied to the first node n11 as input signals. The output signal of the output logic element 230, that is, the repair signal hitb <0> is at a low level.

As such, when the input address coincides with the address of the blocked fuse circuit, the repair signal hitb <0> is at a low level.

On the other hand, a case where the input address and the address of the blocked fuse circuit is inconsistent will be described as follows.

First, the operation of the repair circuit for the case where most of the input address signal is inconsistent with the address signal of the cut off fuse circuit will be described. For convenience of description, the second bit of lax2 (lax2 <1>), the second bit of lax34 (lax34 <1>), the second bit of lax56 (lax56 <1>), the second bit of lax78 (lax78 <1>), A case where the first bit lax9A <0> of lax9A and the first bit laxBC <0> of laxBC are input as an address signal will be described as an example.

In this case, since the switch circuit driven by an address signal other than laxBC is in a state of being connected with the fuse circuit, the current applied to the first node n11 is induced to the ground terminal. On the other hand, the output of the second inverting element 310 which inverts the signal applied to the first node n11 is at a high level so that the first N-type transistor N1 is turned on, and the inversion delay signal bk_cmd of the active signal is turned on. The second N-type transistor N2, driven by N1) is turned off so that the current applied to the first node n11 is induced to the ground terminal through the first N-type transistor N1.

As a result, the second P-type transistor P12 is turned off, and a low level signal is input to the logic element 230 so that the repair signal hitb <0> becomes a high level. As shown in FIG. 5, it can be seen that the potential of the first node n11 starts to drop in the second time t12 and drops completely to the ground potential when the third time t13 is reached.

Next, a case where only a part of the input address signal is inconsistent with the address signal of the blocked fuse circuit will be described. For example, when the other address signal matches the address signal of the blown fuse circuit and only the second bit lax2 <1> of lax2 is inconsistent, the current of the first node n11 is caused by the second bit signal of lax2. It is induced to the ground terminal by a switch circuit driven.

In addition, a switch circuit in which the first N-type transistor N1 driven by the inverted signal of the first node n11 is turned on and the current induced in the first node n11 is driven by the second bit signal of lax2. In addition, the potential of the first node n11 can be quickly shifted to a low level because it is induced to the ground terminal through the first N-type transistor N1.

As a result, it is possible to effectively reduce the time required to output the repair signal hitb <0>.

Referring to FIG. 5, for example, an active signal RACTV is input at a fourth time t14, a delay signal bact of an active signal is subsequently applied, and then a first node at a fifth time t15. The potential of (n11) starts to drop and becomes a ground potential completely at the sixth time t16, which is equal to the transition time from the fifth time t5 to the sixth time t6 in the timing diagram shown in FIG. In comparison, it can be seen that the transition time to ground potential is very short.

As described above, by generating the repair signal at a high speed, a subsequent redundancy address search process and the like can also be quickly performed to improve the overall operation speed of the memory device.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, when a fuse circuit address for converting an input address and a defective cell into a redundant cell is inconsistent, a repair signal instructing to detect the redundant address can be generated at high speed.

Accordingly, the overall operating speed of the memory device can be improved, thereby improving the reliability of the product.

Claims (7)

A repair circuit of a semiconductor memory device, which receives a pre-decoded address signal as an active signal is enabled, checks whether an input address coincides with an address of a blocked fuse circuit, and receives a high or low level signal. An address comparison unit outputting to the node; An enable signal generator for outputting a repair signal according to a potential applied to the first node; And A level compensator for inducing a current applied to the first node to a ground terminal when the address signal inputted to the address comparator and at least one address signal of the cutoff fuse circuit do not match; A repair circuit for a semiconductor memory device, comprising: The method of claim 1, The address comparison unit includes a plurality of switch circuits respectively driven according to the pre-decoded address signal; And A plurality of fuse circuits connected to or disconnected from the switch circuit depending on whether a memory cell is defective; Repair circuit of a semiconductor memory device comprising a. The method of claim 1, The enable signal generator includes a first P-type transistor connected between a power supply terminal and the first node and driven by a delay signal of the active signal; A first inversion element for inverting the signal applied to the first node; A second P-type transistor connected between the power supply terminal and the first node and driven by an output signal of the first inverting element; An inversion delay element for inverting the reset signal of the repair circuit; And A logic element configured to input a signal applied to the first node and an output signal of the inversion delay element, and output a low level signal as a repair signal only when both input signals are high level; Repair circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The inversion delay element may include an odd number of inversion elements connected in series. The method of claim 3, wherein The logic device is a repair circuit of a semiconductor memory device, characterized in that composed of a NAND gate. The method of claim 1, The level compensator may include a second inversion element for inverting a potential applied to the first node and outputting the inverted voltage to a second node; A first N-type transistor connected between the first node and a ground terminal and driven by a signal applied to the second node; And A second N-type transistor connected between the second node and a ground terminal and driven by an inverted delay signal of an active signal; Repair circuit of a semiconductor memory device comprising a. The method of claim 6, The inverted delay signal of the active signal has a shorter delay time than the delay signal of the active signal.

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