KR20070035525A - Bi-directional current sensing by monitoring vs voltage in a half or full bridge circuit - Google Patents

Abstract

The present invention relates to an apparatus and method for determining the output current in a switch transistor output circuit with bridges connected in a typical MOSFETS, including high side and low side transistor switches. The voltage is sensed at the common node between the high and low side switches, and the voltage is offset in the first circuit by a fixed total amount to have a positive value for any positive or negative output current of interest. The output current is actually determined in a second circuit that receives the offset voltage at a predetermined time in relation to the time at which the low side switch is turned on. The first circuit includes a current reference source / level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration. The second circuit is coupled to the output of the first circuit by a gate NMOS transistor at the time required to provide a current measurement signal. The second circuit includes a second current reference source having electrical characteristics essentially the same as the first current reference source, the second plurality of transistors each matching the output side circuit transistors and having the same circuit configuration. Connected with In the second circuit, the offset signal is compared with high and low side reference signals to provide an indication if the output current exceeds the overcurrent limit positively or negatively. The sensing circuit is advantageously integrated with the output circuit gate driver in a single IC.

Half-Bridge or Full-Bridge Circuit, Bidirectional Current Sensing

Description

BI-DIRECTIONAL CURRENT SENSING BY MONITORING VS VOLTAGE IN A HALF OR FULL BRIDGE CIRCUIT}

This application entails priority based on US provisional application 60 / 576,829, filed June 2, 2004, and all disclosures of this provisional application are incorporated herein by reference.

This application is also filed on March 23, 2004, filed under the name of Dana Wilhelm, and relates to US Patent Application No. 10 / 806,668, entitled "High Bolt Offset Sensing Circuits and Methods," and all disclosures of this application. Which is incorporated herein by reference.

The present invention relates to a method and apparatus for bidirectional current sensing for high power half and full bridge transistor circuits, and in particular, such a method and apparatus has no insertion of any component into the power circuit and the bridge It can be fully integrated into the driver IC.

The present invention will be described with a half bridge MOSFET circuit in the background, but it should also be understood that the disclosed concept can be directly applied to circuits using other forms or power transistors, and to circuitry within a full bridge topology. .

High voltage half bridge and full bridge power circuits are used in a variety of applications such as motor drives, fluorescent electric ballasts and power supplies. A simple half bridge circuit is illustrated in (10) in FIG. The circuit is connected to a common point 14 between the MOSFETS and through a first circuit path comprising MOSFET M _HS and capacitor C1 and through a second circuit path comprising MOSFET M _LS and capacitor C2 and between the two capacitors. Between high and low side totem poles are connected between MOSFETs M _HS and M _LS , which are connected to a second common point 16 to provide a load 12 between C1 and C2.

Gate drive circuit 18, a typical IC, supplies gate drive signals to turn MOSFETS M _HS and M _LS on and off in response to logic input signals H _IN and L _IN .

In applications involving half bridge or full bridge topologies, current sensing is required for feedback or to prevent run away situations. Conventional methods of current sensing require inserting external components, such as resistors, in the power circuit, for example, between MOSFETs M _HS and M _LS (not shown), which is disturbing, i.e., reduces power consumption. Causing extra pins on the driver IC.

Moreover, for example in class-D amplifiers in any high power bridge topology application, the power transistors are connected between positive and negative bolt rails rather than the high voltage rail and ground as illustrated in FIG. In this case, both positive or negative currents may appear. To be used in all power bridge applications, the measurement circuitry in the driver IC must be able to adapt to negative swings.

Thus, there is a need for an implementation circuit and method capable of measuring bidirectional currents that are integrated in the driver IC while avoiding the need to insert a sensing element into the power circuit. The present invention intends to satisfy this need.

According to the invention, the low side switch in the half / full bridge circuit is dual as the current sensing element. Since the R _DSON of the MOSFET switching element is known and the drain voltage of the switch is the same as VS (common node), the current in the circuit can be confirmed by sensing the VS voltage while the low side switch is in operation. have. The method of current sensing is not completely disturbing and can be fully integrated into the driver IC.

The VS sensing portion of the new circuit is based on the technology disclosed in the above-mentioned Dana Wilhelm patent application. The device of the Dana Wilhelm application is intended to be used for offset sensing, ie to determine when the common node transitions from a high state to a low state or from a low state to a high state. This is required, for example, in electrical ballasts driving resonant loads, in which case the premature turn on of the low side MOSFET causes the voltage at the common node to Will lead to voltage. This so-called "hard-switching" is a source of switching losses, and generates heat in MOSFETS M _HS and M _LS , ultimately leading to the MOSFETS failure.

It is now recognized that the concepts of the Wilhelm device may also be suitable for current sensing. In addition, by shifting the voltage at the MOSFET node 14 VS voltage to a fixed total amount before being sent to the low side of the sense circuit, sensing of negative current is enabled and bi-directional current is sensed.

Accordingly, it is an object of the present invention to provide an improved apparatus and method for sensing current in a high power MOSFET switch output circuit.

It is a further object to provide an apparatus and method in which the voltage of the common node between two switching transistors in a totem pole configuration is used to determine the current on the bias of R _DSON of the low side transistor.

A further object is to provide an apparatus and method for shifting the voltage at a common node by a predetermined total amount for sensing negative currents.

Another object of the present invention is to provide a current sensing arrangement that does not require the insertion of a sensing element in the output current path.

It is another object of the present invention to provide a current sensing arrangement that can be combined with other components of the driver for the switching transistors in a single integrated circuit.

It is another object of the present invention to provide a current sensing arrangement that can be used in devices having both half bridge and full bridge topologies as described above.

According to one aspect of the present invention, there is provided two arraying transistors connected in a totem pole configuration, providing an arrangement for sensing current in a high power MOSFET switch output circuit, wherein the voltage at a common node between the transistors is It is sensed by a circuit connected to the node, and the voltage is used to calculate the current on the bias of R _DSON of the low side transistor.

According to another aspect of the present invention, the above arrangement is integrated with other components of the driver for the output transistors.

According to another aspect of the present invention, the voltage at the common node between the transistors is shifted by a fixed total amount to measure positive and negative currents through R _DSON of the low side transistor.

The precise nature of the invention will become apparent from the description of the invention in conjunction with the accompanying drawings, as well as other objects, features and advantages, and like parts are designated by like reference numerals.

1 is a diagram of a simplified half bridge circuit to which the present invention may be applied.

2 is a schematic diagram of a new current sensing circuit, in accordance with the present invention.

3 is a block diagram illustrating signal processing for bidirectional overcurrent sensing.

4 is a diagram of the waveform of the circuit of FIG.

Figure 5 shows the relationship between the particular volts in the circuit of Figure 2 above.

Referring again to FIG. 1, the application of the present principles in the illustrated circuit arrangement includes sensing circuitry within IC 18, and common node 14 at the appropriate pin of the IC as indicated by the broken line. Requires to be connected.

A circuit for carrying out the arrangement according to the invention is illustrated in FIG. The circuit, generally designated 30, consists of two parts: The current reference / mirror circuit comprising MOSFETS M2-M5 includes a level shifting resistor R1 in the high side well, and MOSFETS M6-. Match the circuits on the low side including M9 (except for the level shift resistor). The two sides are linked with a high voltage NMOS M1. This is operated to pass along the VS voltage when the high side well is close to ground as described in connection with FIG.

The operation of the circuit is as follows: VS is shifted by a constant amount Iref1 x M3 / M2 x R1 so that the shifted voltage V1 = VS + Iref1 x M3 / M2 x R1 is always positive. If the current reference and current mirrors on the high side match their counterparts on the low side, i.e., Iref1 = Iref2, M3 / M2 = M7 / M6 and M5 / M4 = M9 / M8, then V3 = V1, and V4 is different from V3 / V _DSON of NMOS M1, which is very small. However, the relationship described above applies when V1 is only positive. When V1 is negative, V3 is not equal to V1. Instead V2 is lower, and M5 is pinched off to prevent the body diode of M1 from driving and to prevent M1 from destructively latching up.

The final result is V4 (Vsense) = VS + Iref1 × M3 / M2 × R1-V _DSON , M1

                       ~ VS + Iref1 × M3 / M2 × R1.

Since VS is equal to the product of the low side switch and R _DSON of the low side current, the illustrated circuit can be driven more easily.

3 illustrates the practical use of the concepts described above. Here, the low side logic input L _IN is a low side delay circuit 52, pre-driver circuit 54, output to provide a gate drive signal L ₀ for the low side MOSFET switch M _LS (see FIG. 1). Connections are made via a driver 56 (all three forms, as appropriate and required). The low side delay is used to provide a suitable dead time between the _turning off of the high side switch M _{HS and} the turning on of the low side switch M _LS .

As indicated by the waveform of V4 shown in FIG. 4, after the low side switch M _LS is turned on at any time, in order to defend against external noise and to prevent unwanted shoot through M1, current sensing This is desirable to work. For this purpose, the output of the pre-driver 54 is to provide a delayed version of the low side gate drive signal L _IN , such as an enable signal for NMOS M1 (see FIG. 2). Connected via a leading edge chop filter 58, a NAND gate 60 and an inverter 62. A second input to NAND gate 60 is provided as a non-delayed version of the low side logic input signal L _IN .

The V4 sense signal is also used to provide an overcurrent sensing function. For this purpose, the V4 signal is coupled to the direct and inverting inputs of comparators 66 and 72, respectively. Second inputs to the comparators 66 and 72 are provided with plus and minus reference signals + V and -V, respectively, indicating positive and negative values above the threshold current. The output of the inverter 60 is connected via a leading edge fin filter 68 as one input to the NOR gate 70 and is provided directly from the second input inverter 72 of the NOR gate.

The output of the gate 70 is provided as an input to the NOR gate 64 together with the output of the NAND gate 60.

The output of the NOR gate 64 provides an overcurrent indication signal.

For accurate current (VS) sensing, the current I1 in M1 needs to be small enough so that the V _DSON of M1 and M5 can be ignored (see FIG. 5). This is balanced by requiring the current to be large enough to limit the transients at V4. These transients are caused by capacitive coupling from the gate of M1 and can be seen as false peaks of V4 when M1 is operating. The transients can be prevented by using a low pass filter after V4 or by placing a leading edge 촙 filter after V4 is compared to the overcurrent threshold voltage. Larger I1 will add parasitic capacitance at V4 faster, allow faster filters to be used, and improve response time.

As will be appreciated, in order to sense large negative currents, Iref1 and R1 must be appropriately selected to ensure that VS + Iref1 x M3 / M2 x R1 is always positive. Also for reliable current sensing under all conditions, Iref1 and R1 should be chosen so that they are not essentially affected by changes in power supply and temperature. Moreover, the robustness of the circuit can be improved by using zener diodes ZD1 and ZD2 to limit high voltage transients at the source and drain of M1.

Although the present invention has been described herein in connection with specific embodiments, many other variations, modifications and other uses will be apparent to those skilled in the art. Therefore, it is intended that the present invention not be limited by the specific disclosure herein, but rather be given a thorough scope, which is recognized in accordance with the appended claims.

Claims (18)

As a gate driver for a bridged connected switching transistor output circuit comprising a high side and a low side transistor switch: A first input for receiving a high side switch enable signal; A second input for receiving a low side switch enable signal; A third input coupled to the common node between the high and low side switches; A first output for providing a gate drive signal to the high side switch; A second output for providing a gate drive signal to the low side switch; A third output for providing an output signal indicative of the output current via the high and low side switches; An offset circuit electrically coupled with the third circuit including a reference current source, a level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration; A measurement circuit electrically coupled with the offset circuit comprising a second current reference source having an electrical characteristic essentially the same as the first current reference source, and a second plurality of transistors each being coupled to the input side circuit transistors. Match the same circuit configuration; A coupling element for coupling said offset circuit with said measurement circuit in response to a gating signal, wherein: The offset circuit is operative to offset a voltage signal at the first input terminal in a predetermined manner and to pass the offset signal to the coupling circuit; The coupling element is responsive to the gate signal through which the offset signal passes through the measurement circuitry; The measuring circuit is operative to generate the measuring signal. The gate driver of claim 1, wherein the offset circuit, the coupling circuit, and the measurement circuit are integrated into an integrated circuit. The gate driver of claim 1, wherein the output current is not affected by the connection of the offset circuit and the common node. 2. The gate driver of claim 1, wherein the transistors in the offset circuit and the measurement circuit are MOSFETs and the coupling element is an NMOS high voltage transistor. 2. The gate driver of claim 1, wherein the gating signal is generated from a delayed version of the signal at a first input. 6. The gate driver of claim 5, wherein the signal is generated by passing the signal at the first input through a leading edge 촙 filter. 2. The gate driver of claim 1, wherein the measurement circuit comprises a comparator arrangement for comparing the offset path and the output side circuit by the coupling element associated with indicating an overcurrent limit. 8. The gate driver of claim 7, further comprising a filter circuit coupled between the comparator arrangement and the coupling circuit. 9. The gate driver of claim 8, wherein the filter circuit comprises a leading edge shock filter. 8. The apparatus of claim 7, wherein the comparator arrangement is: A first comparator circuit for comparing said offset signal having a positive overcurrent limiting signal; A second comparator circuit for comparing the offset signal having a negative overcurrent limiting signal; And where: The first comparator is coupled to the output circuit through a filter circuit; And said second comparator is coupled directly to said output circuit. The method of claim 1 wherein the offset signal is obtained by adding the voltage to a voltage fixed at the third input. Generating a gate driver. A method for determining the output current in a bridged switch transistor output circuit comprising high side and low side transistor switches, the method comprising: Determining the voltage at a common node between the high and low side switches without using any element that changes the output current because of the determination; Electrically coupling a signal indicative of the voltage at the common node through a first circuit that increases the signal with positive sensing, in accordance with a predetermined relationship of generating an offset voltage signal; Electrically coupling the offset voltage signal through a second signal circuit to obtain a measurement signal indicative of the output current. 14. The switch of claim 13, wherein the fixed voltage comprises high side and low side transistor switches that add the signal representing the voltage at the common node to generate the offset signal. A method for determining the output current in a transistor output circuit. 13. The high side of claim 12, wherein the voltage of the signal at the common node is offset by a sufficient amount such that the resulting offset signal is positive for bidirectional currents of all required magnitudes. A method for determining said output current in a switch transistor output circuit comprising low side transistor switches, wherein a bridge is connected. 13. The method of claim 12, wherein the high and low side switches are turned on and off by disadvantaged gating signals, and the offset signal is coupled with the second circuit only during a portion of the low side switch being turned on. A method for determining said output current in a switch transistor output circuit comprising high side and low side transistor switches, wherein a bridge is connected. 16. The device of claim 15, further comprising preventing the offset signal from coupling with the second circuit if its value is negative. Method for determining the output current in a switch transistor output circuit. 13. The high side of claim 12 further comprising comparing the offset signal having a reference signal and providing an output signal when the offset signal indicates an overcurrent threshold for the output circuit. A method for determining said output current in a switch transistor output circuit comprising low side transistor switches, wherein a bridge is connected. 13. The method of claim 12, further comprising comparing the offset circuit having a positive reference signal and a negative reference signal and providing an indication when the offset signal indicates a positive or negative overcurrent threshold for the output circuit. Further comprising a high side and a low side transistor switches, the method of determining the output current in a switch transistor output circuit to which a bridge is connected.

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