KR20070032308A - Power amplifier and pulse width modulated amplifier - Google Patents

Abstract

The present invention relates to a power amplifier having a phase amplification path having a phase amplification stage in the phase amplification path. Here, the phase amplification stage receives the magnitude component of the power amplified output signal, and to generate the power amplified output signal, the phase amplification stage is a phase component of the input signal, the magnitude component of the input signal and the power amplified output. Responsive to the received magnitude component of the signal. The invention also relates to a power amplifier having a magnitude amplification path for the magnitude component of the input signal. The magnitude amplification path has a magnitude amplifier stage. The invention also relates to a power amplifier having a phase amplification path with a phase amplification stage in the phase amplification path.

Power amplifier, phase amplification, magnitude amplification, pulse width modulation

Description

POWER AMPLIFIER AND PULSE WIDTH MODULATED AMPLIFIER}

The present invention relates to power amplifiers. More particularly, the present invention relates to an amplifier having a phase amplification path. The invention also relates to an amplifier having a magnitude amplification path and a phase amplification path. The invention further relates to a pulse width modulated amplifier.

The efficiency of an RF power amplifier has a significant impact on the battery life of a portable device, such as a portable transmitter, for example, because the amplifier consumes most of the power used by the device.

In the case of base station power amplifiers, the power consumption is even greater, generating heat that also reduces reliability, which may require active cooling, which also increases power consumption even further.

Therefore, efficient power amplifiers are very desirable for power transmitters. Efficient C, D, E and F power amplifiers can only produce constant-amplitude outputs. However, many recent transmitter designs require a non-constant amplitude RF output to maximize the data rate within a given channel bandwidth.

In the design of traditional linear power amplifiers, it is common to involve a trade-off between efficiency and linearity. Polar modulatiion is known in the art as a technique for simultaneously obtaining linearity and efficiency in an RF power amplifier. Polarity modulation is also known as envelope elimination and restoration (EER). In this approach, the RF input signal is decomposed into polar components, namely phase and magnitude. These two polar components are each amplified and then recombined to produce an amplified, linear RF output signal. The phase component of the RF input signal is typically amplified by a constant-amplitude amplifier optimized for efficiency. The magnitude element (or envelope element) of the RF input signal is typically amplified by a switching mode power supply that acts as a power supply for at least one output stage having a constant amplitude.

Various approaches using polarization are described by L. Kahn in Proc. IRE, pp803-806, "Single-Sided Transmission by Envelope Elimination and Restoration," and also on May 3, 1989 by M. Koch and M. Fisher, "A High-Frequency 835MHZ Linear Power Amplifier for Digital." Cellular Telephony "39th IEEE Vehicular Technology Conference.

1 is a block diagram of a traditional RF amplifier 10, employing the above-described envelope elimination and recovery techniques. In the amplifier shown in FIG. 1, the RF input signal 12 is first decomposed into polar elements. These polar components consist of a phase that is a constant amplitude signal and a magnitude that is a low frequency envelope signal. The phase and magnitude elements are each independently amplified along separate paths 15 and 11. The phase and magnitude components are then recombined to produce a linearly amplified RF output signal 19.

The phase component is extracted from the input signal by the limiter 16 and amplified by an efficient constant amplitude amplifier which may comprise a nonlinear preamplifier 17 and an efficient nonlinear output stage 18. . The magnitude factor with a bandwidth comparable to the channel bandwidth is extracted from the input signal by the envelope detector 13 and amplified by a linear baseband amplifier 14. To maximize efficiency, the linear baseband amplifier 14 is implemented using a switched mode power supply having a class D amplifier as the output stage.

Techniques for implementing a switched mode power supply using pulse width modulation are known. The output of such a power supply is a square wave whose mark / space ratio represents the magnitude component of the RF input signal. However, using pulse width modulation to amplify the magnitude factor may result in inter-modulation distortion in the RF output.

It is known in the art to apply a negative feedback path based on the filtered output signal to reduce distortion during modulation in a class-D amplifier using pulse width modulation. However, public number no. A U.S. patent application with 2002/0070799 A1 discloses a pulse width modulated digital amplifier, which discloses a PWM modulator for driving a high power switch with a low pass filter that filters the output of the power switch. Here, the digital amplifier has a feedback control loop having a feedback signal provided directly from the output of the high power switch as an analog input signal. Both the analog input signal and the feedback signal are provided to the inverting input of the integrator, and the inverting input of the integrator is grounded, whereby the feedback signal acts directly on the analog input signal.

US 5,973,556 discloses a delta modulated RF power supply having a magnitude amplification path and a phase amplification path. Delta modulation amplifiers are used to amplify the magnitude components of RF power amplifiers with envelope rejection and reconstruction. The magnitude amplification path includes a feedback path from the RF output signal, but there is no feedback path in the phase amplification path.

U. S. Patent No. 5,675, 288 discloses a circuit for linearizing a non-linear amplifier having a magnitude amplification path and a phase amplification path. The magnitude amplification path includes a feedback path from the output signal, and the phase amplification path also includes a feedback path from the output signal. The feedback path of the phase amplification path includes a phase comparator, where the phase of the feedback signal is compared with the phase of the input signal. Here, the magnitude factor or phase factor of the output signal is not used in the phase amplification path.

According to a first aspect of the present invention, there is provided a power amplifier for generating a power amplified output signal from an input signal, the power amplifier comprising: a phase amplification path and a phase amplification stage in the phase amplification path; The phase amplification stage receives a magnitude component of the power amplified output signal; To generate the power amplified output signal, the phase amplification stage comprises responsive to a phase component of an input signal, a magnitude component of the input signal, and a received magnitude component of the power amplified output signal.

According to a second aspect of the invention, there is provided a power amplifier for generating a power amplified output signal from an input signal, the power amplifier comprising: a magnitude amplification path for a magnitude component of the input signal; A magnitude amplification stage in the magnitude amplification path; Phase amplification paths; And a phase amplification stage in the phase amplification path. Here, the phase amplification stage receives the magnitude component of the power amplified output signal and the amplified magnitude component of the input signal from the magnitude amplification stage. The phase amplification stage comprises a phase component of an input signal, a magnitude component of an input signal, a received magnitude component of a power amplified output signal and the received amplified magnitude component of an input signal to produce the power amplified output signal. Answer.

In the first and second aspects of the invention, it should be understood that the magnitude factor of the power amplified output signal received by the phase amplification stage may be a magnitude factor corresponding to the power amplified output signal. Thus, if the output signal of the power amplifier is filtered, the magnitude factor may correspond to an unfiltered output signal or may correspond to a filtered output signal.

According to the first and second aspects of the invention, the power amplified signal produced by the phase amplification stage is substantially and linearly related to the input signal in phase and magnitude.

According to the first and second aspects of the invention, the phase amplification stage is adapted to produce an output that depends on the difference between the received magnitude component of the power amplified output signal and the received magnitude component of the input signal. It is preferable to include a detector (difference detector). Here, the phase amplification path preferably comprises a magnitude feedback path, which combines a signal corresponding to a power amplified output signal or a power amplified output signal with the difference detector as a magnitude factor of the power amplified output signal. To do this. The magnitude feedback path of the phase amplification path may comprise an output envelope detector to detect the magnitude component of the power amplified output signal. The magnitude feedback path of the phase amplification path may also comprise an attenuator for reducing the amplitude of the magnitude component of the power amplified output signal.

According to the first and second aspects of the invention, the power amplifier further comprises an input envelope detector for detecting a first input magnitude element of the input signal and combining the first input magnitude element of the input signal into a phase amplification stage. It may be made, including. Here, the first input magnitude element may be coupled to the difference detector of the phase amplification stage as a received magnitude element of the input signal.

According to the first and second aspects of the invention, the phase amplification stage preferably comprises an amplitude-phase converter for converting the output of the difference detector into a phase difference signal.

In embodiments according to the first and second aspects of the present invention, the phase amplification stage may further receive a phase component of the power amplified output signal, the phase amplification stage to generate a power amplified output signal. It may also be responsive to the received phase component of the power amplified output signal. The phase amplification stage comprises a mixer, a multiplier or a phase discriminator to generate an output signal that depends on the phase component of the input signal and the received phase component of the power amplified output signal. It can also be done. The phase amplification stage preferably comprises a phase feedback path to couple the power amplified output signal to a phase discriminator. The phase feedback path may comprise a limiter to generate a phase component of the power amplified output signal. The phase feedback path may also include an attenuator for reducing the power amplified output signal. The phase amplification stage preferably includes a phase shifter for generating the first phase shifted signal by shifting the phase of the input phase element as a function of the signal output from the phase discriminator.

In embodiments according to the first and second aspects of the invention, the phase amplification stage preferably comprises a limiter for generating a phase element of the input signal.

In embodiments according to the first and second aspects of the invention having a difference detector for generating a difference signal from received magnitude elements, the phase amplification stage is output from a phase or difference detector of an input phase element. And a phase shifter for shifting the phase of the first phase shifted signal as a function of the signal. When the phase amplification stage comprises an amplitude-phase converter for converting the output of the difference detector into a phase difference signal, the input phase element or the first phase shifted signal may be shifted by the generated phase difference signal. It may be. The phase shifter shifts the phase of the input phase element or shifts the phase of the first phase shifted signal as a function of the signal output from the difference detector or by a phase difference signal generated by an amplitude-phase converter. And may include a first phase shifter for shifting, wherein the phase shifter shifts or generates a phase of the first phase shifted signal as a function of shifting a phase of an input phase element or an inverse function of a signal output from a difference detector. It may further include a second phase shifter which is shifted by the inverse of the phase difference signal. Therefore, the phase shift obtained by the second phase shifter is substantially inverse or opposite to the phase shift obtained by the first phase shifter. The first and second phase shifters are first and second multipliers / mixers for shifting a phase of an input phase element or a phase of a first phase shifted signal by a phase difference signal and an inverse of the phase difference signal, respectively. It may be.

In embodiments with first and second phase shifters, the phase amplification stage preferably comprises first and second phase amplifiers that amplify the output signals of the first and second phase shifters, respectively. Further, in the embodiments according to the first and second aspects of the present invention, the phase amplification stage includes first and second phase limiters for respectively limiting output signals of the first and second phase shifters. The outputs of the first and second phase limiters may be input to the first and second phase amplifiers, respectively. The first and second phase amplifiers may be class F or class E amplifiers. If the class F amplifier, the first and second phase amplifiers may be switch mode amplifiers.

The phase amplification stage may include a summer or a power mixer that adds or mixes the outputs of the first and second phase amplifiers to produce a power amplified output signal. The phase amplification stage also preferably includes a filter for filtering the output of the summer or power mixer to obtain a power amplified output signal. It should be noted that, within the scope of the inventive concept, the input signal of the filter may be used or the output signal of the filter may be used to generate the magnitude factor of the power amplified output signal.

In embodiments according to the second aspect of the invention, the first and second phase amplifiers are preferably coupled to the output of the magnitude amplifier, where the gain of the phase amplifier is regulated or modified by the magnitude amplifier. (modify)

In embodiments according to the second aspect of the invention, the magnitude amplification path preferably comprises an input envelope detector for detecting an input magnitude element of the input signal and coupling the input magnitude element to a magnitude amplifier. Here, the input envelope detector for detecting a first input magnitude element may be part of a magnitude amplification path, wherein the first input magnitude element is coupled to the magnitude amplifier.

In embodiments according to the second aspect of the invention, the magnitude amplifier stage preferably comprises a class D amplifier. Also, the magnitude amplifier stage preferably includes a pulse width modulated amplifier. The magnitude amplifier stage may also include a low pass filter, where the output delivered by the magnitude amplifier stage is a low pass filtered signal.

In an alternative embodiment according to the second aspect of the invention, the phase amplification stage may comprise a nonlinear amplifier for amplifying the output of the phase shifter, which is connected to the output of the magnitude amplifier, thereby The gain of the nonlinear amplifier is adjusted or modified by the magnitude amplifier so that the nonlinear amplifier produces a power amplified output signal. The nonlinear amplifier may include third and fourth multipliers / mixers that mix the output of the magnitude amplifier with the outputs of the first and second multipliers / mixers, respectively, wherein the third and fourth multipliers / mixers It may further include a power mixer for mixing the outputs. The nonlinear amplifier preferably includes a filter for filtering the output of the power mixer to obtain a power amplified output signal.

According to a third aspect of the present invention, there is provided a pulse width modulated amplifier, comprising: a difference detector or amplifier for generating one or more outputs dependent upon a difference between an input signal and a feedback signal; A pulse width modulator coupled to the difference detector to generate a pulse width modulated signal as an output; A power switch circuit for amplifying the output of the PWM modulator; And a feedback path coupling the one or more outputs of the power switch circuit to the difference detector as a feedback signal.

According to a third aspect of the invention, the pulse width modulated amplifier preferably further comprises a low pass filtering circuit coupled to the output (s) of the power switch circuit. It should be noted here that the output (s) of the power switch circuit may be coupled to both the feedback path and the low pass filter.

According to a third aspect of the invention, the feedback path preferably comprises an attenuator for reducing the amplitude of the feedback signal to the difference detector. In addition, the power switch circuit preferably includes a pull-up switch having a pull-up output and a pull-down switch having a pull-down output. Here, the power switch circuit is such that the pull-up switch is open and the pull-down switch is shorted when the power switch circuit is ON, and the pull-up switch is shorted and the pull-down switch is opened when the power switch circuit is OFF. May be controlled by the output of a PWM modulator. The feedback path preferably includes an adder for combining the pull-up output and the pull-down output to produce one feedback signal. Here, the output of the summer may be supplied to the attenuator or may be supplied to the difference amplifier through the attenuator.

In embodiments according to the third aspect of the invention having a low pass filter, the low pass filter comprises a first inductor having a first terminal coupled to a pull-up output and a first inductor coupled to a pull-down output. It is preferred to include two inductors. Here, the second terminal of the first inductor and the second terminal of the second inductor may both be connected to the same terminal of the output capacitor so as to carry the output signal of the pulse width modulated amplifier.

In an embodiment according to the third aspect of the invention, the PWM modulator may comprise a ring oscillator, the ring oscillator comprising an inverting amplifier and first and second phase shifters, The phase shift of the first and second phase shifters is controlled in response to the output (s) of the differential amplifier. Here, the difference amplifier has two difference outputs, and there is a signal difference between the two difference outputs indicating that the difference between the input signal and the received feedback signal is amplified. The first phase shifter may be controlled in response to the first difference output, and the second phase shifter may be controlled in response to the second difference output. The first phase output from the first phase shifter and the second phase output from the second phase shifter are preferably coupled to produce an output of the PWM modulator, the output of the PWM modulator being coupled to a power switch circuit. Is received by. Wherein the first and second phase outputs may be multiplied together to produce an output of a PWM modulator. Preferably, this multiplication is performed using an exclusive OR function.

According to an embodiment according to the third aspect of the invention, the pulse width modulated amplifier may further comprise one or more filters for filtering the output (s) of the difference amplifier, wherein the filtered outputs of the difference amplifier are PWM modulators. Are combined as inputs. In an embodiment according to the third aspect of the invention, the power switch circuit comprises at least two MOSFET switch transistors. It is the scope of the present invention that the pulse width modulated amplifier according to any embodiments pertaining to the third aspect of the invention may also be used as a magnitude amplifier in the magnitude amplification path of the power amplifier according to the second aspect of the invention. Note that it belongs to.

Other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the present invention with respect to the preferred embodiments which will be described below in conjunction with the accompanying drawings.

1 shows a block diagram of a conventional RF amplifier employing envelope removal and restoration.

2 shows a simplified block diagram of a power amplifier according to an embodiment of the present invention having a magnitude amplification path and a phase amplification path.

3 is a more detailed block diagram of a power amplifier according to an embodiment of the present invention, corresponding to FIG.

4 is a detailed diagram of a phase amplification stage according to an embodiment of the present invention corresponding to the phase amplification path of the power amplifier shown in FIG.

Figure 5 shows a detailed diagram of an example of a pulse width modulated amplifier according to the present invention.

Figure 6 is a block diagram of a power amplifier with a phase amplification path that includes a magnitude feedback path for the magnitude or amplitude component of the power amplifier output signal in accordance with one embodiment of the present invention.

7A and 7B are block diagrams illustrating embodiments of a power amplifier having a phase amplification path including feedback paths for both phase and amplitude or amplitude components of the power amplifier output signal, in accordance with an embodiment of the invention. It is a diagram.

FIG. 8 shows a first embodiment of a phase amplification stage with a summer output, which may be used in conjunction with the power amplifiers of FIGS. 6, 7A and 7B.

FIG. 9 shows a second embodiment of a phase amplification stage with a summer output, which may be used in conjunction with the power amplifiers of FIGS. 6, 7A and 7B.

According to a second aspect of the present invention, there is provided an efficient and very linear power amplifier that may be used as an efficient RF power amplifier, which is related to Figure 1, which is a block diagram of a traditional RF amplifier employing envelope cancellation and restoration. It is based in part on the polarity modulation concept described above.

A preferred embodiment according to the second aspect of the invention is shown in FIG. 2, which shows a simplified block diagram of a power amplifier 200 having a magnitude amplification path 201 and a phase amplification path 202. FIG. Is shown. The magnitude amplification path 201 includes an envelope detector 204 and a magnitude amplification stage 205, with the input signal 203 connected to the envelope detector 204, which envelope element draws magnitude components from the input signal. Extraction and the magnitude component is fed to the magnitude amplification stage 205. In a preferred embodiment, the magnitude amplification stage 205 may comprise a class D amplifier.

The phase amplification path 202 includes a magnitude feedback path 207 with a phase amplification stage 206 and an envelope detector 208, which envelope element size of the power amplified output signal 210. The magnitude factor of the output signal 210 is extracted and supplied to the phase amplification stage 206. The input signal 203 is supplied to the phase amplification stage 206, where the phase component of the input signal 203 is extracted. Phase amplification stage 206 also has an extracted magnitude element 209 of input signal 203 as input. Here, the extracted magnitude element 209 of the input signal 203 may be extracted by a separate envelope detector, but is preferably extracted by the envelope detector 204. In addition, the output of the magnitude amplification stage 205 is connected to the power input terminal 211 of the phase amplification stage 206. Phase amplification stage 206 may comprise a high efficiency non-linear phase output stage, which may be in the form of a class C output stage, a class D output stage, a class E output stage or a class F output stage. . In a preferred embodiment, the phase amplification stage 206 includes an E class amplifier.

According to a preferred embodiment of the present invention, it should be noted that the input signal 203 is an RF input signal.

3 shows a detailed block diagram of an example of a power amplifier according to the present invention corresponding to the simplified block diagram of FIG. The power amplifier 300 of FIG. 3 has a magnitude amplification path 301 similar to the magnitude amplification path shown in FIG. 2, and includes an envelope detector 304 and a magnitude amplification stage 305, which are RF signals. An input signal 303 is coupled to the envelope detector 304, which supplies the magnitude component of the RF input signal to the magnitude amplification stage 305.

The power amplifier 300 also includes a phase amplification path including a magnitude feedback path 307 having a phase amplification stage 306 and an envelope detector 308 for extracting the magnitude components of the power amplified RF output signal 310. Has 302

The magnitude feedback path 307 also has an attenuator 312 that reduces the amplitude of the output of the envelope detector 308. In FIG. 3, the attenuator 312 is configured after the envelope detector 308, but the attenuator 312 may also be configured in front of the envelope detector 308. Phase amplification stage 306 comprises a limiter 313 for generating a phase element of the RF input signal 303. A phase element may be extracted from the input signal 303 by limiting the RF input signal, i.e., clipping to remove the magnitude element. The output of the limiter 313 is a constant envelope signal having a phase that changes in accordance with the phase of the RF input signal. In addition, the phase amplification stage 306 comprises a difference detector 314. The difference detector 314 receives the output 309 of the envelope detector 304 as an input signal and receives the output of the attenuator 312 representing the reduced magnitude component of the RF output signal 310 as an input signal. An output of the difference detector 314 indicative of the difference between the received magnitude factor signals is provided to an amplitude-phase converter 315 that converts the received magnitude difference signal into a phase signal. The phase output of the transducer 315 is supplied to the phase shifters 316 and 317, which further input as input the phase component of the RF input signal output from the limiter 313. Receive. The output signal of phase shifter 316 is shifted in phase by the phase output of transducer 315, while the output signal of phase shifter 317 is inversed by the phase output of transducer 315. Deviation in phase.

Phase amplification stage 306 further comprises a non-linear amplifier 318 with first and second multipliers / mixers 319, 320, a power mixer 321, and a filter 322. The first multiplier 319 has an output from the phase shifter 316 as an input, and the power input terminal of the multiplier 319 is supplied from the output of the magnitude amplification stage 305. Similarly, second multiplier 320 has an output from phase shifter 317 as input, and the power input terminal of multiplier 320 is also supplied from the output of magnitude amplification stage 305. The outputs of the multipliers 319 and 320 are summed together by the power mixer 321, the output of the mixer 321 is filtered by the filter 322, the filter 322 is a power amplified RF output signal ( 310).

4 is a detailed diagram of an example of a phase amplification stage 406 according to the present invention corresponding to the phase amplification stage 306 of the power amplifier shown in FIG. In Fig. 4, the RF input signal is supplied to the limiter 413, and the output of the limiter is supplied to the phase shifters 416 and 417. The output of the envelope detector 304 and the output of the attenuator 312 are fed to the difference detector 414.

The difference detector 414 has two outputs 414a, 414b that are input to an amplitude-phase transducer corresponding to the transducer 315 of FIG. In Fig. 4, the converter comprises two D-type flip flops 415a and 415b having as inputs square wave signals CP + and CP- which are square wave signals of the RF input signal. The outputs of the flip flops 415a and 415b are multiplied together by an OR gate 415c which in turn controls the switch 415d that switches the outputs 414a and 414b of the difference detector 414, thereby being detected. Phase difference outputs are obtained that correspond to amplitude differences. The switched difference detector outputs are fed to filter 415e, the filtered positive phase difference output is fed to phase shifter 416, and the filtered negative phase difference output is phase shifted (417). Is supplied.

The output of the phase shifter 416 is supplied to the limiter 419a which is part of the multiplier 319, and the output of the limiter 419a is supplied to the gate of the first NMOS transistor 419b, which is the first NMOS. Transistor 419b forms a power part of multiplier 319, the source of first NMOS transistor 419b being grounded and the drain output of magnitude amplifying stage 305 through inductor 421a. It is coupled to the power input. In the same way, the output of the phase shifter 417 is supplied to the limiter 420a which is part of the multiplier 320, and the output of the limiter 420a is supplied to the gate of the second NMOS transistor 420b. The second NMOS transistor 420b forms a power part of the multiplier 320, the source of the second NMOS transistor 420b is grounded and the drain is magnitude amplified by an inductor 421a. 305 is coupled to the power input.

The power mixer of FIG. 4, corresponding to the power mixer 321 of FIG. 3, is obtained by coupling the drains of the NMOS transistors 419b, 420b together to the inductor 421a, and outputs the output signal of the magnitude amplification stage 305. Have as input. The inductor 421a forms a part of a transformer and has an inductor 422a on the other side of the transformer. The output of the transformer is coupled to inductor 422b, which is part of a filter corresponding to filter 322 of FIG. 3, which also includes capacitor 422c. The output of the filter is a power amplified RF output signal 430.

According to a third aspect of the invention there is provided a pulse width modulated amplifier, which may provide a solution to the magnitude amplification stage of a power amplifier according to the second aspect of the invention discussed above. An embodiment of a pulse width modulated amplifier according to a third aspect of the present invention is shown in FIG. In Figure 5, an input signal 501, which may be a magnitude element of the RF input signal, is supplied to a difference detector or amplifier 502, which has a feedback signal 503 as a second input. The difference detector 502 has two outputs filtered by the low pass filter circuit 504, the two filtered difference outputs being coupled to the first phase shifter 505 and the second phase shifter 506. The first and second phase shifters are part of the PWM modulator 507.

The PWM modulator 507 or generator has phase shifters 505, 506 arranged in series such that the output of the first phase shifter 505 is provided to the input of the second phase shifter 506. The output of the two phase shifter 506 is provided to the input of the inverting amplifier 508, and the output of the inverter 508 is provided to the input of the first phase shifter 505. Thus, the phase shift provided by the phase shifters 505, 506 is controlled by the outputs of the difference detector 502. R1, the output of the first phase shifter 505, and R2, the output of the second phase shifter 506, are multiplied together by a multiplication circuit or an exclusive OR function 509, producing P1, the output of the PWM modulator. .

P1, the output of the PWM modulator, is used as a control input to the power switch circuit 510. The power switch circuit 510 may be implemented using CMOS technology, and the power switch circuit 510 illustrated in FIG. 5 may include a PMOS transistor 511 having a source connected to a positive supply power and an NMOS transistor having a source grounded. 512). Gates of transistors 511 and 512 are controlled by output P1. A first output of the power switch circuit 510 is provided at the DP terminal, which is the drain of the PMOS transistor 511, and a second output of the power switch circuit 510 is provided at the DN terminal, which is the drain of the NMOS transistor 512. When the PMOS transistor 511 is in the ON state, the NMOS transistor 512 is in the OFF state and the output at the DP terminal is pulled up by the supply power supply. When the NMOS transistor 512 is in the ON state, the PMOS transistor 511 is in the OFF state and the output at the DN terminal is pulled down to ground. The power switch outputs at the DP and DN terminals are summed together by a summer circuit 513, and the output of the summer circuit is supplied to the attenuator 514. The output of the attenuator provides a feedback signal 503 which is passed to the difference detector 502.

In one embodiment for the PWM modulated amplifier shown in FIG. 5, the outputs at the DP and DN terminals of the power switch circuit 510 are also coupled to the low pass filter 515, which is the filtered output of the amplifier. To get (519). Here, the filter 515 includes a first inductor 516 whose first terminal is connected to the DP terminal and a second inductor 517 whose first terminal is connected to the DN terminal. The second terminal of the inductors 516, 517 is connected together to the output terminal of the output capacitor 518.

6 is a block diagram of a power amplifier according to a first aspect of the present invention, in which a power amplifier having a phase amplification path including magnitude feedback paths for magnitude or amplitude components of the power amplifier output signal is shown.

The structure shown in the block diagram of FIG. 6 may be referred to as coherent amplitude linearization feedback. In Fig. 6, the input signal S _i (t), which may be an RF input signal, is amplified to A _v S _i (t) using the principle according to the first aspect of the invention.

The phase of the input signal is extracted by limiting the signal _Si (t) using the limiter block A _i .

In equation (2), if x> 0, then ∏ (x) = 1, ∏ (x) = -1 for all other x values.

The phase of the signal is shifted by the use of two phase shifters P _{F +} and P _F− .

In equation (3), φ _c = φ _K A _c (t).

Signals P _{P +} and P _P- are fed to amplifier blocks A _{F +} and A _F- via limiting blocks L _{F +} and L _F- , respectively, and the amplified signals P _{F +} and P _F- are joined together in summer block S _F. Is added or summed to provide a signal S _F (t). The signal S _F (t) is supplied through a filter to provide an output signal S _O (t). The signal S _O (t) may be given as a fundamental harmonic of S _F (t), and may be expressed as follows.

From equation (4), it can be seen that the output signal S _O (t) can be controlled via the signal A _C (t). Here, the signal A _C (t) is an output of the difference detector, and the difference detector has A _o (t), which is a magnitude factor of the input signal S _i (t), and A _F (t), which is a magnitude factor of the output signal. The magnitude component A _o (t) of the input signal S _i (t) can be generated by the mixer block M _i , and the magnitude factor A _F (t) of the output signal is the mixer block M _fb , the limiter A _fb , And attenuator blocks. The feedback input to the attenuator block may be an unfiltered output signal S _F (t) or a filtered output signal S _O (t). Referring to Figure 6, the magnitude feedback path includes an attenuator block, a limiter A _fb and a mixer block M _fb , thus providing a feedback path from the unfiltered output signal S _F (t) to the difference detector. The difference detector supplies the signal A _C (t) with phase shifters (P _{F +} , P _F− ). In Fig. 6, the limiter A _fb and the mixer block M _fb can be considered to perform the envelope detector function.

If the phase shifts in signals P _{P +} and P _P- are not exactly opposite, a magnitude feedback path that delivers the magnitude component of the output signal to the difference detector may cause chirp (phase-error) at the output. . This can be corrected by adding phase feedback. This is illustrated in FIG. 7A, which shows a power amplifier in accordance with the present invention having a phase amplification path comprising a feedback path for both phase and magnitude (or amplitude) elements of the power amplifier output signal. It is.

In FIG. 7A the magnitude feedback path is the same as in FIG. However, a phase feedback path sharing the magnitude feedback path, the attenuator block and the limiter A _fb is provided, and the output of the phase feedback path is P _Fp (t) which is the output signal of the limiter A _fb . Here, the signal P _Fp (t) represents a phase signal extracted from S _F (t) which is an unfiltered output signal. Signal P _Fp (t), the mixer block (or phase discriminator) is supplied to the (M _O), the mixer block (M _O) is a restrictor bar further has as input the output signal of P _P (t) from A _fb Here, the signal P _P (t) represents a phase signal extracted from the input signal S _i (t). The output of the phase discriminator block (M _O) is supplied to the phase section is block P _O, P _O is the phase side is block limiter further has as input a _P P (t) the output signal from the A _i. The phase shifted output signal of the phase shifter block P _O is used as an input signal of the phase shifters P _{F +} , P _F− .

The structure shown in the block diagram of FIG. 7A may be referred to as coherent amplitude and phase linearization feedback.

By using a circuit corresponding to the diagram shown in Fig. 6 or 7A, the magnitude (or amplitude) amplifier which is part of the magnitude amplification part may be omitted.

The structure shown in FIG. 7A may be converted to a heterodyne up converter by inserting the mixer block M _up before the phase shifter block P _O. Such a heterodyne system is shown in Figure 7b. The input signal P _P (t) input to the mixer M _up is up-converted to the signal P _up (t) via the local oscillator signal L (t) and input to the phase shifter P _O. Here, signal L (t) is generated by local oscillator block LO. In Figure 7b, it is in place of _P P (t) that were used in Figure 7a, the up _up P (t) the output signal converter should be noted that the supply to the M _O phase discriminator block.

6, 7A and 7B, it should be understood that the blocks whose names are _denoted M (M _i , M _O , M _fb , M _up ) are multipliers that multiply two input signals. The M block may also be called a mixer. The blocks P _P , P _{F +} , P _F- denoted _P are phase shifters. The output signal of the P block is a signal in which the first input signal is phase shifted. The second input signal of the P block controls the degree of phase shift at the output. The blocks S _F , S _A , called S, are adder or subtractor blocks. The output signal of the S block is given by the sum or difference of the input signals.

6, 7A and 7B, the amplifiers A _{F +} and A _F- controlled by signals P _{P +} and P _P- sum the output signals P _{F +} and P _F- . group, and transmitted to the unit S _F, S _F summer unit delivers the signal S _F (t) to the output filter. The output filter delivers its output to the load Z _L. The limiter blocks L _{F +, F-} are the signals from the L and controls the A _{F +, F-} A amplifier, the amplifier (A _{F +, F-} A) may accept F class amplifier.

8 and 9, phase amplification with a summer output, which may be used to provide the functions of the amplifiers A _{F +} , A _F− and summer S _F of FIGS. 6, 7A, and 7B. Embodiments for the stage are shown. As can be seen from the description of Figures 8 and 9, which will be described below, the signals from the limiter blocks L _{F +} , L _F- have two characteristics that switch between two states of closed and open. It may control the switching devices. The phase amplification stages of Figures 8 and 9 are based on a high efficiency amplification scheme. These structures may achieve high efficiency because they deliver only a fixed power output level.

In one embodiment for the phase amplification stage with a summer shown in Figure 8, the summation and cancellation of the output signal is preferably performed on sinusoidal signals, for example,

Here, S (out) is an output signal, and S1 and S2 are signals transmitted from each class F amplifier.

It can be seen that in equation (5) two sine waves may be added to form one sine wave with an amplitude related to phase φ c. 8 are solutions based on class F amplifiers. As has been known for many years in the art, the class F amplifier operates by matching at least the carrier frequency fc (or also referred to as 1 ^st harmonic of the carrier frequency) or requiring at least a substantial impedance to appear. Even harmonics, for example 2 · fc, 4 · fc, 6 · fc, etc., should exhibit a low impedance or a substantially similar impedance to shorted, while odd harmonics, for example 3 · fc, 5 · fc, 7 · fc, etc. shall exhibit a high impedance or substantially similar impedance to an open circuit. If these conditions are met, the basic Class-F amplifier will deliver a sinusoidal output voltage.

The system of Figure 8 comprises a stub system known as a "harmonic short stub system". Each quarter wave of the "harmonic stub system" exhibits a short or substantially low impedance when viewed from a 'summing signal node' which is a structural node. At 1st harmonic (the carrier frequency),

In the 'signal summing node' viewed in the direction indicated by Z (stubsystem) in FIG. 8, the load () represents complex impedance R + jX, where R is positive and X is between -∞ and + ∞, preferably Is X = 0.

When viewed from the respective switching devices, each switching device will appear short-circuited at even harmonics, 2 · fc, 4 · fc, 6 · fc, etc., while odd harmonics, 3 · fc, It will be appreciated by those skilled in the art that 5 fc, 7 fc and the like will appear as open loads (high impedance). Referring to 805 and 806 of FIG. 8, when using a lambda / 4 length transmission line instead of an RF choke, if a power giving device is substantially low at the frequencies at issue If it has an impedance, the even harmonics will be shorted through these strips. In such a case, even harmonic strip lines in the 'harmonic short stub-system' may not be spared. By shorting all harmonics above fc at the 'signal summing node', the impedance seen from one switching device in these harmonics does not affect the value of R (load) as well as the operation of the other switching device. The first harmonic sinusoidal signals are summed at the first harmonic according to the formula discussed above, producing a sinusoidal signal whose amplitude is given by the phase φ c.

In Fig. 8, the devices corresponding to 801 and 802 are power supplies. They may be constant (ie provide a fixed voltage) or may be variable. These power supplies may be connected to an open-loop arrangement, or may be connected to a closed-loop (feedback) if their variable voltage depends on the output power. In configurations where their voltage changes, the change in voltage may be slow to adapt to the adjustment in power level and may be fast to produce amplitude modulation in the output signal. In the latter case, the voltage level may or may not depend on the resulting output voltage as given by the phase amplifier.

Devices corresponding to reference numerals 803 and 804 are switching devices capable of fast switching between two states, one state of which is a device short-circuited, and the other state of which the device is open, i.e., not conducting. These devices can be MOSFET transistors, or any kind of bipolar, LDMOS / VDMOS, HBT, GaAs, radio-tube, or any kind that can quickly change between substantial short and open impedances. Switching devices. They are switched between the on state and the off state by a control signal from the limiter blocks L _{F +} , L _F− shown in FIGS. 6, 7A and 7B.

Devices corresponding to reference numerals 805 and 806 may be RF blocking devices (eg choke coils), but may be transmission lines having a length of 1/4 of the wavelength found at the transmitted frequency. Can be. As is known, transmission lines are lines of conductive material having lengths close to the wavelength of the frequency used by the transmission line. The wavelength of the signal in the transmission line is indicated as 'lamda'.

A transmission line with a length of lambda / 4 at a given frequency is substantially short-circuited when viewed from the other end of the transmission line, with no load connected at its end (open circuited). It is a state. Similarly, the shorted state of one end will be seen as a substantially open-circuited load when viewed from the other end. The relationship between the wavelength and the frequency is as follows.

The second harmonic will have half the size of the first harmonic size, the third harmonic will have one third the size of the first harmonic size, and a similar relationship applies to the fourth harmonic, fifth harmonic, etc. do. Thus, the transmission line has a variable length when viewed at different frequencies.

Returning to the transmission lines 805 and 806, in this embodiment shorting the power supply devices 801, 802 at all frequencies N * f (transmit) (N is a positive integer), due to the nature of the transmission line The short circuit in the power supply device will be shown to be open at the first harmonic, where the length l (trans) = lambda / 4 of the transmission line and the short circuit at the second harmonic, where the length of the transmission line is In l (trans) = 2 * lambda / 4, the third harmonic will be shown as an open circuit, where the length of the transmission line is 3 * lambda / 4. In the following, the fourth, fifth harmonics and the like are similar.

The set of transmission lines 811 is individually adjusted to appear substantially open circuited at frequencies 2 * f (transmit), 3 * f (transmit), 4 * f (transmit), 5 * f (transmit) and the like. May be The choice of how many transmission lines to add to 811 is up to the embodiment, but when reaching a predetermined frequency, N * f (transmit), adding additional transmission lines adjusted to higher frequencies is required. It doesn't work.

In this embodiment, the transmission line 810 preferably has a length that creates an impedance Z (stubsystem) at the first harmonic when viewed in the direction shown in Figure 8, where Z (stubsystem) = R (load) + j * 0, that is, real impedance.

Repeatedly, the impedance seen by Z (stubsystem) is:

The transmission lines 807 and 808 convert the impedance Z into a series of alternating short-open-short-open impedances, so that each of the switching devices 803 and 804 sees these impedances individually.

-Continue this alternation to the N ^th harmonic.

Fully satisfying these impedance requirements is the specification of a Class F amplifier. If the transmission lines 805, 806 are true transmission lines that are not RF chokes, then the transmission line system 811 does not require even-numbered transmission lines 2, 4, 6, and so forth. 806 is already a short circuit at even harmonic impedances.

At a node called a 'signal summing node' 809, the first harmonics delivered from each switching device are summed. Since Z (stubsystem) is shorted at all harmonics above the first, switching devices 803, 804 cannot affect each other's operation at these frequencies. In the first harmonic the switching device 803 will see an impedance consisting of the R (load) 813 and the switching device 804. The switching device 804 will see an impedance composed of an R (load) 813 and a switching device 803. The sine wave signals from each branch will be summed together at the 'signal sum node'.

In order to avoid DC power flowing from the power supply devices 801, 802 to the load 813, a DC blocking capacitor 812 is located between the amplifier and the load. The load 813 can be of any size, and a smaller resistance will cause more power to be delivered.

Summarizing the circuit of FIG. 8, the switching devices 803, 804 generate sine waves that are summed at node 809, which is a 'signal summing node'. The resulting signal is a sine wave with an adjustable amplitude by varying the phase difference between the switching signals controlling the devices 803, 804. The load 813 benefits from the signal.

In a second embodiment of the phase amplification stage with a summer shown in Fig. 9, the sine waves to be summed are generated from the class E amplifiers. The amplifier is preferably adjusted to maximum efficiency.

The sinusoidal output signals of the two E-class amplifiers 912, 913 are summed by combining these outputs by the method shown in equation (5):

Here, S (out) is an output signal, and S1 and S2 are signals transmitted from respective class E amplifiers.

As already mentioned, it can be easily seen that the two sine waves add up to form one sine wave with an amplitude related to the phase φ c.

In the circuit of Figure 9, a basic Class E amplifier comprises resonators 905 and 906 connected to switching devices 903 and 904. Switching devices 903 and 904 are devices capable of fast switching between two states, where one state means that the device is short-circuited, and the other state is an open state of the device, i.e., no conduction. Means. These devices can be MOSFET transistors, or bipolar, LDMOS / VDMOS, HBT, GaAs, radio-tube, or any kind of switching device that can quickly change between substantial short and open impedances. Can be lifted. These switching devices are switched between the on state and the off state by a control signal from the limiter blocks L _{F +} , L _F− shown in FIGS. 6, 7A and 7B.

The resonator system is preferably adjusted to resonate near f (carrier), which is the carrier frequency of the transmitted signal. Since the resonator exhibits infinite impedance at this frequency, when switched at this frequency, the switching device 903 will generate a very large sinusoidal-like voltage swing across the resonator 905. will be. Similar phenomena occur in the switching device 904 and associated resonator 906.

The power supply devices 901, 902 are essentially power suppliers. These may be constant power supplies (ie providing a fixed voltage) or may be variable power supplies. These power supplies may be connected to an open-loop arrangement, or may be connected to a closed-loop (feedback) if their variable voltage depends on the output power. In configurations where their voltage changes, the change in voltage may be slow to adapt to the adjustment in power level, and may be fast to generate amplitude modulation in the output signal. In the latter case, the voltage level may or may not depend on the resulting output voltage as given by the phase amplifier. Such power supply devices exhibit substantially low impedance around and above the carrier frequency.

Band pass filters 907 and 908 have a basic function of removing any signal other than f (carrier), which is a modulated carrier frequency. In the art, optimizing existing non-ideal Class E amplifiers may require additional adjustments; The design principles may focus on concepts such as zero voltage switching (ZVS) and zero current switching (ZCS). Resonators, switching devices, band pass filters may or may not be adjusted to achieve this purpose.

The sinusoids generated from each of the class E amplifiers 912 and 913 are combined at node 909, which is the 'signal sum node'. DC blocking component 910 is located after node 909 to avoid current flow from power supply devices 901, 902 to load 911.

The load resistor 911 may be of any size, and the smaller the resistance value, the greater the power will be delivered.

Although the present invention has been introduced and described in accordance with specific embodiments, it will be understood by those skilled in the art that various modifications may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are also intended to be within the scope of the following claims.

Claims (43)

A power amplifier for generating a power amplified output signal from an input signal, the power amplifier, Phase amplification paths; And A phase amplification stage in the phase amplification path; The phase amplification stage receives a magnitude component of a power amplified output signal, wherein the phase amplification stage is configured to generate the power amplified output signal; Power amplifier responsive to the received magnitude factor. A power amplifier for generating a power amplified output signal from an input signal, the power amplifier, A magnitude amplification path for the magnitude component of the input signal; A magnitude amplifier stage in the magnitude amplification path; Phase amplification paths; And A phase amplification stage in the phase amplification path; The phase amplifying stage receives a magnitude component of the power amplified output signal and an amplified magnitude component of an input signal from the magnitude amplifier stage, wherein the phase amplifying stage comprises: A power amplifier responsive to the magnitude component of the input signal, the received magnitude component of the power amplified output signal, and the amplified magnitude component of the input signal. The power amplified signal of claim 1 or 2, wherein the power amplified signal generated by the phase amplification stage comprises: A power amplifier characterized by being substantially linearly related to the input signal in phase and magnitude. The phase amplification stage according to any one of claims 1 to 3, wherein And a difference detector to produce an output that depends on the difference between the received magnitude component of the input signal and the received magnitude component of the power amplified output signal. The method of claim 4, wherein the phase amplification path, And a magnitude feedback path for coupling the power amplified output signal to the difference detector as the magnitude component of the power amplified output signal. The method of claim 5, wherein the magnitude feedback path of the phase amplification path is: And an output envelope detector for sensing the magnitude component of the power amplified output signal. The method of claim 5 or 6, wherein the magnitude feedback path of the phase amplification path is And an attenuator for reducing the amplitude of the magnitude component of the power amplified output signal. The method according to any one of claims 1 to 7, And an input envelope detector for sensing a first input magnitude element of an input signal and coupling the first input magnitude element to a phase amplification stage. 9. The method of claim 4 and 8, wherein the first input size element is A power amplifier coupled to the difference detector of the phase amplification stage as a received magnitude component of the input signal. The phase amplification stage according to any one of claims 4 to 9, And an amplitude-phase converter for converting the output of the difference detector into a phase difference signal. The method according to any one of claims 1 to 10, wherein the phase amplification stage, And a limiter for generating phase elements of the input signal. The method according to claim 10 or 11, wherein the phase amplification stage, And a phase shifter for shifting the phase of an input phase element with the generated phase difference signal. The method of claim 12, wherein the phase shifter, And first and second phase shifters for respectively shifting the phase of an input phase element in the inverse of the generated phase difference signal and the generated phase difference signal. The phase shifter according to claim 12 or 13, And first and second multipliers / mixers for shifting the phase of an input phase element, respectively, inversely of said generated phase difference signal and said generated phase difference signal. The method according to claim 13 or 14, wherein the phase amplification stage, And first and second phase amplifiers for amplifying the output signals of the first and second phase shifters, respectively. The method of claim 15, wherein the first and second phase amplifiers, A power amplifier, characterized in that the switch-mode class F amplifier. The method according to claim 2, 15 or 16, wherein the first and second phase amplifiers, Coupled to the output of a magnitude amplifier, wherein the gain of the phase amplifiers is adjusted or modified by the magnitude amplifier. The method according to any one of claims 15 to 17, wherein the phase amplification stage, And an adder or power mixer for adding or mixing the outputs of the first and second phase amplifiers to produce a power amplified output signal. The method of claim 18, wherein the phase amplification stage, And a filter for filtering the output of the summer or power mixer to obtain a power amplified output signal. The method according to any one of claims 2 to 19, wherein the magnitude amplification pathway is And an input envelope detector for detecting an input magnitude element of an input signal and coupling the input magnitude element to the magnitude amplifier. The input envelope detector according to any one of claims 8 to 20, wherein the input envelope detector for detecting a first input magnitude element is: And the first input magnitude element is part of a magnitude amplification path coupled to the magnitude amplifier. 22. The amplitude amplifier stage of any one of claims 2 to 21 wherein A power amplifier comprising a class D amplifier. 23. The amplitude amplifier stage of any of claims 2 to 22 wherein A power amplifier comprising a pulse width modulated amplifier. 24. The amplifier of any one of claims 2 to 23 wherein the magnitude amplifier stage is A low pass filter, wherein the output delivered by the magnitude amplifier stage is a low pass filtered signal. The method according to claim 2, 12, 13, 14, wherein the phase amplification stage, And a non-linear amplifier for amplifying the output of the phase shifter, wherein the non-linear amplifier is coupled to the output of the magnitude amplifier and the non-linear amplifier produces a power amplified output signal. Gain of a non-linear amplifier is adjusted or modified by the magnitude amplifier. 27. The system of claim 25, wherein the non-linear amplifier is And third and fourth multipliers / mixers for mixing the outputs of the magnitude amplifiers with the outputs of the first and second multipliers / mixers, respectively. And a power mixer for mixing the outputs of the third and fourth multipliers / mixers. 27. The method of claim 26, wherein the non-linear amplifier is And a filter for filtering the output of the power mixer to obtain a power amplified output signal. A pulse width modulated amplifier, A difference detector or amplifier that produces one or more outputs that depend on the difference between the input signal and the feedback signal; A PWM modulator coupled with the difference detector to generate a pulse width modulated signal as an output; A power switch circuit for amplifying the output of the PWM modulator; And A feedback path coupling the one or more outputs of the power switch circuit to the difference detector as a feedback signal Pulse width modulated amplifier comprising a. The method of claim 28, And a low pass filter circuit coupled to the output (s) of the power switch circuit. The method of claim 28 or 29, wherein the feedback path, And an attenuator for reducing the amplitude of the feedback signal to the differential amplifier. The power switch circuit according to any one of claims 28 to 30, wherein A pulse width modulated amplifier comprising a pull-up switch having a pull-up output and a pull-down switch having a pull-down output. The method of claim 31, wherein the power switch circuit, When the power switch circuit is ON, the pull-up switch is open and the pull-down switch is shorted. When the power switch circuit is OFF, the pull-up switch is shorted and the pull-down switch is open. Pulse width modulated amplifier. 33. The method of claim 31 or 32, wherein the feedback path is: And a summer adding the pull-up output and the pull-down output to produce one feedback signal. 34. The method of claim 30 and 33, wherein the output of the summer, And a pulse width modulated amplifier supplied to said attenuator and to said differential amplifier through said attenuator. 35. The low pass filter according to any one of claims 29 and 31 to 34, wherein A pulse width modulated amplifier comprising a first inductor having a first terminal coupled to a pull-up output and a second inductor having a first terminal coupled to a pull-down output. 36. The pulse width of claim 35, wherein both the second terminal of the first inductor and the second terminal of the second inductor are coupled to the same terminal of the output capacitor carrying the output signal of the pulse width modulated amplifier. Modulated Amplifier. The method according to any one of claims 28 to 36, wherein the PWM modulator, A ring oscillator, wherein the ring oscillator comprises an inverting amplifier, a first phase shifter and a second phase shifter, wherein the phase shift of the first and second phase shifters is the output (s) of the difference amplifier. And is controlled in response to the pulse width modulated amplifier. The method of claim 37, wherein the difference amplifier, There is a signal difference between the two difference outputs having two difference outputs, indicating that the difference between the input signal and the received feedback signal is amplified, and wherein the first phase shifter has a first difference output. And a second phase shifter is controlled in response to a second difference output. The method according to claim 37 or 38, wherein the first phase output from the first phase shifter and the second phase output from the second phase shifter are: And a pulse width modulated amplifier coupled to produce an output of the PWM modulator received by the power switch circuit. 40. The method of claim 39, wherein the first and second phase outputs are A pulse width modulated amplifier characterized in that it is multiplied together to produce a PWM modulator output. 41. The pulse width modulated amplifier of claim 40, wherein the multiplication is performed using an exclusive OR function. The method according to any one of claims 28 to 41, Further comprising one or more filters to filter the output (s) of the difference amplifier, And the filtered outputs of the difference amplifier are coupled to a PWM modulator as inputs. The method according to any one of claims 28 to 42, And the power switch circuit comprises at least two MOSFET switch transistors.

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