KR20070032017A - Reflective layered system comprising a plurality of layers that are to be applied to a iii-v compound semiconductor material - Google Patents

Abstract

The present invention relates to a method for manufacturing a reflective layer system and to a reflective layer system to be applied to a III-V compound semiconductor material (4). In the present invention, a first layer containing phosphosilicate glass (PSG) is applied directly to the semiconductor substrate 4. Then, a second layer 2 containing silicon nitride covers the first layer, and finally a metal layer 3 is applied.

Description

REFLECTIVE LAYERED SYSTEM COMPRISING A PLURALITY OF LAYERS THAT ARE TO BE APPLIED TO A III-V COMPOUND SEMICONDUCTOR MATERIAL}

The present invention relates to a reflective layer system having multiple layers for application over a III-V compound semiconductor material of an optoelectronic semiconductor chip.

))가 반사되는 각도 범위에 걸쳐 표준 적분된다.There are reflective layers mainly for deflection of light rays on both the outer surface and the inside of the optoelectronic semiconductor chip, where most reflective layers are required to have high reflectance in all spatial directions. As a measure for this, the integral reflectance R _int can be used. In this case, the intensity reflected by the layer system (R (

)) Is standardly integrated over the range of angles that are reflected.

In order to obtain a reflective layer having a high reflectance over all solid angles, a composite layer of a dielectric layer having a low refractive index and a reflective metal layer may be used in addition to the pure metal layer.

As the material of the dielectric layer, for example, silicon oxide may be used because of the low refractive index. However, silicon oxide has the disadvantage of having a coefficient of thermal expansion significantly different from that of III-V compound semiconductors in forming a reflective layer system on the III-V compound semiconductor material, which can lead to problems with bonding. have.

It is an object of the present invention to provide a reflective layer system having an optimal integrated reflectance and an optimal stability for application onto a III-V compound semiconductor material and a method of making such a reflective layer system.

This object is achieved through a reflective layer system having the features of claim 1.

Preferred refinements of the reflective layer system are given in the dependent claims.

In the reflective layer system according to the present invention, there is a dielectric layer containing PSG (phosphosilicate glass) on the surface of the III-V compound semiconductor to which the reflective layer system is to be provided. An additional metal layer follows over the dielectric layer, preferably directly above, as seen from the III-V compound semiconductor surface. The dielectric layer is preferably placed directly on the III-V compound semiconductor surface.

There may also be additional layers above the layer system, for example a layer containing gold, which may be used to bond the surface of the reflective layer system with other surfaces by applying pressure and temperature.

Compared with the pure silicon oxide layer, the dielectric layer containing PSG has the advantage that the coefficient of thermal expansion can vary depending on the phosphate content. Therefore, the thermal expansion coefficient of the dielectric layer can be specifically matched with the thermal expansion coefficient of the III-V compound semiconductor. This avoids the bonding problems that may arise due to different coefficients of thermal expansion, for example, when a pure silicon oxide layer is applied on the III-V compound semiconductor surface.

In addition, as indicated in the document "Physical Properties of Phosphorus-Silica Glass in Fiber Preforms" (Journal of Communications Technology and Electronics, 1998, 43, 4, 480-484 p.), The refractive index of the PSG-containing layer is pure silicon. There is no significant difference with the refractive index of the oxide layer. The disclosure content of this document will be recorded herein in the form of citations.

The reflective layer system formed in this way has sufficient mechanical stability and at the same time optimal integration reflectivity.

Additional layers of several molecular layers may be present between the dielectric layer containing the PSG and the III-V compound semiconductor substrate, such as for the purpose of adhesion mediation.

The reflective layer system may be provided over other materials (eg, zinc selenide) with similar optical properties as the III-V compound semiconductor material.

There is preferably a sealing layer between the dielectric layer and the metal layer, which seals the dielectric layer around the chip to provide overall protection from moisture. PSG has a strong hygroscopicity depending on the phosphate content, which can be particularly meaningful if the metal layer cannot be deposited sufficiently and effectively directly over the dielectric layer due to process phosphoric acid being generated.

It is preferable that the sealing layer contains silicon oxide (not necessarily according to stoichiometry) or SiO _x N _y (x, y∈ [0; 1] and x + y = 1). Such materials provide the advantage of transmitting the overall electromagnetic radiation to be reflected and serving as a good bonding base for the metal layer overlying the material.

In one highly preferred embodiment of the reflective layer system, the phosphate content of the dielectric layer is selected such that the coefficient of thermal expansion of the dielectric layer matches the coefficient of thermal expansion of the III-V compound semiconductor material, which preferably improves adhesion properties significantly.

In another very preferred embodiment of the reflective layer system the metal layer contains at least one material from the group consisting of gold, zinc, silver and aluminum.

An additional layer may also be placed under the metal layer for adhesion mediation. Such adhesion media layer preferably contains Cr or Ti.

Preferably a fourth barrier layer comprising TiW: N is placed on the metal layer of the reflective layer system. Here TiW: N refers to a layer material formed by stacking Ti and W on one surface simultaneously in a nitrogen atmosphere. Alternatively or in addition, the barrier layer may also contain Ni, Nb, Pt, Ni: V, TaN or TiN.

The barrier layer should serve to protect at least some layers of the reflective layer system underlying the barrier layer from the harmful effects of the surrounding environment or further processes. Such a layer can thus be laminated, for example, as a shield to prevent the reflective layer system from contacting the metal melt, for example in a later soldering process. Alternatively the barrier layer may mean a barrier layer against ambient moisture. This is useful, for example, if one of the underlying layers contains silver to prevent silver migration.

Preferably conductive contacts are formed through the reflective layer system for electrical contact, and conductive connections are made through the insulating layer from the III-V semiconductor material by means of the conductive contacts. This allows for example the backside of the active layer sequence of a thin film LED chip to be in electrical contact.

In addition, in one preferred embodiment of the present invention, individual layers or all layers of the reflective layer system may be formed only in a partial region of the III-V semiconductor surface. In this way, the reflective layer system is completely formed only where the chip needs functionality. Once the III-V semiconductor surface is structured, the layers may also be stacked following the structure.

It is particularly desirable for the reflective layer system to be stacked over a III-V compound semiconductor material based on GaN, GaP or GaAs.

In this regard, the term "III-V compound semiconductor material based on GaN" preferably _denotes Al _n Ga _m In _1-nm N (0≤n≤1, 0≤m≤1 and n + m≤1). Refers to the ingredients contained. The material does not necessarily have to have a mathematically correct composition according to the formulas described above. Rather, it may contain one or more dopants and additional ingredients that are not generally different from the physical properties peculiar to the material. The formula contains only the essential elements (Al, Ga, In, N) of the crystal lattice for simplicity, but the elements may be partially replaced by small amounts of other materials.

The term "III-V compound semiconductor material based on GaP" is preferably a material containing Al _n Ga _m In _1-nm P (0≤n≤1, 0≤m≤1 and n + m≤1). Say. The material does not necessarily have to have a mathematically correct composition according to the formulas described above. Rather, it may contain one or more dopants and additional ingredients that are not generally different from the physical properties peculiar to the material. The formula contains only the essential elements (Al, Ga, In, P) of the crystal lattice for simplicity, but the elements may be partially replaced by small amounts of other materials.

The term " III-V compound semiconductor material based on GaAs " is preferably a material containing Al _n Ga _m In _1-nm As (0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and n + m ≦ 1). Say. The material does not necessarily have to have a mathematically correct composition according to the formulas described above. Rather, it may contain one or more dopants and additional ingredients that are not generally different from the physical properties peculiar to the material. The formula contains only the essential elements (Al, Ga, In, As) of the crystal lattice for simplicity, but these elements may be partially replaced by small amounts of other materials.

The reflective layer system according to the invention is particularly suitable for use in thin film light emitting diode chips (thin film LED chips), in which case the reflective layer system is placed inside the chip and the combination of mechanically stable stacks It is because it is essential in the function and reliability of a semiconductor chip.

The thin film LED chip has the following features in particular.

A reflective layer on the first major surface facing the support member of the active epitaxial layer sequence capable of generating electromagnetic radiation, reflecting at least a portion of the electromagnetic radiation generated within the epitaxial layer sequence into the epitaxial layer sequence; Laminated or formed.

The epitaxial layer sequence has a thickness of about 20 μm or less, in particular about 10 μm.

Preferably the epitaxial layer sequence has at least one semiconductor layer comprising at least one side with a mixed structure which, in an ideal case, exhibits a distribution in the epitaxial layer sequence which is nearly close to the Ergoth distribution. In other words, the epitaxial layer sequence is preferably ergodic and stochastic scattering.

The basic principle of a thin film light emitting diode chip is, for example, Appl. Phys. Lett. 63 (16) (co-authored by I. Schnitzer et al., October 18, 1993, 2174-2176p.), The disclosure content of which is hereby incorporated by reference in this application.

Thin film light emitting diode chips are almost similar to Lambert surface emitters.

All or some layers of the reflective layer system may be deposited using chemical vapor deposition (CVD). In this case, for example, plasma chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) may be used.

Influencing factors in the deposition of PSG thin films are included in Baliga et al. (BJ Baliga and SK Ghandhi, 1973 J. Appl. Phys. 44, 3, 990p.), The disclosures of which are incorporated herein by reference. Will be included in the form.

Other advantages, preferred embodiments and refinements of the reflective layer system and method of making the same are presented through the embodiments described below with reference to FIGS. 1A-1C, 2A and 2B, 3 and 4.

1A and 1B are schematic cross-sectional views of a reflective layer system on a III-V compound semiconductor surface.

1C is a schematic cross-sectional view of a reflective layer system on a structured III-V compound semiconductor surface.

2A and 2B are schematic cross-sectional views of a reflective layer system on a structured III-V compound semiconductor surface with different electrical contacts.

FIG. 3 is a graph plotting the integral reflectance of layer sequences of different dielectric layers and metal layers overlying a substrate with refractive index n = 3.4 as a function of the thickness of the dielectric layer.

FIG. 4 is a graph listing the integral reflectance of a layer system comprising a dielectric layer of silicon nitride and a metal layer of gold on a substrate having a refractive index (n) = 3.4 as a function of the wavelength of electromagnetic radiation.

In the embodiments and drawings, the same components or components that have the same functions are denoted by the same reference numerals. The illustrated figure elements, in particular the thicknesses of the illustrated layers, are not drawn to scale. On the contrary, there may be places that are partly oversized to aid understanding.

The reflective layer system according to FIG. 1A comprises a dielectric layer 1 of PSG material over III-V compound semiconductor material 4, wherein the phosphate content of the PSG has a coefficient of thermal expansion of the dielectric layer of the III-V compound semiconductor material ( It is about 20% to match the thermal expansion coefficient of 4). Regarding the variation of the coefficient of thermal expansion of PSG with the variation of the phosphate content, B. J. Baliga and S.K. By Ghandhi, 1974, IEEE Trans. Electron Dev., ED21, 7, 410-764p., The disclosure content of which is hereby incorporated by reference in this application. As seen in the III-V compound semiconductor material 4, the dielectric layer 1 is disposed after the metal layer 3 containing metals such as, for example, gold, zinc, silver and / or aluminum. In this case, the general layer thickness is 700 nm for the dielectric layer 1 and 600 nm for the metal layer 3. Underneath the metal layer 3 there may be, for example, an adhesion medium layer 7 containing Cr or Ti).

In the reflective layer system according to FIG. 1B, there is a sealing layer 2, for example SiN or SiON, between the PSG layer 1 and the metal layer 3, which seal layer has a PSG layer against moisture and other negative effects of surroundings. (1) to seal. Such a sealing layer can generally have a thickness of 50 nm.

As the barrier layer 6, another further layer containing, for example, TiW: N, Ni, Nb, Pt, Ni: V, TaN, TiN can be laminated on the reflective layer. Such barrier layer 6 serves to protect the reflective layer system or some layers of the reflective layer system from the effects of the surrounding or subsequent processes.

In particular TiW: N can be deposited on the layer system as barrier layer 6 having a thickness of 200 nm which is a general thickness.

The reflective layer system according to FIG. 1C resides on a III-V compound semiconductor material structured to have pyramidal shapes. The reflective layer system is surrounded by a dielectric layer 1 containing PSG, which is in turn sealed by an additional sealing layer 2. On it lies a continuous metal layer 3.

Since this structure has no exposed areas that can come into contact with moisture around the chip, for example, side edges, better sealing of the dielectric layer 1 is realized. The metal layer 3 also contributes to the sealing of the first layer 1. Through this layer system, an optimized reflex action is optionally implemented only in the pyramid 41.

An electrical contact point 5 may be formed over the pyramid 41 for electrical contact of the III-V semiconductor material 4 through the reflective layer system. 2a schematically shows contact points 5 fabricated in such a way that holes are etched in the dielectric layer 1 and the sealing layer 2 and then the metal layer 3 is laminated. In this case, the metal layer 3 is electrically conductively connected with the III-V compound semiconductor material 4 by the metal material filling the hole at least partly in the vertical direction and the entire surface in the horizontal direction.

As an alternative to the photolithographic structuring method described above, laser techniques may be used to manufacture the contact points 5. In this case, for example, a window is formed for the contact point 5 using a laser in the dielectric layer 1 and-optionally-in the sealing layer 2. The substrate 4 is exposed in the window. The window has, for example, a diameter of 1 μm to 20 μm, whereby a contact point 5 having a diameter of this size is formed in a subsequent process step. The metal layer 3 is then deposited. At this time, the metal material fills the window at least partly in the vertical direction and the entire surface in the horizontal direction, so that the metal layer 3 is electrically conductively connected with the III-V compound semiconductor substrate 4.

In figure 2b another possible shape of the electrical contact point 5 is schematically illustrated. Unlike the contact point 5 in the embodiment according to FIG. 2A, the vertical extension of the present contact point 5 corresponds at least to the height of the dielectric layer 1 and the sealing layer 2.

Such electrical contact points 5 can be produced, for example, as described below.

In the first step a window for the contact point 5 in the dielectric layer 1 and the sealing layer 2 is etched, for example using a structured mask formed of a photosensitive lacquer layer. Subsequently, as the metal layer 3 is deposited thereon, the metal material fills the window at least partly in the vertical direction and the entire surface in the horizontal direction. In a subsequent step, the lacquer layer is removed, for example with a suitable solvent, in which part of the metal layer 3 overlying the lacquer layer is also removed, leaving only the electrical contact point 5. For the completion of the reflective layer system a metal layer 3 can now be laminated which implements a lateral electrical connection between the individual contact points 5.

Even in this case, as an alternative to structuring the contact point 5 using the photolithography technique, it is possible to structure the contact point 5 using the above-described laser technique.

For example, a reflective layer system formed of a dielectric layer 1 and a metal layer 3 on a substrate having a refractive index n of 3.4, such as a semiconductor material, is higher when the dielectric layer 1 is made of silicon dioxide instead of silicon nitride (see FIG. 3). Has an integral reflectance. In this case, the substrate 4 may be formed of a semiconductor material having a refractive index of 3.4.

4 shows the value of the integral reflectance as a function of the wavelength of reflected electromagnetic radiation of a layer system formed of a layer of silicon nitride and a layer of 400 nm thick gold on a substrate 4 (e.g. of semiconductor material) with a refractive index of 3.4. It is written. Here, it can be seen that the integral reflectance of the layer system increases with the wavelength of the reflected electromagnetic radiation.

PSG (dielectric layer 1) may be deposited over III-V compound semiconductor material using CVD techniques (eg, PECVD techniques). Gas mixtures used in the PECVD technique contain, for example, pure oxygen or dinitrogen monoxide as an oxygen source, phosphine or trimethylphosphite as a phosphorus source and silane, disilane, dichlorsilane, diethylsilane or tetraethoxysilane as a silicon source. do. Argon or nitrogen can be added to each mixture as diluent gas. Especially frequently used gas mixtures contain silane, oxygen and phosphine or tetraethoxysilane, oxygen and phosphine. The PSG layer (dielectric layer 1) deposited in this manner can be sealed with silicon nitride (sealing layer 2) in situ in the next process step. In the next step, the metal layer 3 is now laminated. Alternatively, LPCVD techniques can also be used.

The reflective layer system can be stacked over III-V compound semiconductor material 4 based on GaN, GaAs or GaP, for example with an active layer sequence emitting photons, as described in the above embodiments. In this case, in particular, a photon emitting active layer of a thin film LED chip can be used.

The photon emitting active layer sequence may comprise, for example, pn junctions, double heterostructures, single quantum well structures (SQW structures) or multiple quantum well structures (MQW structures) according to the prior art. Such structures are known to those skilled in the art and will not be described in further detail. Quantum well structures within the scope of the present application include all structures in which the energy state of the charge carriers is quantized by charge carrier confinement. In particular, the designation of quantum well structure does not include an indication of quantization dimensionality. The quantum well structure thus comprises in particular quantum wells, quantum lines and quantum dots and all combinations of the structures.

Finally, the present invention is not specifically limited to the above embodiments, and all embodiments based on the basic principles described generally fall within the scope of the present invention. Also, different elements of different embodiments may be combined with each other.

This patent application claims the priority of German patent applications Nos. 102004031684.8-11 and 102004040277.9-33, the disclosures of which documents are to be incorporated into this patent application by reference.

The present invention is not limited by the above description based on the embodiments. Rather, the invention encompasses each new feature as well as each feature combination which implies each combination in particular of the features of the claims, even if the combination is not specified in the claims.

Claims (15)

As a reflective layer system for applying over III-V compound semiconductor material (4), On the III-V compound semiconductor material 4 there is a dielectric layer 1 containing PSG (phosphosilicate glass), On top of the dielectric layer 1 there is a layer 3 containing metal, Reflective layer system. Reflective layer system, There is a sealing layer (2) between the dielectric layer (1) and the metal layer (3), the sealing layer seals the dielectric layer (1) to prevent the ingress of moisture around the dielectric layer, Reflective layer system. The method of claim 2, The sealing layer 2 contains silicon nitride, Reflective layer system. The method of claim 2, The sealing layer 2 contains SiO _x N _y (x, y∈ [0; 1] and x + y = 1), Reflective layer system. The method according to any one of claims 1 to 4, The phosphate content of the dielectric layer 1 is selected such that the thermal expansion coefficient of the dielectric layer matches the thermal expansion coefficient of the III-V compound semiconductor material 4, Reflective layer system. The method according to any one of claims 1 to 5, The metal layer 3 contains at least one material from the group consisting of gold, zinc, silver and aluminum, Reflective layer system. The method according to any one of claims 1 to 6, An adhesive medium layer 7 exists between the metal layer 3 and the dielectric layer 1, Reflective layer system. The method of claim 7, wherein The intermediate layer 7 between the metal layer 3 and the dielectric layer 1 contains Cr or Ti, Reflective layer system. The method according to any one of claims 1 to 7, There is an additional barrier layer 6 above the metal layer 3, the barrier layer containing at least one material from the group formed of TiW: N, Ni, Nb, Pt, Ni: V, TaN and TiN, Reflective layer system. The method according to any one of claims 1 to 9, Conductive contacts 5 are formed through the reflective layer system and conductive connections from the III-V semiconductor material to the top layer are made by the conductive contacts. Reflective layer system. The method of claim 10, The contact points 5 are formed through etching, Reflective layer system. The method of claim 10, The contact points 5 are formed using a laser, Reflective layer system. The method according to any one of claims 1 to 12, At least one of the layers and / or the surface of the III-V compound semiconductor material 4 is structured, Reflective layer system. The method according to any one of claims 1 to 13, The III-V compound semiconductor material 4 contains at least one material based on GaAs, GaN or GaP. Reflective layer system. As a thin film light emitting diode chip, Including a reflective layer system according to any one of the preceding claims, Thin film light emitting diode chip.

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