KR20070031769A - Fast fourier transformer device using single butterfly and method therefor - Google Patents

Abstract

The present invention relates to a fast Fourier transform device and a method thereof, and more particularly to a fast Fourier transform device and a method using a single butterfly.

In the present invention, a single butterfly structure uses less memory when implementing an FFT, reduces the processing time of the FFT block, and uses a single butterfly structure that can read and process r data at a time. An apparatus and method for efficiently operating a memory are provided.

Accordingly, the apparatus of the present invention is a device for performing a fast Fourier operation using a single butterfly having a structure of Radix-2 ⁿ (where n is a natural number), comprising: a memory unit comprising four different subunit memories; A data address generator for generating a counter that increments a count value each time the butterfly operation is performed, a data address that can be read and written one by one without overlapping in each of the subunit memories based on the counter value, and the address A recording unit for storing input data based on the data address information received from the generator, and a reading unit for reading and outputting data to be input from the subunit memory one by one based on the data address information received from the address generator. It includes.

Butterfly, Single Butterfly, Fast Fourier Transform, FFT

Description

FAST FOURIER TRANSFORMER DEVICE USING SINGLE BUTTERFLY AND METHOD THEREFOR}

1 is a block diagram of an OFDM receiver to which the present invention is applied;

2 is a flowchart illustrating operation of a symbol performed in a receiver of an OFDM system according to the present invention;

3 is an internal block diagram of an FFT according to an embodiment of the present invention;

4 is a diagram representing addresses of data corresponding to four memories in the case of N = 128 according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a shape in which FFT input values for implementing a memory address as shown in FIG. 4 are stored;

6 is a circuit diagram for translating an address of an input memory according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating data stored in each sub-unit memory according to an example of N = 64 (2 ⁶ ) as shown in FIG. 5;

FIG. 8 is a diagram illustrating data that should be read from each subunit memory when a second butterfly operation is performed after the first butterfly operation is performed.

FIG. 9 is a diagram illustrating data to be read from each subunit memory when a third butterfly operation is performed after a second butterfly operation is performed. FIG.

FIG. 10 is a memory configuration diagram in which, in the example of N = 64 (2 ⁶ ), one data can be read from the sub-unit memories without overlapping in the butterfly operation of each step according to the present invention.

The present invention relates to a fast Fourier transform device and a method thereof, and more particularly to a fast Fourier transform device and a method using a single butterfly.

Orthogonal Frequency Division Multiplexing (hereinafter referred to as " OFDM ") in wireless communication systems is rapidly commercialized as the Fast Fourier Transform method is known. As described above, in an OFDM system, a transmitter transmits data using a fast inverse fast Fourier transformer (hereinafter referred to as "IFFT"), and a receiver is referred to as a fast fourier transformer (hereinafter referred to as "FFT"). To receive the data.

의 버터플라이 블록을 사용하여 구현이 가능하다. 여기서

는 x를 넘지 않는 최대 정수를 의미한다. N point FFT의 경우와 같이 최대

개의 버터플라이 블록을 모두 이용하는 구조를 파이프라인(pipeline) 구조라 한다. 반면에 하나의 버터플라이 블록을 이용하는 구조를 단일 버터플라이(single butterfly) 구조라고 한다.As a method for implementing such a fast Fourier transformer, it is common to use a butterfly structure representing a radix-r algorithm. Depending on how many times you use these butterfly structures, you can create an FFT block with a different structure. Typically for N point FFTs used in OFDM systems

It can be implemented using the butterfly block. here

Is the maximum integer not exceeding x. As in the case of N point FFT

A structure that uses all four butterfly blocks is called a pipeline structure. On the other hand, a structure using a single butterfly block is called a single butterfly structure.

In general, when implementing FFT in hardware, considering the complexity, a single butterfly structure is usually used. Therefore, the following describes a single butterfly structure.

A commonly used single butterfly architecture uses one butterfly block, one single-port SRAM and one double-port SRAM to implement the FFT. The single-port SRAM is a memory for reading and storing the result of the front end of the FFT, and the double-port SRAM is a memory for storing the input and output values of the butterfly.

의 클럭이 필요하다. 즉, 하나의 버터플라이 블록의 결과를 얻기 위해서 N 클럭이 소요된다는 의미가 된 다. 이것은 입력이나 출력 값을 저장하기 위해서 하나의 메모리를 사용하고 있기 때문에 한 클럭에 하나의 데이터를 읽어 들여서 나온 결과이다.In this way, FFT operation is performed while using one or one memory to store input and output values.

Clock is required. This means that it takes N clocks to get the result of one butterfly block. This is the result of reading one data per clock since one memory is used to store the input or output values.

On the other hand, the butterfly block using the Radix-r algorithm is designed to process r data in one clock. Therefore, the most efficient use of the Radix-r algorithm structure is to read r data at the same time and process them simultaneously. However, a device for FFT operation, which is generally used, uses one memory for calculation. Therefore, although the Radix-r algorithm is applied for FFT operation, it has a problem in that it does not utilize the butterfly block efficiently because it reads and processes one data at one clock.

It is therefore an object of the present invention to provide an apparatus and method for using less memory when implementing an FFT using a single butterfly structure.

It is another object of the present invention to provide an apparatus and method that can reduce the processing time for processing an FFT block using a single butterfly structure.

Another object of the present invention is to provide an apparatus and method for efficiently operating a memory through a single butterfly structure capable of reading and processing r data at a time.

An apparatus of the present invention for achieving the above objects is a device for performing a fast Fourier operation using a single butterfly having a structure of Radix-2 ⁿ (where n is self-number), the four different subunit memory A memory unit including a memory unit, a counter for increasing a count value each time the butterfly operation is performed, and data for generating a data address that can be read and written one by one without being duplicated in each of the subunit memories based on the counter value. An address generator, a recorder for storing input data based on data address information received from the address generator, and data to be input to the butterfly based on the data address information received from the address generator, one from each of the subunit memories. It includes a reading unit for reading and outputting.

A method of the present invention for achieving the above objects is for performing a fast Fourier operation using a single butterfly having a structure of Radix- ²ⁿ (where n is a natural number) and a device having four different subunit memories. A method comprising: counting a number of times a butterfly operation is performed, generating a data address that can be read and written one by one without overlapping in each of the subunit memories based on the counted value; Storing input data in the memory based on data address information, reading data stored in the subunit memory from each subunit memory based on the data address information, and inputting the data into the butterfly; Output by performing stepwise operation of butterfly It includes the process.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the preferred embodiment of the present invention. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

1 is a block diagram of an OFDM receiver to which the present invention is applied. Hereinafter, the overall operation performed in the OFDM receiver will be described with reference to FIG. 1.

The signal received in the radio band is received through the antenna ANT and input to the ADC converter 101. The ADC converter 101 quantizes the input analog signal into a digital signal. The quantized signal is input to the Rx Filter 103 to filter the quantized signal and then converts the serial signal into a parallel signal. In FIG. 1, a process of converting a serial signal into a parallel signal is not shown. The signal converted into the parallel signal in this way is input to the FFT converter 105. The FFT converter 105 performs demodulation which converts a signal in the time domain into a signal in the frequency domain and outputs the demodulated signal. As described above, when the FFT converter 105 is an N-point FFT converter, it outputs the 0 to N-1 th OFDM subcarriers. The signal output from the FFT converter 105 is input to the decoder 107. The decoder 107 may restore data by decoding the input signal.

Next, the operation performed in the apparatus will be described again with reference to the flowchart of FIG. 2.

2 is a flowchart illustrating operation of a symbol performed in a receiver of an OFDM system according to the present invention. It should be noted that the operation of FIG. 2 is performed every symbol unit.

The OFDM receiver receives a radio signal from an antenna in step 200. The OFDM receiver then proceeds to step 202 to convert the analog signal into a digital signal. The quantization process of converting the analog signal into a digital signal is performed in the ADC converter 101 of FIG. 1. In operation 204, the OFDM receiver filters a signal of a service band. That is, only signals of bands to be serviced by the OFDM receiver are extracted. The filtering process is an operation performed by the reception filter 103 of FIG. 1. After the filtering is performed, the OFDM receiver proceeds to step 206 and stores the filtered signal in the input memory of the FFT converter. In this case, a process of converting the filtered serial signal into a parallel signal is not illustrated in FIGS. 1 and 2.

Storage of the filtered signal in the input buffer of the FFT converter will be described in more detail with reference to FIG. 3 to be described later. Thereafter, the OFDM receiver proceeds to step 208 to perform a butterfly operation. That is, the FFT converter converts a signal of a time band into a signal of a frequency band. Since this operation must be performed for all subcarriers that the OFDM receiver intends to receive, the data on which the operation is performed is stored in the operation memory in step 210. In step 212, the OFDM receiver checks whether the operation is performed on all subcarriers. In other words, it checks to see if the butterfly operation is the last step.

When the butterfly operation is completed as a result of the check in step 212, the completed data is input to the decoder. The OFDM receiver then decodes the input data in step 214. However, if the butterfly operation is not completed as a result of the check in step 212, the OFDM receiver proceeds to step 208 to perform the butterfly operation on the remaining data.

Then again, the process of converting the signal in the time domain into the signal in the frequency domain by the butterfly operation in the FFT converter 105 will be described. First the FFT converter 105 stores the filtered signal in the FFT input memory. The butterfly operates while reading the signal stored in the input memory. Butterfly operation results are stored in operation memory. Here, the input memory and the operation memory can be used as the same one without using them separately. That is, it can be used to store the filtered signal in one memory and to store the filtered signal again in the corresponding memory. By repeating this process, the signal in the time domain is converted into a signal in the frequency domain when the butterfly's final operation is completed.

3 is an internal block diagram of an FFT according to an embodiment of the present invention. Hereinafter, an FFT internal block configuration and its operation according to an embodiment of the present invention will be described with reference to FIG. 3.

In the FFT internal block configuration shown in FIG. 3, the butterfly 320 is illustrated as an FFT structure using radix-2 ² / radix-2 as an example. Since radix-2 ² is used in FIG. 3, the memory 310 is composed of four pieces. That is, the memory 310 includes a first bank Bank_0 310a, a second bank Bank_1 310b, a third bank Bank_2 310c, and a fourth bank Bank_3 310c. Each bank of the memory 310 is one subunit memories 310a, 310b, 310c, 310d, and each of the subunit memories 310a, 310b, 310c, 310d reads one signal at a time and one at a time. The address is configured to do the work of storing the signal.

In addition, the commutator_read 308 aligns signals read from the subunit memories 310a, 310b, 310c, and 310d to enable radix-2 ² butterfly operation, and reads commutator_write. 312 realigns the result of the radix-2 ² butterfly operation to the corresponding position of each of the subunit memories 310a, 310b, 310c, and 310d. That is, the recording unit 308 designates the position of the input data, and the reading unit 312 allows the recorded data to be read normally. A data address generator 326 also informs the location of the data needed for the operation in the radix-2 ² butterfly. The common address generator 328 performs an operation of notifying a twist factor that is multiplied during the butterfly operation. At this time, the torsion factor multiplied during the operation is stored in a predetermined table of the common memory (Coefficient ROM), and the coefficient values are read according to the value indicated by the common address generator 328.

단계의 연산이 수행된다. 또한 하나의 단계를 계산하기 위해서 버터플라이를 N/r 만큼을 반복적으로 이용한다. 이때, 카운터(Counter)(324)는 버터플라이가 하나의 단계에서 몇 번 동작했는지를 카운트한다. 또한 상기 카운터(324)는 상기 카운트된 값을 공통 주소 발생기(328)와 데이터 주소 발생기(326)에 각각 알려준다. 이를 통해 각 주소 발생기들(326, 328)에서 각 반복횟수에 맞게 주소를 생성할 수 있다. 또한 상기 카운터(324)는 한 단계에서의 모든 버터플라이 연산이 끝나면 카운트 값을 0으로 리셋(reset)하고, 다음 단계의 연산을 위한 버터플라이 동작 횟수를 카운트한다.To perform FFT operation when using single butterfly structure

The operation of the step is performed. In addition, the butterfly is repeatedly used by N / r to calculate one step. At this time, the counter 324 counts how many times the butterfly has operated in one step. The counter 324 also informs the common address generator 328 and the data address generator 326 of the counted values, respectively. Through this, the address generators 326 and 328 may generate an address for each iteration number. In addition, the counter 324 resets the count value to 0 when all butterfly operations in one step are completed, and counts the number of butterfly operations for the next operation.

FIG. 4 is a diagram representing addresses of data corresponding to four memories when N = 128 according to an embodiment of the present invention. In FIG. 4, reference numerals 310a, 310b, 310c, and 310d correspond to the memory 310 of FIG. 3. In addition, when the memory is configured to have an address as described above, one piece of data may be read from each of the subunit memories 310a, 310b, 310c, and 310d at a time, and the read data may be stored in the location again.

4 may be applied to the same rule when N = 2 ^{p as} an example. Where p is the exponent and is the p power of 2. The number displayed in the memory of FIG. 4 indicates the order in which the input is input to the FFT. In addition, the memory addresses corresponding to the reference numerals 401 to 408 are values indicating the storage location. Therefore, the numbers located in the memory in FIG. 4 describe which addresses are written in the sub-unit memories 310a, 310b, 310c, and 310d when sequentially input to the FFT processor.

Looking at the rules for implementing the memory as shown in FIG. 4 can be described as follows. For convenience of understanding, it is assumed that data input to the FFT converter 105 of FIG. 1 is stored as shown in FIG. 5. That is, the data to be input is sequentially input to the first buffer, the second buffer, the third buffer, and the fourth buffer. In the order of data stored in the first buffer, a total of 32 data are input from the 0th data to the 31st data, and a total of 32 data from the 32nd data to the 63rd data are input to the data stored in the second buffer. In the case of data stored in the third buffer, 32 pieces of data are input from the 64th data to the 95th data, and the data stored in the fourth buffer is stored from the 96th data to the 127th data.

When data sequentially input as shown in FIG. 5 is stored in the sub-unit buffers 310a, 310b, 310c, and 310d of FIG. 3 as it is, when a multi-step operation is performed in the butterfly, as shown in FIG. Likewise, one data cannot be read or written from each of the four subunit memories 310a, 310b, 310c, and 310d. Therefore, the data recording position is changed as shown in FIG. 4 so that one data in each of the buffers is always read and the read data can be recorded. That is, the numbers written in the subunit memories 310a, 310b, 310c, and 310d in FIG. 4 indicate the order of data sequentially input in FIG. 5.

Data sequentially stored as shown in FIG. 5 is stored and aligned as shown in FIG. 4 based on the apparatus of FIG. 6 according to the present invention. When the content of FIG. 5 is applied as shown in FIG. 4, one data can be read from each of the sub-unit memories 310a, 310b, 310c, and 310d at once without overlapping in calculating the butterfly.

This will be described with reference to FIGS. 7 to 10 to help understand this. FIG. 7 is a diagram illustrating data stored in each sub-unit memory according to an example of N = 64 (2 ⁶ ) as shown in FIG. 5, and FIG. 8 is a second butterfly operation after the first butterfly operation is performed. This is a sequence of data to be read from each sub-unit memory when this is performed, and FIG. 9 is a flowchart of data to be read from each sub-unit memory when the third butterfly operation is performed after the second butterfly operation is performed. FIG. 10 is a memory configuration diagram in which one piece of data can be read from the sub-unit memories without overlapping in the butterfly operation of each step in the example of N = 64 (2 ⁶ ) according to the present invention.

7 to 10 show an example of N = 64 (2 ⁶ ). In this case, using Radix-2 ² , the butterfly is calculated in steps of 6/2 = 3. 7 to 9 show the order of data to be read from the memory for the butterfly operation in the third step.

In FIG. 7, as described above, data from 0 to 15 are input and stored in the first buffer, data from 16th to 31 are input and stored in the second buffer, and 32 is stored in the third buffer. The data from the 47 th data to the 47 th data are input and stored, and the 16th data from the 48 th data to the 63 th data are stored in the fourth buffer. In this case, data to be read in the first butterfly operation from the subunit memories 310a, 310b, 310c, and 310d may be 0th data, 4th data, 8th data, and the like as shown in the first row of FIG. 8. 12th data. However, as shown in FIG. 7, the order of the data is data located in the first buffer. Therefore, even though the memory is divided into small memory units as shown in FIG. 3, in order to perform 64 operations, the butterfly operation cannot be performed by only 16 operations and requires many operations.

In addition, as shown in FIG. 9, the order of input data required in the second step is 0, 1, 2, and 3rd data. 7 and 8, all of them become data existing in the first buffer.

Data read in the above process should be recorded in the read position again. Therefore, if each data is read one by one and written again one by one, even if the memory structure of the type shown in FIG. 3 has the same effect as when implemented as a single memory. Therefore, in the example of FIG. 6, the order of data recorded in the memory in the form of FIG.

This will be described again with reference to FIG. 6.

6 is a circuit diagram for converting a number of an input memory according to an embodiment of the present invention. For example, FIG. 6 should be stored in memory 0 based on the first shown in FIGS. 5 and 7. In the present invention, the location of data stored in memory 3 or other memory or the same memory is changed. It is an apparatus for doing so. Referring to Figure 6 as follows.

First, in the configuration of FIG. 6, each of the exclusive ORs 601, 602, 611, and 612 operators performs an exclusive OR operation on adjacent numbers of even numbers, and performs an exclusive OR operation on adjacent results of odd numbers. do. This results in the output of the final exclusive OR operator being written to address 1 and the result of the odd exclusive OR operator being written to address 0. And the input signal is shown in the form of x ⁰ , x ¹ , x ² , x ³ , x ⁴ ... as counted values of the butterfly counter.

In other words, the FFT input memory can be shared with the operation memory but the address or butterfly counter 324 of each memory can be used to read data of the number of memories at a time from each memory divided into the final operation at the same time. will be. Thus, the address of each memory is the number represented on the left in FIG. This value is expressed in binary to the right of FIG. 4. This value refers to the value counted by the counter 324 of the butterfly as well as the address. The arrangement of FIG. 5 may be changed as shown in FIG. 4 by using a memory representing a count value calculated by the butterfly. If the butterfly counter is divided by 2 bits from the LSB, and the preceding bits are subjected to an exclusive OR operation, and the bits following the exclusive OR operation are performed, a number consisting of two bits is obtained. I can make it. Therefore, if the next cyclic shift (cyclic shift) by this number can be easily changed as shown in FIG. Therefore, if the process of FIG. 6 is expressed as a polynomial, it may be expressed as Equation 1 below.

Butterfly counter: x ⁿ , x ^n-1 , ..., x ² , x, x ⁰

In Figure 6, n is odd: (x ⁿ + x ^n-2 + ... + x) (x ^n-1 + x ^n-3 + ... + x ² + x)

In FIG. 6, n is even: (x ^n-1 + ... + x) (x ⁿ + x ^n-2 + ... + x ² + x ⁰ )

 => (First bit: n is odd) (second bit: n is even)

In Equation 1, + means an exclusive OR.

On the other hand, when the input memory is used separately, the output of the reception filter 103 should be stored in the input memory before the FFT operation. In this case, the memory must be configured to correspond to the butterfly structure for the FFT operation. As with memory for operations, r memories are used to arrange one data at a time into one memory. 5 shows an input memory when the input memory is used separately.

As described above, when implementing a FFT operation using a single butterfly structure, it is possible to optimize the processing time of the FFT operation while using a memory having the same size as using a single memory by simple address manipulation.

Claims (4)

An apparatus for performing a fast Fourier operation using a single butterfly having a structure of Radix-2 ⁿ (where n is a natural number), A memory unit composed of four different subunit memories, A counter for incrementing a count value each time the butterfly operation is performed; A data address generator for generating a data address that can be read and written one by one without overlapping in each of the subunit memories based on the counter value; A recording unit for storing input data based on data address information received from the address generator; And a reading unit configured to read data to be input to the butterfly based on data address information received from the address generator, and output one by one from each of the subunit memories. The method of claim 1, A common memory for storing torsion factor values required for the operation of the butterfly; And a common address generator for generating an address of a torsion factor value required for a butterfly operation based on the counter value to provide the bit value to the butterfly. The data address generator of claim 1, wherein the data address generator comprises: The apparatus of claim 1, wherein the data address is generated using Equation 2. Butterfly counter: x ⁿ , x ^n-1 , ..., x ² , x, x ⁰ n is odd: (x ⁿ + x ^{n -2} + ... + x) (x ^{n -1} + x ^{n -3} + ... + x ² + x) n is even: (x ^n-1 + ... + x) (x ⁿ + x ^n-2 + ... + x ² + x ⁰ )  => (First bit: n is odd) (second bit: n is even) In Equation 2, "+" means an exclusive logical OR. A method for performing fast Fourier operations using a single butterfly having a structure of Radix-2 ⁿ (where n is a natural number) and a device having four different subunit memories, Counting the number of times the butterfly operation is performed; Generating a data address that can be read and written one by one without overlapping in each of the subunit memories based on the counted value; Storing input data in the memory based on the generated data address information; Reading data stored in the subunit memory from each subunit memory based on the data address information and inputting the data into the butterfly; And performing a stepwise calculation of the butterfly using the butterfly to output the butterfly.

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