KR20070026929A - Method of manufacturing a stacked semiconductor device - Google Patents

Abstract

A method for manufacturing a stack type semiconductor device is provided to improve an electrical reliability by preventing the generation of voids using a spacer formed at sidewalls of a second opening of a second insulating pattern. A gate structure(109) is formed on a substrate(100). A first insulating pattern(112) with first openings is formed on the resultant structure. A seed pattern(116) made of single crystal silicon is formed in the first openings. A second insulating pattern(114) with second openings(118) for exposing the first insulating pattern to the outside is formed on the resultant structure. A spacer(122) is formed at sidewalls of each second opening of the second insulating pattern. A single crystal silicon pattern(124) is filled in the second opening.

Description

Method of manufacturing a stacked semiconductor device

1 is a cross-sectional view showing a single crystal silicon film pattern formed by a method of manufacturing a stacked semiconductor device according to a first embodiment of the prior art.

2 is a cross-sectional view illustrating a single crystal silicon film pattern formed by a method of manufacturing a stacked semiconductor device according to a second embodiment of the prior art.

3 to 10 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device in accordance with a first embodiment of the present invention.

11 to 14 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100, 200: substrate 102, 202: device isolation film

104, 204: gate insulating film pattern 106, 206: gate electrode

108, 208: gate spacer 109, 209: gate structure

110 and 210: source / drain regions 112 and 212: first insulating film pattern

114, 214a: Second insulating film pattern 115, 215: First opening

116 and 216 seed layer pattern 118 and 218 second openings

122, 222: spacer 124, 224: single crystal silicon film pattern

The present invention relates to a method for manufacturing a stacked semiconductor device, and more particularly, to a method for manufacturing a stacked semiconductor device including a single crystal silicon film formed through a damascene method.

In general, depending on the crystal structure, materials can be classified into single crystal, poly crystal, and amorphous. The single crystal is composed of one crystal structure, the polycrystal is composed of a plurality of crystal structures, and the amorphous is composed of an irregular atomic arrangement instead of a crystal inside the material.

Since the polycrystal is composed of a plurality of crystal structures, it has many grain boundaries. In addition, when the grain boundaries are large, the movement and control of carriers such as electrons or holes are hindered. Therefore, in the manufacture of a semiconductor device including a stacked thin film transistor (TFT) or the like or a system on chip (SOC) or the like, a single crystal silicon film is used as a channel layer for forming an active region. Mainly choose.

The single crystal silicon film may be obtained by forming an amorphous silicon film on a thin film mainly made of single crystal silicon, and then heat-treating the amorphous silicon film to convert the crystal structure of the amorphous silicon film into a single crystal.

In addition, the single crystal silicon film may also be formed by a damascene channel silicon (DCS) process in which a selective epitaxial growth (SEG) process is performed to fill the inside of the opening after forming the opening exposing the seed. Can be obtained. When the selective epitaxial growth process is performed, the process time is long and the process cost is increased. However, since the crystal defects are small in the single crystal silicon film, the channel characteristics are improved.

Meanwhile, when the single crystal silicon film is formed by applying the damascene method, as shown in FIG. 1, when the second opening 20 defining the formation region of the single crystal silicon film 22 is formed, the second crystal is formed. Since the single crystal silicon film 22 is not well formed on the sidewall of the opening 20, the void 24 may occur. This is because a single crystal silicon film 22 formed to fill the second opening 20 through selective epitaxial growth from the seed layer pattern 16 surface has a poor growth profile on the sidewall of the second opening 20. The voids 24 are frequently generated. The semiconductor device formed on the single crystal silicon film by the voids 24 may cause defects.

Accordingly, as shown in FIG. 2, the second opening 20 having the positive inclination may be formed as a way to reduce the occurrence of the voids 24. As described above, when the second opening portion 20 has a positive slope, the second opening portion 20 is formed along the slope of the positive slope of the growth profile of the single crystal silicon film 22 due to the selective epitaxial growth. The occurrence of voids 24 at the sidewalls of the can be improved.

Thereafter, a polysilicon film (not shown) for thermally oxidizing the second interlayer insulating film 18 and removing the thermally oxidized portion is formed on a portion of the side surface of the single crystal silicon film 22. The forming process can be performed. In this case, the polysilicon film formed while covering the side surface of the single crystal silicon film 22 serves as a cap that prevents leakage current from the power supply to the single crystal silicon film 22, thereby increasing the operating voltage. Can be.

However, when the polysilicon film is etched to form a gate structure, the second opening 20 has a positive inclination so that an etching gas is formed in the sidewall portion of the single crystal silicon film 22 in contact with the polysilicon film. Since it is difficult to penetrate, residual polysilicon 26 is present on sidewalls of the single crystal silicon film 22 protruding from the second opening 20. The residual polysilicon 26 causes a defect of the memory device to be formed.

Accordingly, it is an object of the present invention to provide a method for manufacturing a stacked semiconductor device including a single crystal silicon film pattern suitable for providing a channel having few voids and no residual polysilicon on the sidewalls.

As a method of manufacturing a stacked semiconductor device according to an embodiment of the present invention for achieving the object of the present invention, first, a gate structure is formed on a substrate. A first insulating layer pattern is formed on the substrate, the first insulating layer having first openings covering the gate structure and exposing a surface of the substrate. A seed film pattern made of single crystal silicon is formed in the first openings. A second insulating layer pattern having a second opening exposing the seed layer pattern and the first insulating layer pattern on the gate structure is formed on the first insulating layer pattern. Spacers are formed on sidewalls of the second openings of the second insulating layer pattern. A single crystal silicon film pattern buried in the second opening having the spacer is formed.

As a method of manufacturing a stacked semiconductor device according to another embodiment of the present invention for achieving the object of the present invention, a gate structure is formed on a substrate. A first insulating layer pattern is formed on the substrate, the first insulating layer having first openings covering the gate structure and exposing a surface of the substrate. A seed film pattern made of single crystal silicon is formed in the first openings. A first preliminary insulating film pattern having a second opening having an upper width greater than the lower width is formed on the first insulating film pattern by exposing the seed film pattern and the first insulating film pattern on the gate structure. A single crystal silicon film pattern embedded in the second opening is formed. A part of the upper portion of the second preliminary insulating layer pattern is removed to form a second insulating layer pattern. Spacers are formed on sidewalls of the single crystal silicon film pattern exposed to the second insulating film pattern.

According to the above method, by forming a spacer on the sidewall of the inside of the second opening, the sidewall of the second opening is positively inclined so that the void generated when the sidewall of the second opening is negative or near vertically inclined. Can be reduced. In addition, in the deposition and etching of the polysilicon film for gate formation in a subsequent process, the single crystal silicon film pattern has vertical sidewalls due to the spacers. This reduces the likelihood that residual polysilicon remains as the etching gas is not reached and is etched. Therefore, the defect of the semiconductor element can be reduced.

Hereinafter, a method of manufacturing a stacked semiconductor device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the accompanying drawings, the dimensions of semiconductor substrates, layers (films), patterns, or structures are shown to be larger than actual for clarity of the invention. In the present invention, when each layer (film), region, pattern, or structure is referred to as being formed "on", "top" or "bottom" of a semiconductor substrate, each layer (film), region or patterns. Means that each layer (film), region, pattern or structure is directly formed on or below the semiconductor substrate, each layer (film), region or patterns, or is a different layer (film), another region, another pattern or Other structures may additionally be formed on the substrate.

Example 1

3 to 10 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 3, an isolation layer 102 and a gate structure 109 are formed on the substrate 100.

In detail, the isolation trench 102 is formed on the substrate 100 by performing a shallow trench isolation (STI) process to divide the substrate 100 into an active region and a field region. Subsequently, a gate insulating film (not shown) is formed on the substrate 100 on which the device isolation film 102 is formed by a thermal oxidation process, a chemical vapor deposition process, or an atomic layer deposition process.

A conductive film (not shown) and a gate mask (not shown) are sequentially formed on the gate insulating film. The conductive layer is made of polysilicon doped with an impurity and then patterned into a gate electrode. On the other hand, the conductive film may be formed of a polysilicide structure consisting of doped polysilicon and metal silicide.

The gate mask is formed of a material having a high etching selectivity with respect to a subsequently formed first interlayer insulating film (not shown). For example, when the first interlayer insulating film is made of an oxide such as silicon oxide, the gate mask is made of a nitride such as silicon nitride.

Subsequently, the conductive layer and the gate insulating layer are sequentially patterned using the gate mask as an etching mask. Accordingly, the gate insulating layer pattern 104 and the gate electrode 106 are formed on the substrate 100.

Subsequently, after the silicon nitride film is formed on the substrate 100 on which the gate electrodes 106 are formed, the silicon nitride film is anisotropically etched to form gate spacers 108 on both sidewalls of the gate electrodes 106. As a result, the gate structure 109 including the gate insulating film pattern 104, the gate electrode 106, and the gate spacer 108 is completed.

       Using the gate structures 109 as an ion implantation mask, impurities are implanted into the substrate 100 exposed between the gate structures 109 by an ion implantation process, and then a heat treatment process is performed to perform source / drain on the substrate 100. A contact region corresponding to the region 110 is formed. Subsequently, a nitride film liner (not shown) is formed on the spacer 108, the top surface of the gate electrode 106, and the substrate 100.

Referring to FIG. 4, a first insulating layer pattern 112 having a first opening 115 covering the gate structure 109 and exposing a surface of the substrate 100 is formed on the substrate 100. .

In detail, a first interlayer insulating layer is formed on the substrate 100 to completely fill the gate structure 109. As an example, the first interlayer insulating layer may be formed of an oxide such as BPSG, PSG, USG, SOG, or HDP-CVD.

Subsequently, the upper portion of the first interlayer insulating film is planarized using a chemical mechanical polishing (CMP) process or an etch back process.

Subsequently, after the first photoresist pattern 113 is formed on the planarized first interlayer insulating layer, the first interlayer insulating layer exposed to the first photoresist pattern 113 is anisotropically etched. As a result, first openings 115 are formed to partially expose the contact region 110 of the substrate 100. Thereafter, the first photoresist pattern 113 is removed by an ashing and cleaning process.

Referring to FIG. 5, a seed film pattern 116 made of single crystal silicon is formed in the first openings 115.

In detail, the seed is filled in the first opening 115 by performing selective epitaxial growth (SEG) using the surface of the substrate 100 as a seed, and covers the first insulating layer pattern 112. To form a film.

Subsequently, a seed layer pattern 116 is formed in the first openings 115. The seed layer pattern 116 has an upper width greater than a lower width due to the sidewall profile of the first opening 115. In this case, if the process temperature in the selective epitaxial growth process is less than about 750 ° C., the growth of single crystal silicon is not easy, and if the process temperature exceeds about 1,250 ° C., the process according to the growth of single crystal silicon It is not preferable because control is not easy. Therefore, the selective epitaxial growth process is preferably performed at a temperature of about 750 to 1,250 ° C, and more preferably at a temperature of about 800 to 900 ° C.

The reaction gas used in the selective epitaxial growth process uses a silicon source gas. Examples of the silicon source gas include silicon tetrachloride (SiCl ₄ ), silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorochloride silane (SiHCl ₃ ), and the like. It is preferable to use these individually, and you may mix and use two or more as needed.

Thereafter, as an example, the seed layer pattern 116 may be etched until the top surface of the planarized first insulating layer pattern 112 is exposed using a chemical mechanical polishing process or an etch back process.

Referring to FIG. 6, a second opening 118 exposing the seed layer patterns 116 and the first insulating layer pattern 112 on the gate structure 109 on the first insulating layer pattern 112. A second insulating film pattern 114 having a film is formed.

Specifically, a second interlayer insulating layer (not shown) made of an oxide is formed on the first insulating layer pattern 112 and the seed layer pattern 116. Subsequently, the upper portion of the second interlayer insulating film is planarized using a chemical mechanical polishing process or an etch back process.

Subsequently, after forming a second photoresist pattern 117 on the planarized second interlayer insulating layer, the second interlayer insulating layer exposed to the second photoresist pattern 117 is anisotropically etched. As a result, a second opening 118 is formed to partially expose the seed layer patterns 116 of the substrate 100 and the first insulating layer pattern 112 on the gate structure 109.

Thereafter, the second photoresist pattern 117 is removed by an ashing and cleaning process to form a second insulating layer pattern 114 having a second opening 118.

Referring to FIG. 7, a spacer nitride film 120 is continuously formed on the top surface of the second insulating layer pattern 114, the sidewalls and the bottom surface of the second opening 118.

Specifically, the spacer nitride film 120 made of silicon nitride (SiN) having a substantially uniform thickness on the top surface of the second insulating layer pattern 114, the sidewalls of the second opening 118, and the bottom surface thereof may be formed. Form. The spacer nitride film 120 may be formed by a low pressure chemical vapor deposition (LPCVD) process. The spacer nitride film 120 has a thickness of about 20 to 400 kPa, preferably about 50 to 200 kPa.

Referring to FIG. 8, spacers 122 are formed on sidewalls of the second insulating layer pattern 114 exposed through the second opening 118.

Specifically, anisotropic etching of the upper surface of the second insulating layer pattern 114, the sidewalls of the second opening 118, and the bottom surface of the spacer nitride film 120 is formed. As a result, spacers 122 are formed on sidewalls of the second insulating layer pattern 114 exposed in the second opening 118.

Referring to FIG. 9, a single crystal silicon film pattern 122 embedded in the second opening 118 having the spacer 122 is formed.

Specifically, the selective epitaxial growth process is performed using the seed film pattern 116 exposed on the bottom surface of the second opening 118 as a seed. As a result, a single crystal silicon film (not shown) is formed in the second opening 118 having the spacer 122 to sufficiently fill the second opening 118. Since the process for forming the single crystal silicon film is the same as the process for forming the seed film pattern 116, a detailed description thereof will be omitted.

Therefore, the single crystal silicon film is formed along the sidewall of the second opening 118 having the positive inclination and the spacer 122 is formed, thereby reducing the generation of voids in the sidewall of the second opening 118.

Thereafter, the single crystal silicon film is chemically mechanically polished to expose the top surface of the second insulating film pattern 114. As a result, the single crystal silicon film pattern 124 to be provided as a channel in the second opening 118 is completed.

Referring to FIG. 10, an upper portion of the second insulating layer pattern 114 adjacent to the single crystal silicon layer pattern 124 is removed.

In detail, the upper portion of the second insulating layer pattern 114 is thermally oxidized. Subsequently, the thermally oxidized second insulating layer pattern 114 is removed. As an example, the thickness of the second insulating layer pattern 50 to 500 Å may be removed. This is a process of exposing the sidewalls such that a polysilicon film (not shown) for forming subsequent gates is formed to a part of the sidewalls of the single crystal silicon film pattern 114. As a result, the polysilicon film formed while covering the side surface of the single crystal silicon film pattern 114 acts as a current blocking film so that no leakage current is generated from the adjacent power source to the single crystal silicon film.

Subsequently, a polysilicon film is stacked on the second insulating film pattern 114 and the single crystal silicon film pattern 114 to form an upper gate of the stacked semiconductor device. When the gate is formed by etching the polysilicon layer, an etch gas penetrates into the sidewall of the single crystal silicon film pattern 114 because the sidewall profile of the single crystal silicon film pattern 114 is close to the vertical by the spacer 122. It is easy to carry out and polysilicon can be removed completely. Thus, defects in the memory device due to residual polysilicon can be reduced.

According to the method of the present embodiment, the void problem that occurs when the single crystal silicon film pattern is formed by using the damascene method and performing the selective epitaxial process can be reduced by forming spacers on the sidewalls of the second openings. In addition, when the etching process is performed after the subsequent formation of the polysilicon film, the sidewalls of the single crystal silicon film pattern may be vertical to prevent the etching gas from reaching and thus prevent the remaining polysilicon from being generated.

Therefore, by employing the single crystal silicon film pattern according to the method of the present embodiment as a channel, it is possible to easily manufacture a stacked semiconductor device having improved electrical characteristics and reliability.

Example 2

11 to 14 are cross-sectional views illustrating a method of manufacturing a stacked semiconductor device in accordance with a second embodiment of the present invention.

First, by performing the same process as described with reference to FIGS. 3 to 5, as shown in FIG. 6, the first insulating film pattern 212, the second interlayer insulating film (not shown), and the second photo on the substrate. A resist pattern (not shown) is formed and patterned.

Referring to FIG. 11, the seed insulating layer pattern 216 and the first insulating layer pattern 212 existing on the gate structure 209 are exposed on the first insulating layer pattern 212, and an upper width thereof is the lower width. A second preliminary insulating film pattern 214 having a larger second opening 218 is formed. Subsequently, an ashing and cleaning process is performed to remove the second photoresist pattern.

Referring to FIG. 12, a single crystal silicon film pattern 224 embedded in the second opening 218 is formed. In this case, since the process for forming the single crystal silicon film pattern 224 is the same as the process for forming the seed film pattern 116 of the first embodiment, a detailed description thereof will be omitted.

Referring to FIG. 13, a portion of the second preliminary insulating layer pattern 214 is removed to form a second insulating layer pattern 214a. Subsequently, a spacer nitride film 220 is continuously formed on the top surface of the second insulating layer pattern 214a and the sidewall and the bottom surface of the second opening 218.

In the case of depositing and etching a polysilicon film (not shown) for subsequent gate formation on the single crystal silicon film pattern 224 and the second insulating film pattern 214a formed as described above, as shown in FIG. Similarly, problems may arise due to residual polysilicon. Accordingly, the possibility can be blocked by forming a spacer 222 (FIG. 14) made of an insulator of a subsequent process on the sidewall of the single crystal silicon film pattern 224 in which residual polysilicon can be left.

Referring to FIG. 14, spacers 222 are formed on sidewalls of the single crystal silicon film pattern 224 exposed to the second insulating film pattern 214a. In detail, the spacer nitride layer 220 is anisotropically etched to form spacers 222 on sidewalls of the single crystal silicon layer pattern 224.

By the above process, the sidewall profile of the single crystal silicon film pattern is close to the vertical by the formation of the spacer, so that the problem due to the residual polysilicon may be solved when the etching process is performed after the polysilicon film is formed in the subsequent process. Therefore, the defect of the memory device due to the residual polysilicon can be reduced.

Therefore, by employing a single crystal silicon film pattern as a channel as in the method of Example 1, it is possible to easily manufacture a stacked semiconductor device having improved electrical characteristics and reliability.

As described above, the single crystal silicon film pattern according to the present invention improves electrical reliability by reducing the occurrence of voids by forming spacers on the sidewalls of the second openings.

In addition, in the case of forming a stacked semiconductor device including a single crystal silicon film pattern formed by the method of the present invention, the sidewall profile of the single crystal silicon film pattern is close to vertical by the formation of the spacer. As a result, when the etching process is performed after the deposition of the polysilicon film for forming the upper gate, residual polysilicon does not remain, so that device defects may be reduced. Thus, the electrical characteristics of the semiconductor device are improved.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (9)

Forming a gate structure on the substrate; Forming a first insulating film pattern covering the gate structure on the substrate and having first openings exposing a surface of the substrate; Forming a seed film pattern formed of single crystal silicon in the first openings; Forming a second insulating layer pattern on the first insulating layer pattern, the second insulating layer pattern having a second opening exposing the seed layer pattern and the first insulating layer pattern on the gate structure; Forming a spacer on a sidewall of the second opening of the second insulating layer pattern; And Forming a single crystal silicon film pattern buried in the second opening having the spacers. The method of claim 1, wherein the seed layer pattern is formed by performing selective epitaxial growth using single crystal silicon of the substrate as a seed. The method of claim 1, wherein the forming of the spacers comprises: Continuously forming a nitride film for a spacer on the first insulating film pattern, the second insulating film pattern, and the seed film pattern; And And etching the spacer nitride film over the entire surface to form the spacer. The method of claim 3, wherein the spacer nitride film is formed to have a thickness of 20 to 400 GPa. The method of claim 1, wherein the forming of the single crystal silicon film pattern comprises: Forming a single crystal silicon film by performing selective epitaxial growth using single crystal silicon as a seed to completely fill the second opening on the second insulating film pattern; And And forming a single crystal silicon film pattern by polishing the single crystal silicon film so that the top surface of the second insulating film pattern is exposed. The method of claim 1, further comprising: thermally oxidizing an upper portion of the second insulating layer pattern; And And removing the thermally oxidized second insulating layer pattern. The method of manufacturing a stacked semiconductor device according to claim 6, wherein the thickness of removing the second insulating film pattern is 50 to 500 GPa. Forming a gate structure on the substrate; Forming a first insulating film pattern covering the gate structure on the substrate and having first openings exposing a surface of the substrate; Forming a seed film pattern formed of single crystal silicon in the first openings; Exposing a first insulating film pattern on the seed film pattern and the gate structure on the first insulating film pattern, and forming a second preliminary insulating film pattern having a second opening having an upper width greater than the lower width; Forming a single crystal silicon film pattern embedded in the second opening; Removing a portion of the second preliminary insulating layer pattern to form a second insulating layer pattern; And Forming a spacer on sidewalls of the single crystal silicon film pattern exposed to the second insulating film pattern. The method of claim 8, wherein the forming of the second insulating layer pattern comprises: Thermally oxidizing an upper portion of the second preliminary insulating layer pattern; And And removing the thermally oxidized insulating layer pattern.

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