KR20070023973A - Apparatus and method for inverting address input mode - Google Patents

Abstract

A semiconductor memory device capable of converting an address input mode is provided to increase compatibility by enabling the conversion of the address input mode through an external control signal or a command. An address input circuit includes a first address buffer(120) and a second address buffer(130). An address alignment circuit receives addresses from the first address buffer and the second address buffer, and then rearranges the addresses. During a first mode, the addresses of the first and second address buffers are transferred to the inside of the address input circuit without additional rearrangement. During a second mode, an address serially inputted to one of the first and second address buffers is reconfigured in parallel and then transferred to the inside of the address input circuit.

Description

Semiconductor memory device with switchable address input method {APPARATUS AND METHOD FOR INVERTING ADDRESS INPUT MODE}

1 is a block diagram for explaining a DDR address method input method.

2 is a block diagram illustrating a double pumping address (DPA) method.

3 is a block diagram for explaining a first embodiment of the present invention.

4 is a block diagram illustrating an address latch circuit of FIG. 3.

FIG. 5 is a timing diagram illustrating an address input through the configuration of FIG. 4. FIG.

6 is a block diagram for explaining a second embodiment of the present invention.

* Explanation of symbols for main parts of drawings *

10, 40, input latch 20, 50, 111: first latch

30, 60, 112: second latch 70, 112: third latch

100: clock controller 110: address latch circuit

120: input buffer 1 130: input buffer 2

200: instruction detector 210: instruction latch

220: input buffer 0

 The present invention relates to a semiconductor memory, and more particularly to an address input structure of the semiconductor memory.

Input all addresses such as double pumping address (DPA) and DDR (Double Data Rate) SDRAM, which receive one address for two clocks and input each address for the general memory device. The receiving method is used. In the DPA method, one address can be divided and input for two clocks, thereby reducing the number of input pins in half. Each address bit divided into two clocks can be reconstructed into one complete address through an appropriate delay circuit and a parallel-parallel circuit. The address multiplexing method, in which a row address and a column address are divided into two clocks, is also an address input method. On the other hand, in the address input method of DDR SDRAM which inputs one address bit in one clock, the input speed of the address is fast but the number of pins required for the input is twice that of the DPA method. For convenience of expression, the address input method is called a DPA method for receiving one address for two clocks, and the method of receiving one address for one clock is called a DDR method.

1 is a block diagram illustrating an address input path of a DDR system. Referring to FIG. 1, FIG. 1 illustrates a DDR address input in which an I / O (input / output unit) configuration of an address is formed in 16 bit units A0 to A15. The DDR system includes an input latch 10 for latching all address bits input, a first latch 20 for synchronizing with an instruction, and a second latch driven by an internal clock PCLK. When all the address bits are inputted at one time in synchronization with one clock, the addresses transferred internally are also latched in units of 16 bits, and the addresses via the second latch 30 are finally internally completed in 16-bit complete form. Delivered.

2 is a block diagram illustrating an address input path of a DPA method. Referring to FIG. 2, the DPA method uses an input latch 40 for temporarily storing 8-bit address bits, a first latch 50 for one clock delay, and an 8-bit address for one clock delay in synchronization with the internal clock PCLK. It consists of a second latch 60 for transmitting the inside, and a third latch 70 for latching an address that is not delayed. Among the 16-bit address bits constituting one address, A0 to A7 are referred to as lower addresses, and A8 to A15 are referred to as upper address bits.

The input latch 40 sequentially latches the upper address and lower address inputted during the two clocks in synchronization with the input / output clock IO_CLK. If the address bits of the lower addresses A0 to A7 are input first and the address bits of the upper addresses A8 to A15 are input to the next clock, the input latch 40 is the lower address A0 to A7 at the first clock. Latch. In the second clock, the input latch 40 latches the upper addresses A8 to A15 and the first latch 50 latches the lower addresses A0 to A7. In the third clock, the third latch latches the upper addresses A8 to A15, and the second latch latches the lower addresses A0 to A7. At this time, in synchronization with the internal clock PCLK generated from the external clock CLK, the lower addresses A0 to A7 of the second latch 60 and the upper addresses A8 to A15 of the third latch are simultaneously output and transferred to the inside. do. Each 8-bit address output in synchronization with the internal clock PCLK constitutes complete addresses of the AIs A0 to A7 and AJ A8 to A15 according to the serial-to-parallel switching operation by the above-described configurations.

Memory devices based on the two address input methods described above have different advantages. The DPA method can reduce the number of pins in half compared to the DDR method that inputs an address at one time, while the input speed is limited. On the other hand, when one address is input simultaneously for one clock like the DDR method, the number of pins increases but high speed operation is possible. In general, a memory device adopts one address input method. However, there was a problem that it is difficult to solve each of the shortcomings because they are not compatible with each other.

 The present invention has been proposed to solve the above problems, and an object of the present invention is to implement a memory device that can use both the DPA method and the DDR method.

An address input circuit of the present invention for achieving the above object includes a first address buffer; A second address buffer; And an address alignment circuit for receiving and rearranging addresses from the first address buffer and the second address buffer, wherein in the first mode, addresses of the first address buffer and the second address buffer are rearranged without any rearrangement. In the second mode, an address serially input into one of the first address buffer and the second address buffer is reconfigured in parallel and transferred to the inside.

In a preferred embodiment, an upper address is input to the first address buffer, and a lower address is input to the second address buffer.

In a preferred embodiment, the first mode is a mode in which the upper address and the lower address are simultaneously input.

In a preferred embodiment, the second mode is a mode in which the upper address and the lower address are sequentially input to only one of the first address buffer and the second address buffer.

In a preferred embodiment, the selection of the first mode and the second mode is controlled by an external control signal.

In a preferred embodiment, the selection of the first mode and the second mode is selected by a command.

In a preferred embodiment, the address input circuit includes a command detector for detecting a command and outputting a mode selection signal.

In an exemplary embodiment, the address alignment circuit includes: a first latch configured to sequentially latch an input address by an external clock; A second latch driving and receiving and storing an address of the first latch on a first internal clock; And a third latch driving and receiving and storing an address of the first latch on a second internal clock.

In a preferred embodiment, the first internal clock is applied to the second latch to latch one of an upper address and a lower address sequentially input to the first latch.

In a preferred embodiment, the second clock is applied to a third latch to latch an address not stored in the second latch among upper and lower addresses sequentially input to the first latch.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram showing a preferred embodiment of the present invention. Referring to FIG. 3, an address input circuit according to the present invention includes a clock controller 100 for generating a clock to align upper and lower addresses, an address latch circuit 110 for aligning an input address according to each mode, and an external device. An input buffer 1 120 and an input buffer 2 130 are temporarily stored.

The clock controller 100 generates and supplies clocks TAI_CLK, TAJ_CLK, and OUT_CLK for aligning addresses of the address latch circuit 110 by the mode selection signal DPA_SEL for selecting an address input method. The address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK are generated from an input / output clock IO_CLK provided from the outside in FIG. However, it will be apparent to those skilled in the art that the generation of the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK may be generated through internally used clocks rather than externally generated I / O clocks IO_CLK. . Waveforms according to the address input method of the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK will be described in the timing diagram of FIG. 5 to be described later.

The address latch circuit 110 prefetches an externally input address from an input buffer and transfers the address to an internal address. In particular, when all addresses used in the DDR method are received at a time, all addresses are prefetched and latched simultaneously from the input buffer 1 120 and the input buffer 2 130. At this time, the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK for address alignment have the same waveform as the input / output clock IO_CLK. However, there is a difference in delay for proper timing. On the other hand, when the address input mode is selected as the DPA mode and the mode selection signal DPA_SEL is 'HIGH', the address will be divided into the input buffer 1 120 for two clocks. At this time, the address latch circuit 110 receives the upper address A8 to A15 and the lower address A0 to A7 serially inputted through the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK output in response to the mode selection signal DPA_SEL. Are aligned in parallel and reconstructed to complete addresses. A detailed description of the address latch circuit 110 will be given in FIG. 4 to be described later.

The input buffer 1 120 is an input buffer that receives the lower addresses A0 to A7 in the DDR mode. In the embodiment of the present invention, it is assumed that the upper and lower addresses each consist of 8 bits. However, in the DPA mode, the upper address A8 to A15 and the lower address A8 to A15 are sequentially inputted through the input buffer 1 120 for two clocks. The input buffer 1 120 operates in both the DPA mode and the normal mode.

The input buffer 2 130 is an input buffer that receives only the upper addresses A8 to A15 in the DDR mode. However, in the DPA mode, the lower address and the upper address will be input through the input buffer 1 120, and the input buffer 2 130 is not used. When the DPA mode is selected, the input buffer 2 130 is deactivated by the mode selection signal DPA_SEL applied from the outside, and address transfer is limited.

The address input circuit according to the present invention can implement both the DDR mode for receiving one address all in one clock and the DPA mode for receiving the address in two clocks according to the mode selection signal DPA_SEL input from the outside. .

4 is a block diagram illustrating a detailed configuration of the address latch circuit 110 described in FIG. 3. Referring to FIG. 4, the address latch circuit 110 includes a first latch 111 that is prefetched and latched by an input / output clock IO_CLK with respect to an input address, and a lower address (by an internal address alignment clock TAI_CLK). A second latch 112 to which A0 to A7 are patched and latched, a third latch 113 to patch and latch higher addresses A8 to A15 by the internal address alignment clock T AJ_CLK, and Only the DDR mode includes a fourth latch that receives the upper addresses A8 to A15 in synchronization with the input / output clock IO_CLK.

The first latch 111 is controlled to prefetch and latch the 8-bit address input via the input buffer 1 120 by the input / output clock IO_CLK. In the DDR mode, the first latch 111 latches only the lower addresses A0 to A7. However, in the DPA mode, the upper addresses A8 to A15 and the lower addresses A0 to A7 are input and latched for two clocks in synchronization with the input / output clock IO_CLK.

The second latch 112 prefetches and latches data latched in the first latch 111 by the address alignment clock TAI_CLK. When the lower addresses A0 to A7 are input to the first latch 111, the lower addresses A0 to A7 of the first latch 111 are latched to the second latch 112 by the address alignment clock TAI_CLK. Timing will be synchronized. However, when the upper addresses A8 to A15 are latched in the first latch 111, the lower addresses A0 to A7 that are already latched are maintained without being input. The output of the second latch is controlled by the address alignment clock OUT_CLK generated by the clock controller 100.

The third latch 113 is driven by the address alignment clock TAX_CLK, and stores and outputs an input address. In the DDR mode, the third latch 113 may receive the upper addresses A8 to A15 from the fourth latch 114, but in the DPA mode, the third latch 113 receives the upper addresses A8 to A15 from the first latch 111. Will be saved. The address alignment clock TAJ_CLK latches the upper addresses A8 to A15 in synchronization with the timing at which the upper address is latched in the first latch 111. The flow path of the address bits represented by the reference numeral 1 describes the movement path of the upper addresses A8 to A15 in the DPA mode. The output of the latched data of the third latch 113 is controlled by the address alignment clock OUT_CLK generated from the clock controller 100.

The fourth latch 114 is a latch circuit that receives an address from the input buffer 2 130 described with reference to FIG. 3. However, this will be described only in the case of operation in the DDR mode, and in the DPA mode, since the input buffer 2 130 is inactivated and the address transfer is blocked, the path ② shown in the figure will be destroyed and only the path ① will be activated. .

The address latch circuit of FIG. 4 described above receives the upper addresses A8 to A15 and the lower addresses A0 to A7 at the same time in the DDR mode, and transfers them to the inside. Lower addresses are sequentially input. The upper and lower addresses sequentially input are stored in the second latch 112 and the third latch 113, respectively, by the address alignment clocks TAI_CLK and TAJ_CLK. As a result, the upper and lower addresses stored in the second latch 112 and the third latch 113, respectively, are reconfigured in the same arrangement as when all the address bits are simultaneously input in the DDR mode. When the upper and lower addresses are stored in the second latch 112 and the third latch 113, when the address alignment clock OUT_CLK activates the output, the upper and lower addresses input in series for two clocks are simultaneously internally. Will be output.

By controlling the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK described above, a time point of latching and outputting without a separate delay circuit can be controlled. Through the above-described configuration and operations, the upper and lower addresses input serially are rearranged into one complete address.

FIG. 5 is a timing diagram illustrating the configuration of FIG. 4 and input and rearrangement operations of addresses for respective modes. The operation of address input and reordering of the present invention will now be described based on the above-described drawings. Referring to FIG. 5, in the DDR mode in which the mode selection signal DPA_SEL is 'LOW', the address alignment circuits TAI_CLK and TAJ_CLK are generated at the same period as the input / output clock IO_CLK. Both the first latch 111 and the fourth latch 114 are activated to receive the lower addresses A0 to A7 and the upper addresses A8 to A15, respectively. In addition, the address alignment clock OUT_CLK has a predetermined delay but is generated to have the same waveform as the input / output clock IO_CLK to control the output of the second latch 112 and the third latch 113. In the DDR mode, the upper and lower addresses are simultaneously input through the first latch 111 and the fourth latch 114 so that separate address alignment is unnecessary. Therefore, the address alignment clocks TAI_CLK and TAJ_CLK also have the same period as the input / output clock IO_CLK.

However, when the mode selection signal DPA_SEL transitions to 'HIGH' and switches to the DPA mode, the period of the internal address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK is doubled. In addition, the fourth latch 114 is inactivated, and the upper and lower addresses sequentially input to the first latch 111 are respectively the second latch 112 and the third latch 113 by the address alignment clocks TAI_CLK and TAJ_CLK. Are optionally prefetched and stored. The second latch 112 latches the lower addresses A0 to A7: TAI0 by the address alignment clock TAI_CLK. The third latch 113 prefetches and stores the upper addresses A8 to A15: TAJ0 output from the first latch after one clock (based on IO_CLK) by the address alignment clock TAJ_CLK.

As a result, the address lower address TAI0 and the upper address TAJ0 stored in the second latch 112 and the third latch 113 are rearranged in parallel so that all the address bits are rearranged in one complete form of the address unit A0. Will be configured. When the upper and lower addresses input in series are internally aligned in the second latch 112 and the third latch 113, they will be simultaneously output internally by the address alignment clock OUT_CLK. In this way, an address input circuit capable of inputting addresses in both the DDR mode and the DPA mode is configured by continuously inputting one address for two clocks and rearranging internally.

6 is a block diagram illustrating another embodiment of the address input circuit of the present invention. In the embodiment of FIG. 3, a separate pin is provided to select a mode from the outside, and the above-described mode switching is performed. However, the configuration of FIG. 6 includes a circuit capable of mode switching by a command. Here, the same reference numerals as in FIG. 3 shown above indicate the same members having the same function. Referring to FIG. 6, the address input circuit of the present invention may determine whether the input buffer 0 (200), the instruction latch (210), and the valid instruction that receive an instruction that plays the role of the mode selection signal (DPA_SEL) of FIG. And a command detector 200 for determining. Through such a configuration, the address input circuit of the present invention can select an address input mode through a command.

The input buffer 0 200 stores a command CMD input in synchronization with the address. Of course, the input / output of the input buffer 0 (200) is controlled by the input / output clock (IO_CLK) and is synchronized with the operation of the input buffer 1 (120) and the input buffer 2 (130) to which an address is input.

The instruction latch 210 is configured to be synchronized with the first latch 111 or the fourth latch 114 of FIG. 4 described above.

The command detector 220 detects an input command and determines whether the command indicates a DDR mode or a command defining a DPA mode. In the case of the command indicating the DDR mode, the input buffer 2 130 is activated to allow the upper address to be input simultaneously with the lower address. The address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK of the clock controller 100 are controlled to have the same period as the input / output clock IO_CLK. On the other hand, when the input command is a command defining the DPA mode, the command detector 220 deactivates the input buffer 2 130 in response to this, thereby limiting the input of the address. In addition, the command detector 220 controls the clock controller in the DPA mode so that the upper and lower addresses to which the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK are input in series are internally reconfigured.

The clock controller 100 generates and supplies clocks TAI_CLK, TAJ_CLK, and OUT_CLK for aligning addresses of the address latch circuit 110 in response to the output of the command detector 220. If the command detection result indicates the DDR mode, the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK will be generated at the same period as the input / output clock IO_CLK. This means that the mode selection signal of FIG. 5 is generated in the same waveform as when the signal is 'LOW'. However, when the command detection result of the command detector 220 indicates a command indicating the DPA mode, the command detector 220 generates a clock signal having a period twice as long as the input / output clock IO_CLK and having opposite logic values. The waveform of the address alignment clock at this time is the same as the waveform shown when the DPA_SEL of FIG. 5 transitions to 'HIGH'.

The address latch circuit 110 temporarily stores an address input through the input buffer 1 120 and the input buffer 2 130 by the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK and transfers the address to the inside. When the command inputted in synchronization with the address indicates the DDR scheme, the address bits simultaneously input through the input buffer 1 120 and the input buffer 2 130 are latched. In this case, the address alignment clocks TAI_CLK and TAJ_CLK may be input to prefetch and latch all addresses simultaneously from the input buffer 1 120 and the input buffer 2 130. In this case, the address alignment clocks TAI_CLK and TAJ_CLK for address alignment have the same waveform as the input / output clock IO_CLK. On the other hand, if the command is a command indicating the DPA mode, the address will be divided into two clocks into the input buffer 1 (120). At this time, the address latch circuit 110 aligns the upper and lower addresses serially input in parallel through the address alignment clocks TAI_CLK, TAJ_CLK, and OUT_CLK output to configure the DPA mode operation, and reconfigures them into complete addresses.

The input buffer 1 120 is an input buffer that receives the lower addresses ADDR1: A0 to A7 in the DDR mode. When the command is in the DPA mode, the upper address A8 to A15 and the lower address A8 to A15 are sequentially inputted through the input buffer 1 120 for two clocks. The input buffer 1 120 operates in both the DPA mode and the DDR mode.

The input buffer 2 130 is an input buffer which receives only the upper addresses ADDR2: A8 to A15 in the DDR mode. However, when the command detector 220 indicates the DPA mode, the input buffer 2 130 is inactivated and the lower address and the upper address are input through the input buffer 1 120.

According to the embodiment of the present invention through the above-described configuration, it is configured to set the address input mode through a command. In particular, when a command is entered to switch to the DPA mode, the path for inputting the upper address is deactivated, and the upper and lower addresses are serially input as the address to which the lower address is input. Internally, addresses serially inputted by the address alignment clock are reconstructed in parallel so that a complete address unit is delivered internally.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

 As described above, the present invention is configured to be compatible with the DPA method and the DDR method to enable the switching of the address input method through an external control signal or a command to implement a highly compatible semiconductor memory device.

Claims (10)

A first address buffer; A second address buffer; An address alignment circuit for receiving and rearranging addresses from the first address buffer and the second address buffer, In the first mode, addresses of the first address buffer and the second address buffer are transferred without any rearrangement, and in the second mode, an address inputted serially into any one of the first address buffer and the second address buffer. Address input circuit, characterized in that to deliver in the reconfigured in parallel. The method of claim 1, And the first address buffer is a buffer to which an upper address is input, and the second address buffer is input to a lower address. The method of claim 2, And the first mode is a mode in which the upper address and the lower address are simultaneously input. The method of claim 3, wherein And the second mode is a mode in which the upper address and the lower address are sequentially input only to any one of the first address buffer and the second address buffer. The method of claim 1, The selection of the first mode and the second mode is controlled by an external control signal. The method of claim 1, And the selection of the first mode and the second mode is selected by a command. The method of claim 6, And the address input circuit includes a command detector for detecting a command and outputting a mode selection signal. The method of claim 1, The address alignment circuit, A first latch for sequentially latching an input address by an external clock; A second latch driving and receiving and storing an address of the first latch on a first internal clock; And a third latch driving and receiving and storing an address of the first latch on a second internal clock. The method of claim 8, And the first internal clock is applied to the second latch to latch one of an upper address and a lower address sequentially input to the first latch. The method of claim 9, And the second clock is applied to a third latch to latch an address not sequentially stored in the second latch among upper and lower addresses sequentially input to the first latch.

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