KR20070023570A - Interface circuit and semiconductor device - Google Patents

Abstract

(OBJECTIVE) In an interface where the phase relationship of the data and the strobe signal for sampling the data is different at the input and output, the circuitry that enables loopback testing by adjusting the phase of the input and output data and the strobe signal. offer.

(Solution means) In order to test the phase shift 30 and the sampling circuit 40 on the input side, the phase shift circuit 20 on the output side outputs the phases of DQ and DQS together, and the DQ, The DQS is input from the output buffers 14 and 15 to the input buffers 16 and 17 respectively, so that the DQS is shifted by 90 degrees in the phase shift circuit 30 and the DQ is sampled in the sampling circuit 40. To test the output side function, the phase shift circuit 30 is controlled so that the DQS on the input side does not phase shift, the phase shift circuit 20 on the output side sets the phase shift amount of the data sampling clock to 90 degrees, and the phase of the DQS. The shift amount is fixed at 180 degrees, and the DQS, which has been phase shifted 90 degrees with respect to the DQ in advance, is input from the output buffer 15 to the input buffer 17, and the phase shift circuit 30 does not shift the phase. 40) samples the loopbacked DQ with a 90 degree phase shifted DQS.

 Data signal, strobe signal, phase, shift, loopback.

Description

INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE}

BRIEF DESCRIPTION OF THE DRAWINGS The figure for demonstrating the operating principle of one Embodiment of this invention.

2 is a diagram showing the configuration of an embodiment of the present invention.

3 is a timing diagram illustrating DQ and DQS at the time of writing and reading of the DDR SDRAM.

4 shows a conventional typical configuration of an interface circuit of DDR SDRAM.

(Explanation of the sign)

10 Control circuit 12, 13 Latch circuit

14, 15 output buffer 16, 17 input buffer

20, 20 ', 30, 30' phase shift circuit 40 sampling circuits

100 BIST circuit 101 PRBS generating circuit

102 PRBS expectation matching circuit 105 DQ terminal

106 DQS jack 111 selector

112, 113 latch circuit (register) 114, 115 output buffer

116, 117 input buffer 120 WDLL

130 RDLL 140 Lead FIFO

150 MDLL

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to a configuration suitable for high speed testing of an interface where a signal and a phase of a strobe signal sampling the signal differ in output and input.

Double Data Rate (DDR) Synchronous DRAM (SDRAM) uses the rising and falling edges of an external clock to input and output data at twice the frequency, resulting in shorter defined data widths than single data rate (SDR) SDRAMs. Lose. In the DDR SDRAM, since the timing of data transfer from the controller side to the receiver of the DRAM and the timing of data transfer from the DRAM to the receiver of the controller are informed, the bidirectional data strobe signal DQS is used. That is, this data strobe signal DQS is used as a reference clock for the operation of input / output of data at the time of read / write.

At the time of reading, the edge of the data strobe signal DQS and the read data DQ from the DDR SDRAM are shown by a DLL (Delay Lock Loop) circuit or internal control in the DDR SDRAM as shown in FIG. 3. The edges coincide (almost coincide with the edges of the clock signals CK, / CK). For this reason, the interface (controller) which is not shown in figure shows the data strobe signal DQS to the center of the read data DQ when the read data DQ and the data strobe signal DQS are received from the DDR SDRAM. The sample is delayed by a phase shift circuit (refer patent document 1). In Fig. 3, the phase between the edges of the data strobe signal DQS becomes 180 degrees for one cycle (360 degrees) of the clock signals CK and / CK, and at the time of reading, the data strobe signal is provided by the interface circuit (controller). The read data DQ is sampled by phase shifting the DQS by 90 degrees.

At the time of writing, as shown in Fig. 3, the rising and falling edges of the DQS supplied to the DDR SDRAM from the interface (controller) side (not shown) are located at the center of the write data DQ. As shown in FIG. 3, the phase of the DQS is delayed by 90 degrees with respect to the DQ, and is supplied to the DDR SDRAM. The receiver of the DDR SDRAM takes in data based on the rising and falling transition of the DQS.

Fig. 4 shows an outline of the circuit configuration of the output side and the input side of the data DQ and the data strobe signal DQS in the interface of the conventional DDR SDRAM. Referring to Fig. 4, on the output side, the phase shift circuit 20 'is phased 90 degrees with respect to the data DQ with respect to the clock signal CLK (a clock signal for synchronization supplied to the interface and also supplied to the DDR SDRAM). Shift-shift output, and phase-shift the data strobe signal DQS 180 degrees with respect to the clock CLK, and output the latched circuits 12 and 13 with the clock from the phase shift circuit 20 '. Each latch is output to the output terminal via the output buffers 14 and 15, respectively. This ensures the setup time / hold time in the receiver of the DDR SDRAM (not shown).

On the input side, since the read data DQ and the data strobe signal DQS are output from the DDR SDRAM at the same timing, the read data DQ and the data strobe signal DQS output from the DDR SDRAM are input buffers (16, 17). Each of the data strobe signals DQS is output by being phase shifted by 90 degrees in the phase shift circuit 30 ', and the sampling circuit 40 phases the read data DQ from the input buffer 16. It samples by the data strobe signal 90 degree phase shifted output from the shift circuit 30 '(refer patent document 1). This ensures the setup time / hold time of the sampling circuit 40.

In the interface shown in Fig. 4, for example, at the time of testing an output function (a circuit system for outputting write data and data strobe signal DQS in phases of 90 degrees and 180 degrees in a DDR SDRAM), an output signal is tested. Automatic Test Equipment) contrasts with expectations. In addition, when testing the interface's input / output function (a circuit system that samples the read data by phase shifting the received data strobe signal DQS by 90 degrees from the read data and the data strobe signal DQS from the DDR SDRAM), Check if the signal is operating normally by inputting the signal.

The interface is mounted on a DIMM, such as a Fully Buffered (FB) -Dual Inline Memory Module (DIMM), for data exchange with DRAM on the DIMM, and buffers the data inside the chip to AMB or memory controller of the subsequent DIMM. Applies to AMB (Advanced Memory Buffer) to send and receive data from point to point.

[Patent Document 1] Japanese Unexamined Patent Publication No. 2005-78547

As described with reference to FIG. 4, a high speed tester is required when testing the output function and the input function of the interface for the high speed DDR SDRAM. High speed testers are expensive and have the challenge of increasing test costs. Increasing test costs leads to higher product costs.

In testing the above interfaces, application of a magnetic loopback test is contemplated in order to test with a low speed tester for mass production testing, for example, instead of a high speed tester. However, in the DDR SDRAM and its interface, since the phase between the data DQ and the data strobe signal DQS is different at the input and the output, the outputs of the DQ and DQS from the output buffer of the interface are converted to the DQ and DQS of the interface. It can be seen that it is impossible to go back to the input buffers and perform loopback tests.

For example, in Fig. 4, the phase shift circuit 20 'on the output side phase shifts 90 degrees and 180 degrees, respectively, and outputs DQ and DQS output from the output buffers 14 and 15 to the input buffers 16 and 17, respectively. If the DQS is sampled by phase shifting the DQS by 90 degrees with the phase shift circuit 30 ', the input side will sample the DQS by 180 degrees phase shift on the input side, and the edges of the DQ and the DQS overlap. It accurately samples the point of change in DQ (the edge of DQ overlaps the edge of DQS). Thus, the loopback test has a problem that the output function and input function of the interface cannot be tested correctly.

In order to solve the said subject, invention disclosed in this application consists of the following structures schematically.

A circuit according to an aspect of the present invention performs input and output of a data signal and a strobe signal that defines the timing of sampling of the data signal, and a specification in which the phase relationship between the data signal and the strobe signal differs in input and output. As an interface circuit of a circuit, a circuit on the side of outputting a data signal and a strobe signal varies and outputs at least one phase shift amount of the output data signal and the output strobe signal based on the input phase shift control signal. A circuit for switching and controlling a phase difference between the data signal and the strobe signal, wherein a side for inputting the data signal and the strobe signal includes at least one phase of the input data signal and the input strobe signal based on the phase change control signal; By varying the shift amount, the difference between the input data signal and the strobe signal And a switching control circuit for a car.

A circuit according to another aspect of the present invention is a phase shifted data signal by selecting one of at least two phase shift amounts based on a phase shift control signal inputted by an output circuit that outputs the data signal and the strobe signal. And a first phase shift circuit for phase shifting the strobe signal by a predetermined phase shift amount. In addition, a second phase shift circuit for inputting a data signal and a strobe signal may select one of at least two phase shift amounts and phase shift the input strobe signal based on the phase shift control signal; And a sampling circuit for sampling the input data signal in response to the strobe signal output from the second phase shift circuit.

In the interface circuit according to the present invention, the first and second phase shift circuits respectively select one of the two phase shift amounts in correspondence with the phase relationship between the output and the input of the data signal and the strobe signal, During the test, the phase shift amount designated by the phase shift control signal is selected, and the phase relationship between the data signal and the strobe signal in the input circuit is correctly operated by loopback of the data signal from the output circuit and the strobe signal to the input circuit. And / or whether the phase relationship between the data signal and the strobe signal in the output circuit is properly operated.

In the interface circuit according to the present invention, in the normal operation, in the output side circuit, the first phase shift circuit phase shifts the data signal so that the phase between the data signal and the strobe signal becomes a predetermined first value, and the input side circuit. In the second phase shift circuit, the strobe signal is phase shifted to the first value, and in the test of the input side circuit, in the output side circuit, the first phase shift circuit sets the phase of the data signal and the strobe signal to the same phase. In the input side circuit, the data signal and strobe signal of the same phase output from the output side circuit are input, and the 2nd phase shift circuit may phase-shift a strobe signal to a 1st value, and may output it to a sampling circuit.

In the interface circuit according to the present invention, in the test of the output side circuit, in the output side circuit, the first phase shift circuit sets the phase between the data signal and the strobe signal to the first value, and in the input side circuit, The phase shift circuit may be configured such that the phase shift of the strobe signal is zero.

In the interface circuit according to the present invention, the data signal and the strobe signal may be the data signal DQ and the data strobe signal DQS of the DDR SDRAM. In this case, in the normal operation, in the output side circuit, the first phase shift circuit is set so that the phase difference between the data signal and the strobe signal is 90 degrees, and in the input side circuit, the second phase shift circuit performs the phase of the input strobe signal. Phase-shifted by 90 degrees and outputted to the sampling circuit, and when testing the input side circuit, in the output side circuit, the first phase shift circuit sets the phase of the data signal and the strobe signal to the same phase, and in the input side circuit, It is good also as a structure which inputs the data signal and strobe signal of the same phase output from the circuit, and phase-shifts the input strobe signal by 90 degree in a 2nd phase shift circuit.

In the interface circuit according to the present invention, at the time of testing the output side circuit, in the output side circuit, the first phase shift circuit is set so that the phase difference between the data signal and the strobe signal is 90 degrees, and in the input side circuit, from the output side circuit. The outputted data signal of the same phase and the strobe signal are input, and the second phase shift circuit sets the phase shift of the input strobe signal to zero.

To practice the invention  Best form for

The present invention described above will be described with reference to the accompanying drawings to explain in more detail. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of one Embodiment of this invention. Referring to FIG. 1, a circuit according to an embodiment of the present invention is an interface circuit for exchanging data with a DDR SDRAM (not shown), and a phase shift circuit on the output side of data DQ and data strobe signal DQS. 20 has a function of switching the phase shift amount of the sampling clock of the output data DQ to 90 degrees or 180 degrees based on the phase switching control signal from the control circuit 10.

For example, during data output to the DDR SDRAM, the phase shift circuit 20 sets the phase shift amount of the sampling clock of the output data DQ to 90 degrees, and the phase of the sampling clock of the data strobe signal DQS. The shift amount is 180 degrees, and the DQS is delayed by 90 degrees from the DQ.

Even during the function test on the output side by the loopback test, the phase shift circuit 20 sets the phase shift amount of the sampling clock of the output data DQ to 90 degrees. In the phase shift circuit 20, the phase shift amount of the sampling clock of the data strobe signal DQS is fixed to 180 degrees. This delays the DQS by 90 degrees than the DQ.

During the input side functional test by the loopback test, the phase shift circuit 20 sets the phase shift amount of the sampling clock of the output data DQ to 180 degrees. In the phase shift circuit 20, the phase shift amount of the sampling clock of the data strobe signal DQS is 180 degrees. This outputs DQ and DQS of the same phase.

In addition, on the input side, the phase shift circuit 30 has a 90 degree phase shift with respect to the data strobe signal DQS input to the input buffer 17 based on the phase change control signal from the control circuit 10. It controls switching to 0 degree (no phase shift).

For example, during normal operation, the phase shift circuit 30 phase shifts the data strobe signal DQS from the DDR SRDAM by 90 degrees and outputs it to the sampling circuit 40. In addition, when the function test on the input side by loopback outputs DQ and DQS of the same phase from the output side and receives them from the input buffers 16 and 17, respectively, the phase shift circuit 30 phase shifts the DQS by 90 degrees. To the sampling circuit 40.

In the functional test on the output side by loopback, when DQS having a phase delay of 90 degrees from DQ and DQ is output from the output side, these are respectively received by the input buffers 16 and 17, and the phase shift circuit 30 receives the data strobe signal. The phase shift amount of (DQS) is set to 0 and output to the sampling circuit 40.

In addition, although not particularly limited, the control circuit 10 includes a pattern generator for generating pattern data, a checker for comparing the pattern data input to the loopback with an expected value, and a BIST (Built-In) for self-testing by loopback. Self Test) circuit.

Although not particularly limited, in FIG. 1, the data signal DQ and the data strobe signal DQS input to the latch circuits 12 and 13 are not shown memory controllers (not shown CPU) to which the interface is connected. Under the control of. Alternatively, DQ and DQS input to the latch circuits 12 and 13 may be output from the control circuit 10 at the time of testing.

The function test on the input side will be described. In order to test the phase shift circuit 30 on the input side, the sampling circuit 40 and the like, the phase shift circuit 20 on the output side outputs the phases of the data signal DQ and the data strobe signal DQS together. In this case, the clock for sampling the data signal DQ is shifted by 180 degrees and output in the same phase as the data strobe signal DQS. The latch circuits 12 and 13 respectively convert the data signal DQ and the data strobe signal DQS into sampling clocks of the same phase from the phase shift circuit 20 (the phases of which are all 180 degrees shifted from the input clock). After sampling, the data signal DQ and data strobe signal DQS of the same phase are returned from the output buffer 14 and the output buffer 15 to the input side, respectively, and the input buffer 16 and the input buffer 17 Are respectively inputted to the data strobe signal DQS, and the data strobe signal DQS is phase shifted by 90 degrees in the phase shift circuit 30, and the output buffers (s) are output from the sampling circuit 40 using the data strobe signal DQS which has been phase shifted by 90 degrees. The data signal DQ from 16 is sampled.

Next, the functional test on the output side will be described. To test the output side function, the control circuit 10 controls the phase shift circuit 30 so as not to phase shift the data strobe signal DQS on the input side. The amount of phase shift in the phase shift circuit 30 becomes 0 degree.

The phase shift circuit 20 on the output side sets the phase shift amount of the data sampling clock to 90 degrees, and the phase shift amount of the data strobe signal DQS is fixed to 180 degrees, so that the phase shift circuit 20 is fixed to 90 degrees in advance with respect to the data signal DQ. The phase-shifted data strobe signal DQS is output from the output buffer 15. The data signal DQ and data strobe signal DQS output from the output buffer 14 and the output buffer 15, respectively, are input to the input buffer 16 and the input buffer 17, respectively. The data strobe signal DQS output from the input buffer 17 is input to the phase shift circuit 30, but the phase is not shifted and is output to the sampling circuit 40. In the sampling circuit 40, the looped-back data signal DQ is sampled in response to the data strobe signal DQS phase-shifted 90 degrees in advance by the phase shift circuit 20 on the output side.

As described above, in the present invention, a mode without phase shifting is added to the phase shift circuit 30 to enable the loopback test of the phase function on the input side or the output side. For this reason, the high speed loopback test can be performed with an inexpensive low speed tester in the test of the interface of a phase where data and strobe differ in input and output like DDR. It demonstrates based on an Example below.

Example

Fig. 2 is a diagram showing the configuration of the semiconductor device of one embodiment of the present invention, and shows the configuration of the output side and the input side of DQ and DQS in the interface circuit of the DDR SDRAM. In Fig. 2, the BIST circuit 100 mounted in the circuit returns a PRBS (Pseudo Random Bit Sequence) generating circuit (pattern generator) 101 which generates a pseudo random binary sequence and returns from the output buffer to the input buffer in a loopback. A PRBS expectation matching circuit (inspector) 102 for comparing the input pattern with the expected pattern is provided to verify the loopback pass in the PRBS generating circuit 101 and the PRBS expectation matching circuit 102.

The selector 111 that receives data from the internal logic of the semiconductor device and the pattern data from the PRBS generation circuit 101 selects data from the internal logic of the semiconductor device during normal operation, and selects the data from the PRBS generation circuit during the test. A pattern from 101 is selected.

On the output side, the WDLL (Write Delay Lock Loop) 120 inputs a system lock signal (clk; also referred to as a "core clock") (the clock CK of the DDR SDRAM in Fig. 3 is input to the system lock signal clk). Synchronization), and the phase shift control signal from the BIST circuit 100 is received to control the phases of the sampling clocks of the data DQ and the data strobe signal DQS. Further, in response to the clock signal from the WDLL 120, a latch circuit 112 for sampling the data signal output from the selector 111 and an output of the latch circuit 112 are inputted to input / output terminals DQ of the data signal. An output buffer 114 output to 105, a latch circuit 113 for sampling the data strobe signal DQS in response to a clock signal output from the WDLL 120, and an output of the latch circuit 113; And an output buffer 115 for outputting to the input / output terminal DQS 106 of the data strobe signal. The data strobe signal DQS input to the latch circuit 113 is supplied from the controller side (not shown) during normal operation, but is generated and supplied to the selector (not shown) by the BIST circuit 100 during testing. It is good also as a structure to switch control by this.

The input side includes an input buffer 116 having an output terminal of the output buffer 114 and an input terminal connected to the terminal 105, an input buffer 117 having an output terminal connected to the output of the output buffer 115 and a terminal 106, and an input buffer 117. A read delay lock loop (RDLL) 130 for inputting the output of the input buffer 117, and a read in first out first 140 for sampling the output of the input buffer 116 with the output clock of the RDLL 130; And a MDLL (Master Delay Lock Loop) 150 for generating a basic phase adjustment signal with a clock clk as an input.

In the present embodiment, the DLL circuits of the WDLL 120 and the RDLL 130 are used as the phase shift circuits 20 and 30 of FIG. 1. The DLL circuit used in this embodiment can use any known circuit configuration in which the phase delay amount is selectable. For example, a delay circuit having a variable delay time of the output signal and a delayed input signal are fed back to the delay circuit. A phase comparator for comparing the phase with the input signal of and a phase comparator according to the phase comparison result of the phase comparator so that the phase of the output signal has a predetermined relationship (for example, 90 degrees, 180 degrees, or no delay), And a selection control circuit for variably controlling the delay of the output signal, such as selecting an output tap of the delay circuit. Any circuit configuration, such as a phase interposer, can be used as long as it is a circuit which can set the phase of a clock to a desired value.

The RDLL 130 switches by phase 90 degrees / 0 degrees based on the phase shift control signal from the BIST circuit 100. The adder of the RDLL 130 adds a basic phase adjustment signal (reference clock input to the RDLL) from the MDLL 150 and an RDLL phase fine signal (a signal for fine adjustment) set and input from the outside of the apparatus. Then, the phase shift amount is synchronously controlled in accordance with the addition result. When the phase shift amount is 0, the RDLL performs feedback control to output a signal having the same phase as the input signal.

An adder of the WDLL 120 adds a WDLL phase tone signal (a reference clock input to the WDLL) and a basic phase adjustment signal.

The operation of this embodiment will be described with reference to FIG. First, the normal operation will be described.

When writing normal operation, the selector 111 selects data from internal logic. The WDLL 120 outputs the phase shifted by 90 degrees as a clock for a data sample. The WDLL 120 phase shifts 180 degrees and outputs it as a clock for a DQS sample. In normal operation, the write data signal DQ and the data strobe signal DQS phase shifted by 90 degrees with respect to the write data signal DQ are supplied to the DDR SDRAM.

In addition, during readout of normal operation, data signals (lead data; DQ) and data strobe signals (DQS) of the same phase are input to the input buffer 116 and the input buffer 117 from the DDR SDRAM, respectively. . The RDLL 130 phase shifts the data strobe signal DQS output from the input buffer 117 by 90 degrees, and the read FIFO 140 uses the data strobe signal from the RDLL 130 as a sampling clock to read data. Sample. The sampled data is supplied to a CPU (not shown) via a controller (not shown).

Next, the operation of the loopback test by the BIST circuit 100 will be described.

When performing the function test on the input side, in order to test the 90 degree shift function of the RDLL 130 on the input side and the function of the read FIFO 140, the BIST 100 outputs a phase shift control signal to the WDLL 120, The WDLL 120 controls to output the phases of the data DQ and the data strobe signal DQS together.

Specifically, in the WDLL 120, the phase of the DQS is 180 degrees (180 degrees with respect to the clock), and the phase of the DQ is 180 degrees. And the BIST circuit 100 supplies a phase switching control signal to the RDLL 130, and makes the phase shift of the RDLL 130 90 degrees. The DQ / DQS of the same phase is input to the input buffers 116 and 117 from the output buffers 114 and 115, respectively, and to the read FIFO 140 with a clock shifted by 90 degrees with the DQS to the RDLL 130. Is sampled. The PRBS expectation matching circuit 102, which has received data from the read FIFO 140, compares with the expectation pattern and outputs a pass if it matches.

In addition, when performing a functional test on the output side, the BIST circuit 100 outputs a phase shift control signal to the RDLL 130, sets the phase shift of the RDLL 130 to 0 degrees, and strobes the data strobe from the input buffer 117. Do not phase shift the signal DQS. The data strobe signal DQS phase shifted 90 degrees with respect to the data signal DQ on the output side in advance is looped back to the input side and sampled to the read FIFO 140.

In addition, the switching in the output side and the input side of the phase shift amounts of DQ and DQS described in the above embodiments is merely an example, and the present invention is not limited to this configuration. For example, although the phases of both DQ and DQS are output 180 degrees with respect to the clock CLK on the output side, the phases are output together, but may be set to the same phase A (but A> 90) other than 180 degrees. In this case, in the WDLL 120, the phase shift amounts of the clocks for sampling the data DQ are switched between A-90 and A. FIG.

According to the present embodiment, the phase shift function and the mode without phase shift are added to the WDLL 120 which performs the phase shift, and the loopback test of the phase function only on the input side or the output side is made possible. For this reason, a high speed loopback test can be performed using an inexpensive low speed tester in the test of an interface of a phase where data and strobes differ in input and output, as in DDR SDRAM. In addition, when performing a fast loopback test of an interface using a tester with a low test rate, the clock supplied from the tester is tested on the tester's load board because the operating frequency of the interface as the device under test (DUT) is high. The multiply circuit mounted on the jig may be frequency multiplied and then supplied to the interface as the device under test (DUT).

In the above embodiment, on the output side, the phase shift amount of the data strobe signal DQS is fixed to 180 degrees, and the phase shift amount of the data DQ is switched to 90 degrees or 180 degrees. The phase shift amount may be fixed at 90 degrees, and the data strobe signal DQS may be switched at 90 degrees or 180 degrees. In the above embodiment, the configuration of switching the phase shift amount of the data strobe signal DQS to 90 degrees or 0 degrees in the RDLL on the input side is not limited to this configuration. For example, the phase shift amount of the data strobe signal DQS may be set to the fixed value A (A> 90), and the phase shift amount of the data signal may be set to A-90 or A.

In the above embodiment, the interface circuit of the DDR SDRAM in which the phases of the DQ and the DQS are the same at the time of reading and the phase difference between the DQ and the DQS at the time of writing is described as an example, but the present invention is limited to the interface of the DDR SDRAM. no. In other words, the same applies to any case where the phase of the strobe signal that defines the sample timing of the data in the opposing device differs between the input and the output (other than input: 0 degrees, output: 90 degrees). Can be. 1 may be selected from two or more phase shift amounts in the phase shift circuit 20 of FIG. 1, and one may be selected from two or more phase shift amounts in the phase shift circuit 30. .

As mentioned above, although this invention was demonstrated based on the said Example, this invention is not limited only to the structure of the said Example, Of course, it includes the various deformation | transformation and correction which a person skilled in the art can make within the scope of this invention.

According to the present invention, in an interface where a phase relationship between data and a strobe signal for sampling the data is different at an input and an output, such as an interface of a DDR SDRAM, a loopback test by adjusting the phase of the data and the strobe signal of the input and output. To make it possible.

Claims (10)

An input and output of a data signal and a strobe signal defining a timing of sampling of the data signal, wherein a phase relationship between the data signal and the strobe signal is different in input and output as an interface circuit; On the side outputting the data signal and the strobe signal, at least one phase shift amount of the output data signal and the output strobe signal is varied based on the input phase shift control signal, and the output data signal and the strobe are output. Circuitry for switching control of a phase difference between signals; And On the side of inputting the data signal and the strobe signal, at least one phase shift amount of the input data signal and the input strobe signal is varied based on the phase shift control signal, so that the input data signal and the strobe signal are changed. Interface circuit characterized by comprising a circuit for switching the phase difference between the control. An input and output of a data signal and a strobe signal that defines the timing of sampling of the data signal are performed, and a phase relationship between the data signal and the strobe signal is different in input and output as an interface circuit. An output side circuit which outputs the data signal and the strobe signal selects one of at least two phase shift amounts based on the input phase shift control signal to phase shift the data signal, and predetermines the strobe signal. A first phase shift circuit for phase shifting by a true phase shift amount; A second phase shift circuit for inputting the data signal and the strobe signal to phase shift the inputted strobe signal by selecting one of at least two phase shift amounts based on the phase shift control signal; ; And And a sampling circuit for sampling the input data signal in response to the strobe signal output from the second phase shift circuit. The method of claim 2, The first and second phase shift circuit, During the writing and reading of the normal operation, the phase shift amounts defined in correspondence with the predetermined phase relationship between the output and the input of the data signal and the strobe signal are respectively selected, In the test, the phase shift amount specified in the phase shift control signal is selected in accordance with the test contents, and the data in the input side circuit is looped back to the input side circuit of the data signal and the strobe signal from the output side circuit. And the phase relationship between the signal and the strobe signal operates correctly and / or whether the phase relationship between the data signal and the strobe signal in the output side circuit operates correctly. The method of claim 2, In the writing of the normal operation, in the output side circuit, the first phase shift circuit phase shifts the data signal so that the phase between the data signal and the strobe signal is a first predetermined value, In the reading of the normal operation, in the input side circuit, the second phase shift circuit phase shifts the input strobe signal to the first value and outputs it to the sampling circuit, In the test of the input side circuit, in the output side circuit, the first phase shift circuit sets the phase of the data signal and the strobe signal to the same phase, and in the input side circuit, the same output from the output side circuit. Inputting a data signal of a phase and a strobe signal, and said second phase shifting circuit phase shifting said strobe signal to said first value and outputting it to said sampling circuit. The method according to claim 2 or 4, In the test of the output side circuit, in the output side circuit, the first phase shift circuit sets the phase between the data signal and the strobe signal as the first value, and in the input side circuit, the second phase shift. And the circuit sets the amount of phase shift of the input strobe signal to zero. The method of claim 2, The data signal and the strobe signal are data signals and data strobe signals of DDR SDRAM, In the writing of the normal operation, in the output side circuit, the first phase shift circuit is set so that the phase difference between the data signal and the strobe signal is 90 degrees, In the reading of the normal operation, in the input side circuit, the second phase shift circuit phase shifts the phase of the input strobe signal by 90 degrees and outputs it to the sampling circuit, In the test of the input side circuit, in the output side circuit, the first phase shift circuit makes the phase of the data signal and the strobe signal the same phase, and in the input side circuit, the same phase output from the output side circuit. Inputting a data signal and a strobe signal, wherein the second phase shift circuit phase shifts the input strobe signal by 90 degrees. The method according to claim 2 or 6, In the test of the output side circuit, in the output side circuit, the first phase shift circuit is set so that the phase difference between the data signal and the strobe signal is 90 degrees, and in the input side circuit, the output from the output side circuit is performed. Inputting a data signal of the same phase and a strobe signal, and said second phase shifting circuit sets the phase shift of said inputted strobe signal to zero. The method of claim 2, And at least one of said first and second phase shift circuits comprises a delayed synchronization loop circuit. The method of claim 2, A pattern generation circuit for generating a test pattern, and during the test, the test pattern from the pattern generation circuit is phase shifted as the data signal and looped back from the output side circuit to the input side circuit, And a matching circuit for inputting data sampled by the sampling circuit of the input side circuit and comparing with the expected value pattern. The semiconductor device provided with the interface circuit in any one of Claim 1, 4, 6, 8, 9.

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