KR20070022351A - Field effect transistors fabricated by wet chemical deposition - Google Patents

Abstract

The present invention provides a field-effect transistor and a method of depositing on a substrate 480 to fabricate a field-effect transistor, the method comprising wet chemical vapor deposition of a reacting material to form a semiconductor material. Deposited materials include cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury. The wet chemical deposition may be performed by chemical bath deposition or spray pyrolysis. No vacuum deposition method is necessary.

Description

Field effect transistor manufactured by wet chemical vapor deposition {FIELD EFFECT TRANSISTORS FABRICATED BY WET CHEMICAL DEPOSITION}

The present invention relates to field-effect transistors and their production methods.

Field-effect transistors, particularly thin film field-effect transistors (TFTs), have a wide variety of applications and potential uses in such fields as display or storage technology.

Some of the methods for producing thin film transistors are known in the art, for example in GB-A-2044994.

Epitaxial growth of cadmium sulfide on indium phosphide monocrystals with chemical vapor deposition from cadmium ammonia-thiourea aqueous solution is "epitaxial growth on cadmium sulfide layer on indium phosphide from aqueous ammonia solution" by D Lincort, R Ortega-Borges And M Froment, Appl. Phys. Lett., 64 (5), 1995, 569. The materials produced in this way can be used for optoelectronic applications.

US-A-4360542 describes a photovoltaic cell manufacturing method wherein cadmium sulfide is deposited as a thin film on a stable substrate by thermal decomposition of a cadmium ammonia thiocyanate composite aqueous ammonia solution.

Fabrication of thin film transistors comprising thin semiconductor films of CdS or CdS using low temperature chemical bath decomposition methods is described, for example, in "Preparation of Thin Film Transistors with Chemical Bath Decomposed CdSe and CdS Thin Films", FY Gan and I Shih, IEEE Trans. Electron Devices. 49 (2002), 15.

The use of chemical bath deposition techniques for the deposition of CdS, CdSe, ZnS, ZnSe, PbS, SnS, Bi ₂ S ₃ , Bi ₂ Se ₃ , Sb ₂ S ₃ , CuS and CuSe thin films has been described as "for applications related to solar energy. Semiconductor thin films by chemical bath decomposition ”, solar energy materials and solar cells, such as PK Nair, 52 (1998), 313-344. In the method described in this publication, a semiconductor thin film is deposited on a substrate immersed in a dilute solution containing a metal ion and a source of hydroxide, sulfide or selenide ions. Chemical bath deposition techniques are known to be well suited for producing large areas of thin films for solar energy related applications.

Chemical bath deposition of indium sulfide is also described in "Chemical Bath Deposition of Indium Sulfide Thin Films: Fabrication and Features", Thin Solid Film 40 (1999) 18, CD Lokhande, A. Ennnaoui, PS Patil et al.

US-A-5689125 describes a semiconductor device comprising a boundary layer of cadmium sulfide (CdS). The boundary layer is produced using chemical bath deposition at 30-90 ° C. using ammonium hydroxide, hydride cadmium sulfide (3CdSO ₄ 8H ₂ O) and thiourea solution.

Such conventional methods using chemical bath deposition require that techniques such as lithography and etching be involved to remove deposition material from areas of the substrate that are not generally required. It would be advantageous to provide a method of depositing a semiconductor material such as CdS that does not need to use such a subtraction step. Applicant has developed such a method.

The deposition of indium sulfide, In ₂ S ₃ by chemical spray pyrolysis to produce conductive films for optoelectronic and photovoltaic applications has been described in "Characteristics of Spray Pyrolyzed Indium Sulfide Thin Films", TTJohn, S. Bini, Y. Kashiwaba et al. , Semicond. Sci. Technol . 18 (2003) 491.

Indium tracks can be transformed into In ₂ S ₃ by heat treatment in a flow stream of H ₂ S {J. Herrero and J. Ortega Sol. Energy Mater 17 (1988) 357}.

In displays based on polymer electronics, the starting material pentacene is currently used as a semiconductor. A mobility of about 0.02 cm 2 / Vs limits the size of the display to about QVGA (typically 320 x 240 pixels). As semiconductor mobility increases, the refresh rate needs to be increased and / or increased in size to VGA (720 x 400 pixels) size and SVGA (800 x 600 pixels) size.

In commercially available active matrix liquid crystal displays, amorphous hydrated silicon is used as the semiconductor. The process is by standard semiconductor techniques such as vacuum deposition followed by lithography and etching. Conventional deposition techniques of active and high mobility semiconductor materials require the use of vacuum techniques. For cost and efficiency reasons, manufacturing processes that do not require vacuum deposition are preferred.

The list or description of documents previously published herein is not necessarily to be taken as an admission that the documents are part of common technical knowledge or common knowledge.

The present invention provides a method for manufacturing a semiconductor, in particular a field-effect transistor, wherein the semiconductor material is deposited on a substrate by wet chemical vapor deposition or spray pyrolysis.

The method of the invention is particularly suitable for depositing cadmium sulfide or indium sulfide on a substrate.

In one embodiment, this method is:

(Iii) providing a solution comprising a bond of a compound that reacts to form a material having semiconductor properties or a material having semiconductor properties;

(Ii) applying a drop of the solution onto a substrate;

(Iii) heating the product of step (ii) to a temperature of 50-90 ° C .;

(Iii) rinsing the product of step (iii); And

(Iii) heating the product of step (iii) to a temperature of from 50 to 200 ° C.

As used herein, the term " material having semiconductor properties " includes materials in which the electrical conductivity is intermediate between the metal and the insulator, the conductivity of which changes with temperature and is exposed to the presence of impurities and / or light The case changes in the presence of an electric field. In general, the conductor has a resistivity of less than 10 ⁻⁵ mA at about 25 ° C. atmospheric pressure. In general, semiconductors have a resistivity in the range of 10 ⁻⁵ mA to 10 ⁸ mA at 25 ° C. atmospheric pressure. In general, the insulator preferably has a resistivity of at least 10 ⁸ mA at 25 ° C. atmospheric pressure.

The material having semiconductor properties can be any material having semiconductor properties suitable for use in field-effect transistors. The method of the present invention is particularly suitable for the deposition of semiconductor materials that can be deposited using chemical bath deposition techniques. Chemical bath deposition techniques are described, for example, in US Pat . No. US-A-5689125, Lincott et al. , Appl. Phys Lett . 64 (5), 31 January 1994, described in Nair et al., Solar Energy Materials and Solar Cells , 52 (1998), 313-344 and Gan and Shih, Transactions on Electronic Devices , Vol. 49, No. 1, January 2002. It is.

Materials having semiconductor properties used in the present invention preferably include at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper and mercury. Preferably the material with semiconductor properties comprises cadmium or indium.

Materials having semiconductor properties used in the present invention preferably include at least one of sulfur, selenium and tellurium. Preferably the material having semiconductor properties comprises sulfur.

Those skilled in the art will appreciate that other materials having semiconductor properties may be used in the methods of the present invention.

Preferably the combination of the reacting compounds to form a material having semiconductor properties is used in step (iii). Bonds suitable for use in the present invention include mixtures including mixtures comprising at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper and mercury. Preferably cadmium or indium comprising a mixture is used.

If the mixture is used in step (a), it is followed by reaction of a suitable starting material, including cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury, with a suitable material for forming the mixture. ) May be obtained before. Preferably halogen salts such as cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury chloride salts or acetates of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury may be used. have.

Other starting materials that can be used to prepare cadmium, including mixtures, include cadmium halogen compounds such as cadmium chloride, CdCl ₂ and dialkyls such as Cd (carboni-6 alkyl) ₂ . As will be appreciated by those skilled in the art, materials which combine the corresponding zinc, lead, tin, bismuth, antimony, indium, copper and mercury can be used to obtain mixtures of these materials. The use of chloride salts is particularly preferred.

Those skilled in the art will readily be able to determine which materials are suitable for forming mixtures with the starting materials described above. Any suitable material can be used. Suitable materials include, but are not limited to, ammonia, triethanolamine, citric acid and ethylenediamine. Preferably a solution containing ammonia is used. The use of ammonia is particularly preferred because it is easy to remove after the reaction process if necessary. In a preferred aspect, the mixture is obtained by mixing ammonia solution with a chloride solution such as cadmium or indium chloride.

Suitable concentrations of the ammonia solution are 1-5M, for example about 2M. Suitable concentrations of cadmium chloride solution are 10 × 10 ⁻³ to 20 × 10 ⁻³ M, for example about 16 × 10 ⁻³ M. Those skilled in the art will appreciate that alternatively similar concentrations of other mixtures forming the material may be used.

Preferably, the mixture forming the material is chosen such that the solution used in the step comprises very low concentrations of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury. This is believed to reduce uniform precipitation on the substrate and allow for uneven deposition of deposits on the substrate.

Preferably the mixture is an amine mixture. Particular ^preference is given to the use of tetraamine cadmium mixtures, Cd (NH ₃ ) ₄ ²⁺ . The tetraamine cadmium mixture, Cd (NH ₃ ) ₄ ²⁺ , can be obtained using any conventional manner, for example by reaction of ammonia solution with cadmium acetate. Preferably, the tetraamine cadmium mixture, Cd (NH ₃ ) ₄ ²⁺ is obtained by mixing a solution of cadmium halide such as cadmium chloride with ammonia solution.

The present invention has surprisingly been found to be of significant advantage in connection with the use of halide salts such as chloride salts as opposed to acetate in the formation of the mixture used in the step under certain circumstances. It has been found that when a material made using a mixture derived from cadmium acetate is exposed to ambient light, a potentially unacceptable decrease in continuous photocurrent and current modulation may occur in some situations. This effect is generally not seen when cadmium chloride is used as starting material. Without wishing to be bound by theory, the inventors believe that when cadmium chloride is used, a small amount of chloride is bonded while substituting CdS latex. This is believed to have the effect of lowering the Fermi level just below the conduction band to prevent the generation of continuous photocurrent.

The comparison of FIGS. 1 and 2 shows the effect of using cadmium chloride rather than cadmium acetate. As shown in FIG. 1, exposure of a material produced using cadmium acetate to ambient light results in a continuous photocurrent at room temperature for several weeks and degrades the modulation of the current. 2 shows that when a material produced using cadmium chloride is placed in a dark place after receiving ambient light, the photocurrent disappears almost immediately.

Preferably the bond used in step (iii) comprises a source of at least one of sulfur, selenium and tellurium ions. Any suitable source of sulfur ions can be used. Any suitable source of sulfur ions binds but is not limited to thiourea or thioacetamide. The concentration of the source of sulfur ions, for example thiourea, is preferably 25 × 10 ⁻³ to 40 × 10 ⁻³ M, for example about 32 × 10 ⁻³ M. Any suitable source of selenium ions can be used. Suitable sources of selenium ions include but are not limited to sodium selenium sulfide. Any suitable source of tellurium ions can be used. Those skilled in the art will appreciate that the concentration of a suitable source of selenium ions or tellurium ions may be similar to the source of sulfur ions described above.

Of the material having a low concentration to the semiconductor properties of the material, such as a ^- Ideally, the source of sulfur, selenium and tellurium ions used should provide a slow release of the sulfur, selenium and tellurium ions, free end HS ^- and S2 This results in the prevention of uniform extraction.

Optionally, the material having semiconductor properties can be doped. Suitable dopants are known in the art.

The deposition step, step (ii) may occur at any suitable temperature. The most suitable temperature will depend on factors such as the nature of the substrate and the nature of the material to be deposited. Those skilled in the art will be able to readily determine suitable temperatures. The process of the present invention is particularly suitable for use with compositions wherein the optimum chemical bath deposition temperature is about 60-70 ° C. The solution to be deposited can thus be heated to this temperature prior to deposition. Alternatively, the solution may be present at a relatively low temperature, for example 0 to 35 ° C., for example at ambient temperature (about 15 to 30 ° C.), for example 20 to 25 ° C. and the substrate at a higher temperature. For example, at a temperature of 50 ° C. or higher, such as 60 to 70 ° C. If a heated substrate is used, the temperature of the material deposited on the substrate will quickly increase to a temperature similar to that of the substrate due to the small size deposited drop by drop.

Any suitable method of depositing a drop of the solution on the substrate can be used in step (ii). Suitable materials include, but are not limited to, inkjet printing, dispensing and use of aerosols in combination with electric fields.

Any suitable substrate known for use in the manufacture of field-effect transistors can be used. The properties of the substrate will depend at least in part on the desired final structure of the field effect transistor. The substrate may be an insulator or may have conductive properties.

In one aspect of the invention, a substrate may also be used that can act as a gate electrode. Substrates suitable for use in this aspect include doped silicon wafers. Such wafers generally include a SiO ₂ layer thermally grown on their top surface. The SiO ₂ layer is generally about 200 nm thick and has a capacity of about 17 nF / cm 2.

The test substrate may comprise any suitable source and drain electrodes, for example Au / Ti source and drain electrodes. Such source and drain electrodes can be made by methods known in the art. Suitable methods include standard photolithography on deposited metal films { Synthetic , such as field-effect transistors made from solution treated organic semiconductors, AR Brown et al. Metals , 88 (1997) 37-55}.

Alternatively, a polymer test substrate can be used. If a polymer substrate is used, the substrate can be flexible. Such substrates are described in Nature Materials , 2004, 3 (2), pages 106-110, “Flexible Active-Matrix Display and Shift Resistant Mainly Solution Solutioned Organic Semiconductors”, GHGelinck et al . Such substrates include a support with a foil on top, a planar layer, gold structured like a gate electrode, a commercially available epoxy-based negative resistor SU8, such as a gate insulator, polymers such as SU8, and gold sources and drains in general. An electrode. Materials disclosed as gate dielectrics in US Patent No. 6,635,406, incorporated herein by reference, may be used in embodiments of the present invention. Such materials include polyvinylphenols (e.g. PVPs exposed to a flood exposed to UV), polyglutimides, polyimides, as well as commercially available polyepoxy based photoresists such as SU8. Hard-baked, a conventional photoresist comprising polymers such as polyvinylalcohol, polyisoprene, polyepoxy-based resins, polyacrylates, polyvinylpyrrolidone, p-hydroxystyrene polymers, and melamine polymers Hard-baked novolacs. Commercially available novolac photoresists that may be suitable for use in the practice of the present invention include HPR 504. The gate insulator can generally comprise an organic insulating polymeric compound that can be crosslinked using a crosslinking agent. There is no restriction on the choice of polymeric insulator. Polyvinylphenol and polyvinyl alcohol have been known as suitable insulating polymeric materials, of which polyvinylphenol is more preferred. Suitable crosslinkers include aminoplasts such as hexamethoxymethylmelamine (HMMM).

Silicon dioxide (SiO ₂ ) may be used as the gate insulator. If SiO ₂ is used as the gate insulator, SiO ₂ may be primed. An example of a primed substrate suitable for use in the present invention is a substrate primed with hexamethyldisilazane and comprising a silicon dioxide gate insulator. Such primed substrates may be obtained by gas phase reaction of hexamethyldisilagen with the surface of the substrate, for example providing a monolayer of hexamethyldisilagen on the surface of the substrate. If necessary, the primer can be removed by spraying nitric acid or by plasma or UV / ozone treatment.

The size of the droplets deposited in step (ii) will depend on factors such as the deposition method used, the wettability of the surface of the substrate and the droplets or spreads on the substrate, which will depend on factors such as the surface tension of the solution.

In step (iii), the product of step (ii) is generally 50-90 ° C., preferably 60-85 ° C., more preferably 65-80 ° C. and most preferably 70-75 ° C., for example about Heated at a temperature of 70 or about 75 ° C. Step (iii) is generally carried out for less than 1 hour, preferably less than 30 minutes, more preferably less than 10 minutes, for example about 5 minutes. The time for which step (iii) is performed will depend on factors such as concentration, composition and temperature of the deposited solution.

Any suitable heating method can be used in step (iii). For example, the substrate may be located on a hot plate. Preferably the substrate is applied to prevent evaporation during the step. It is preferable to apply the substrate during the heating process because evaporation changes the composition of the droplets, for example as the pH decreases, which affects the properties of the semiconductor layer.

Without wishing to be bound by theory, the heating step results in the formation of a material having semiconductor properties on the surface of the substrate.

In step (iii), the product of step (iv) is rinsed. Preferably demineralized water is used in this step. The product of step iii can be rinsed for any suitable time for 1 to 10 minutes, such as about 5 minutes.

As used herein, the term desalted water refers to water from which minerals and / or salts have been removed.

Step (iii) is generally carried out at a temperature of from 50 to 200 ° C, preferably from 120 to 180 ° C, more preferably from 140 to 160 ° C, for example about 150 ° C. Generally step (iii) is carried out for 1 to 3 hours, preferably for about 2 hours. Step (iii) can be carried out under any suitable atmosphere, for example atmospheric pressure or vacuum. Preferably step (iii) is carried out under vacuum. If the step is not carried out under vacuum, any suitable pressure, for example from 1 × 10 ⁻⁴ Mbar to atmospheric pressure may be used.

The present invention also provides a field-effect transistor obtainable by the method described above. Optionally, the transistors of the present invention may include source and / or drain electrodes comprising noble metals. Suitable precious metals include, but are not limited to, gold, silver, platinum and palladium. Since they are not easily oxidized, it is advantageous to use electrodes comprising at least one such metal. Preferably the precious metal is gold. Alternatively, other high work function electrodes can be used, such as electrodes comprising conductive polymers such as ITO or PEDOT (poly (3,4-ethylene dioxythiophene)) or PANI (polyaniline). PEDOT can also be used, for example, in the form of PEDOT / PSS (poly (3,4-ethylene dioxythiophene) stabilized with polystyrenesulphonic acid). PANI can be used in the form of PANI-CSA (polyaniline doped with camphorsulphonic acid).

Compared to methods known in the art, including acidification steps such as lithography and etching, the method of the present invention has the significant advantage that the number of process steps is reduced and the amount of waste produced is reduced.

CdS is used as a highly mobile semiconductor in research, but the major drawback when using CdS on an industrial scale is the toxicity of cadmium. By replacing cadmium with, for example, indium, this disadvantage can be avoided.

In another embodiment, this method is

(Iii) providing a solution comprising a bond of a compound that reacts to form a material having semiconductor properties or a material having semiconductor properties;

(Ii) heating the substrate to 220-450 ° C .; And

(Iii) depositing a drop of the solution on the substrate by spray pyrolysis during deposition to a temperature between 220 and 370 ° C.

The substrate may be a very doped silicon wafer or undoped silica or glass or any other material suitable for deposition temperature and polymer materials that do not decompose or deform at deposition temperatures or suitable for use in metal oxide semiconductors.

The substrate may be annealed under vacuum at about 150 ° C. to improve contact between the source / drain and the semiconductor film.

The combination of compounds suitable for spray pyrolysis and capable of reacting to form materials having semiconductor properties can be, for example, halide salts of indium or cadmium, in particular chloride salts, sources of sulfur ions and sources of oxygen.

Indium sulfide, In ₂ S ₃ may be deposited by chemical spray pyrolysis. In one experiment, 1.5 ml of spray solution containing 0.1 M InCl ₃ and 0.15 M CS (NH ₂ ) ₂ is sprayed onto the substrate at a rate of about 1 ml / min. The temperature of the substrate is 300 ° C. 6 shows the linear and saturation transfer characteristics of the device where the drain bias is measured at 2 and 20V, respectively. The mobility shown in FIG. 6 is as high as about 4 cm 2 / Vs. More optimal mobility is shown in the table below. Mobility is expected to be even more optimized.

1 illustrates the linear transfer characteristics of a CdS field-effect transistor after exposure to ambient light. Curve 100 is the transmission characteristic of ambient light. Curves 101-106 are propagation characteristics for various time periods in the dark. The transistor was produced using cadmium acetate in a chemical bath deposition process as described in the prior art. The photocurrent lasted for several weeks at room temperature.

2 shows the linear transfer characteristics of a CdS field-effect transistor after exposure to ambient light. The transistor was produced using cadmium chloride in a chemical bath deposition process as described in the prior art. Curve 200 is the transmission characteristic of ambient light. Curve 201 is a transmission characteristic in the dark. Curves for various time periods appear in the dark. When the transistor is placed in the dark, the photocurrent disappears almost immediately. The internal figure shows the threshold voltage as a function of time T.

3 shows the linear and saturation transfer characteristics of locally deposited CdS field-effect transistors obtained by the method described in Example 1 and using a gold source and drain contact with a channel length of 40 μm and a channel width of 1000 μm. The figure shown. The right y-axis is mobility (cm 2 / V _s ).

4 is a view showing a sprayer for spray pyrolysis.

5A shows a cross-sectional view of a field effect transistor test substrate.

5B shows a front view of a field effect ring transistor test substrate.

6 shows linear and saturation transfer characteristics and induced mobility values for In ₂ S ₃ field-effect transistors.

7 is a diagram illustrating output characteristics of an In ₂ S ₃ field-effect transistor.

The invention is illustrated by the following non-limiting examples.

Example 1 Fabrication of Transistors by Selective Deposition of CdS on Substrates

Test substrates of highly doped silicon wafers with silicon oxide thermally grown (about 100 nm) on top were used. Gold electrodes (with titanium adhesion layers) are formed on the oxide layer using a combination of evaporation and lithography.

1 ml of 2.5 M CdCl ₂ solution in water was added to the 2 M ammonia solution. After the initial precipitation, a clear solution comprising Cd (NH ₃ ) ₄ ²⁺ is obtained. To this solution was added 3 ml of a 1.75 M thiourea solution in water. The substrate was heated to 70 ° C. The resulting drop of solution was deposited on the test substrate using a syringe.

The substrate was placed on a hotplate at 75 ° C. and applied with Petri-Dish to prevent evaporation. After 5 minutes, the substrate was rinsed with demineralized water and then heated to 150 ° C. for 2 hours under vacuum.

The silicon wafer was used as the gate voltage, where two gold electrodes were the source and drain electrodes (contacted using a micromanipulator). The transistor was characterized using an Agilent 4155c semiconductor parameter analyzer. The source drain voltage varies between 0 and 30 volts, preferably between 2 and 20 volts.

The transfer characteristics of the obtained transistors were measured. This is shown in FIG. 3.

Example 2-In on a substrate ₂ S ₃ Fabrication of Transistors by Deposition of

Experiments were initiated using spray pyrolysis for the deposition of indium sulfide. Spray pyrolysis is based on the evaporation of precursors near the heated substrate in a hotplate. Aerosols have been widely used as a material source for thin film deposition.

The deposition of the indium sulfide thin film was performed with a nebulizer 440 as in FIG. Carrier gas flow 470 is injected into the main tube of the nebulizer and exits the nebulizer through nozzle 450. Liquid 460 flows through the nozzle 450 that meets the carrier gas flow 470 and forms an aerosol. The aerosol is deposited on the substrate 480. The substrate 480 is heated by the hot plate 490. At the optimum flow rate, the solvent evaporates near the heated substrate surface. Wherein said solvent is water. The solvent may also be an alcohol, a mixture of water and alcohol (for example equal proportions of methanol and water), or may be another solvent, in particular an organic solvent. Generally the solvent is an oxygen source for the pyrolysis treatment. Wherein the carrier gas is argon but may be a gas that is substantially inert under these treatment conditions, such as other inert gases or nitrogen.

The precursor is absorbed on the substrate surface which is volatilized and heated near the substrate. Decomposition and / or chemical reactions then produce a high density indium sulfide film. To obtain a larger deposition area, the nebulizer rotates over the surface.

The spray solution comprises a mixture of thiourea {CS (NH ₂ ) ₂ } and indium chloride (InCl ₃ ) solutions in water. The pH of this solution is about 4. In some experiments, this pH is lowered to zero or two by the addition of HCl or acetic acid. The In / S ratio is varied by changing the molarity of the precursor. In most experiments, the total volume and rate of the sprayed solution are 1 ml and 1 ml / min and argon is used as the carrier gas. The hot plate temperature is varied between 300 and 450 ° C. Because of the cooling by the gas and liquid flows, the temperature of the substrate is lowered to about 80 ° C. The spray distance is maintained at 6 cm and the diameter of the rotating circle is about 3 cm. The ratio of indium to sulfur varies between 0.3 and 2. Particularly suitable electrical results are obtained at ratios between 0.9 and 1.04. At a ratio of 1.2 and above, a conductive film is formed. Table 1 summarizes some particularly relevant and representative results.

In / S ratio in solution pH In / S concentration (M) Flow rate (ml / min) Deposition Temperature (℃) Amount sprayed (ml) I _on / I _off Mobility (㎠ / Vs) Off current (pA) 1.04 4 0.1 / 0.104 0.73 270 1 ml 10 ⁷ 0.3 One 1.04 4 0.1 / 0.104 0.73 300 1 ml 10 ⁵ 0.1 One 1.04 4 0.1 / 0.104 0.73 330 1 ml 10 ⁶ One 10 1.04 4 0.1 / 0.104 0.73 360 1 ml 10 ⁴ 6 10000 One 0 0.1 / 0/1 0.73 270 1.4 10 ⁵ 0.6 50 One 0 0.1 / 0/1 0.73 300 1.4 10 ⁷ One One One 0 0.1 / 0/1 0.73 320 1.4 10 ⁶ 4 10 One 4 0.1 / 0/1 0.73 274 One 10 ⁶ 0.1 One One 4 0.1 / 0/1 0.73 327 One 10 ⁶ 0.5 One One 4 0.1 / 0/1 0.73 359 One 10 ⁴ 5 100

Electrical analysis

A thin-film transistor (TFT) test in which a nanocrystalline indium sulfide film consists of an N ⁺⁺ silicon wafer 510 with a thermal SiO ₂ 511 of 200 nm as a gate dielectric (capacitance 1.7 x 10 ^-8 F / cm 2) Deposited on the substrate (FIGS. 5A and 5B). At the top, gold contacts are patterned by photolithography to form source 512 and drain 513. The gate oxide, here 200 nm silicon dioxide film, is primed with hexamethyldisilagen (HMDS) resulting in a hydrophobic surface. The top contact 514 to the bottom gate is silver here. 5B is a front view of a field effect ring transistor test substrate, showing source 512 and drain 513 contacts.

The measurement is performed on a ring transistor having a channel length of 40 μm and a width of 1000 μm. Drain sweep (I _drain to V _drain at V _gate varying from -5 V to 20 V in 5 V steps) and gate sweep (I _drain to V _gate at V _drain = 2 V and 20 V) are measured. Forward gate bias sweep as well as backward gate bias sweep are measured for all drain voltages. The mobility used in this report is measured with the gate bias sweep at V _drain = 2V and V _gate = 20V. Current modulation is the ratio of drain current at V _gate = -20V and V _gate = 20V.

6 shows linear 61 (V _drain = 2V) and saturation 62 (V) of an In ₂ S ₃ field-effect transistor with a channel length of 40 μm and a channel width of 1000 μm using gold source and drain contacts. _drain = 20V) shows the delivery characteristics. The derived mobility value is represented by curve 63. The left y-axis is the drain current. The x-axis is the gate voltage. The right y-axis is mobility (cm 2 / V _s ). In / S ratio is 1.00.

7 is a graph of the output characteristics of an In ₂ S ₃ field-effect transistor with a channel length of 40 μm and a channel width of 1000 μm using gold source and drain contacts. The y-axis is the drain current. The x-axis is the drain voltage. The drain bias is swept from 0V to 20V and again the gate bias returns from 0V to 20V in 5V steps. The output curve shows that gold is an implant, not a Schottky contact.

Table 2 summarizes the X-ray fluorescence (XRF) test results of the compositions of indium and sulfide thin films from different In / S ratios in the precursor solution.

In and S compositions of In ₂ S ₃ thin films deposited with different In / S ratio precursor solutions Precursor sample Amount of In and S 10 ¹⁵ atoms / cm 2 In S In / S In / S = 0.7 39 51 0.76 In / S = 0.8 35 49 0.7 In / S = 0.9 27 39 0.71 In / S = 1 34 26 1.33 In / S = 1.04 41 50 0.82

In addition, the Rutherford white scattering spectrometer (RBS) technique was used to measure the amount of species such as In, S, Cl and O as shown in Table 3.

Compositions measured by RBS of thin films prepared with other sprayed solutions Precursor sample Amount of Species 10 ¹⁵ Atoms / ㎠ In / S ratio measured in thin film In S Cl O In / S = 0.7 24.3 33 5.4 4 0.74 In / S = 0.8 32.7 45 5.5 3 0.73 In / S = 0.9 37.6 49 6.7 6 0.77 In / S = 1 33.8 26 12.7 23 1.30 In / S = 1.04 39.5 46 8.5 10 0.86

These results are very similar to XRF analysis and demonstrate that a large amount of oxygen exists in the thin film at the In / S ratio of 1. It is further noted that a large amount of chloride is present in all the thin films, especially when the ratio is one. Surprisingly desirable electrical properties (current modulation is 7 decades and mobility 4.5 cm 2 / V _s ) are found when the In / S ratio is 1 in the precursors related to the higher content of chlorine and oxygen and the In / S ratio and ₂ S ₃ cube morphology was found when present.

The precursor may also be deposited by ink jet printing. Drops of the solution can be deposited and changed by heating the semiconductor. Residual liquid can be removed by rinsing. Alternatively, the nanoparticles of the metal can be deposited and subsequently cured by ink jet printing, resulting in H ₂ as described, for example, in Sol. Energy Mater 17 (1988) 357 by J. Herrero and J. Ortega. The semiconductor can be formed by heat treatment with a flow of S.

Finally, the discussion is intended only as an example of the invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the invention has been described in particular detail with respect to particular exemplary embodiments, it is understood that numerous modifications and changes can be made without departing from the broader and intended spirit and scope of the invention as set forth in the claims below. It should also be understood. The specification and drawings are, accordingly, to be regarded in an illustrative sense and are not intended to limit the appended claims.

When interpreting the appended claims,

(Iii) the term "comprises" does not exclude components or methods other than those listed in a given claim;

(Ii) singular expressions of components do not exclude the presence of a plurality of such components;

(Iii) any reference signs in the claims do not limit the scope of the claims; And

(Iii) It is to be understood that some “means” may be represented by the same item or structure or function performed.

As described in detail, the present invention is used in field-effect transistors and their production methods.

Claims (42)

As a method of manufacturing a field-effect transistor, (Iii) providing a solution comprising a material having semiconductor properties or a combination of compounds reacting to form a material having semiconductor properties; (Ii) depositing a drop of the solution onto a substrate; (Iii) heating the product of step (ii) to a temperature of 50-90 ° C .; (Iii) rinsing the product of step (iii); And (Iii) heating the product of step (iii) to a temperature of from 50 to 200 ° C, Method of manufacturing field-effect transistors. The method of claim 1, wherein the material having semiconductor properties comprises at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper, and mercury. Method of manufacturing field-effect transistors. The method of claim 2, wherein the material having semiconductor properties comprises cadmium, Method of manufacturing field-effect transistors. The method of claim 2, wherein the material having semiconductor properties comprises indium, Method of manufacturing field-effect transistors. The method of claim 1, wherein the material having semiconductor properties comprises at least one of sulfur, selenium, and tellurium, Method of manufacturing field-effect transistors. The method of claim 5, wherein the material with semiconductor properties comprises sulfur, Method of manufacturing field-effect transistors. The method of claim 1 wherein the bonding of the reacting compounds to form a material having semiconductor properties is used in step (iii). Method of manufacturing field-effect transistors. The method of claim 7, wherein the bond comprises a complex comprising at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper and mercury. Method of manufacturing field-effect transistors. The compound of claim 8, wherein the compound is an amine compound, Method of manufacturing field-effect transistors. 10. The method according to claim 8 or 9, wherein the composite is Cd (NH ₃ ) ₄ ^{2+ which is a} tetraamine cadmium compound or In (NH ₃ ) ₄ ²⁺ which is a tetraamine cadmium compound, Method of manufacturing field-effect transistors. 11. The method of any of claims 8 to 10, wherein prior to step (i) the composite is formed of a material suitable for forming the composite and cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury. Obtained by the reaction of a chloride salt or acetate, Method of manufacturing field-effect transistors. The method of claim 11, wherein the suitable material for forming the composite is ammonia solution, Method of manufacturing field-effect transistors. The method of claim 10, wherein before the step (iii), the tetraamine cadmium compound Cd (NH ₃ ) ₄ ²⁺ is obtained by mixing a cadmium chloride solution and an ammonia solution, Method of manufacturing field-effect transistors. The method of claim 7, wherein the bond comprises a source of at least one of sulfur, selenium and tellurium ions. Method of manufacturing field-effect transistors. The source of claim 14 wherein the source of sulfur ions is thiourea or thioacetamide. Method of manufacturing field-effect transistors. The method of claim 14 wherein the source of selenium ions is sodium selenosulfate, Method of manufacturing field-effect transistors. Obtainable by a method according to any one of claims 1 to 16, Field-effect transistors. 18. The method of claim 17, further comprising a source and / or drain electrode comprising a noble metal, Field-effect transistors. The method of claim 18, wherein the precious metal is gold, Field-effect transistors. In the method of manufacturing a field-effect transistor, (Iii) providing a solution comprising at least one compound that reacts to form a material having semiconductor properties or a material having semiconductor properties; (Ii) heating the substrate to a temperature in the range of 220-450 ° C .; And (Iii) depositing a drop of the solution on a substrate heated by spray pyrolysis,  Method of manufacturing field-effect transistors. 21. The material of claim 20, wherein the material having semiconductor properties comprises at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper, and mercury. Method of manufacturing field-effect transistors. The material of claim 20, wherein the material having semiconductor properties comprises at least one of sulfur, selenium, and tellurium, Method of manufacturing field-effect transistors. The method of claim 20, wherein the material having semiconductor properties comprises indium and sulfides, Method of manufacturing field-effect transistors. The method of claim 23, wherein the material having semiconductor properties comprises indium and sulfur in an atomic ratio of 0.7 to 1.33, Method of manufacturing field-effect transistors. The method of claim 24, wherein the material having semiconductor properties comprises indium and sulfur in an atomic ratio of 0.82 to 1.33, Method of manufacturing field-effect transistors. The method of claim 20, wherein the one or more compounds that react to form the material having semiconductor properties include at least one of cadmium, zinc, lead, tin, bismuth, antimony, indium, copper, or mercury, Method of manufacturing field-effect transistors. 27. The method of claim 26, wherein the one or more compounds that react to form a material having semiconductor properties include at least one of sulfur, selenium, and tellurium, Method of manufacturing field-effect transistors. 21. The method of claim 20, wherein the one or more compounds that react to form the material having semiconductor properties include indium and sulfur, and the atomic ratio of indium to sulfur in the one or more compounds that react to form the material having semiconductor properties is 0.3. To 1.2, Method of manufacturing field-effect transistors. 29. The method of claim 28, wherein the atomic ratio of indium to sulfur in the one or more compounds that react to form the material having semiconductor properties is in the range from 0.9 to 1.04. Method of manufacturing field-effect transistors. The method of claim 28, wherein the one or more compounds that react to form the material having semiconductor properties further comprise a source of oxygen and chlorine. Method of manufacturing field-effect transistors. 27. The method of claim 26, wherein the at least one compound that reacts to form a material having semiconductor properties prior to step (i) comprises at least one source of sulfur, selenium or tellurium ions with cadmium, zinc, lead, tin, bismuth, antimony Comprising compounds obtained by the reaction of chloride salts or acetates of indium, copper or mercury, Method of manufacturing field-effect transistors. 32. The method of claim 31 wherein the source of sulfur ions is thiourea or thioacetamide, Method of manufacturing field-effect transistors. A thin film transistor comprising indium sulfide. The method of claim 33, comprising a polymer substrate, Thin film transistor. 34. The semiconductor device of claim 33 further comprising a semiconductor film having an atomic ratio of indium to sulfur of 0.7 to 1.33. Thin film transistor. 36. The method of claim 35 wherein the atomic ratio of indium to sulfur in the semiconductor film is between 0.82 and 1.30, Thin film transistor. 34. The method of claim 33, comprising a semiconductor film having an atomic ratio of indium to sulfur of 0.7 to 1.33, wherein the semiconductor film further comprises oxygen and chlorine. Thin film transistor. As a method of manufacturing a field-effect transistor, (Iii) providing a solution comprising a combination of compounds having semiconductor properties and reacting to form a material comprising indium or a material having semiconductor properties; And (Ii) depositing a drop of the solution onto the substrate by ink jet printing, Method of manufacturing field-effect transistors. As a method of manufacturing a field-effect transistor, (Iii) providing a solution comprising an element capable of reacting to form a material having semiconductor properties; And (Ii) depositing an element on the substrate by inkjet printing on the substrate, Method of manufacturing field-effect transistors. 40. The method of claim 39, wherein the element is indium, Method of manufacturing field-effect transistors. The method of claim 39, wherein the element is in the form of nanoparticles, Method of manufacturing field-effect transistors. 40. The method of claim 39, wherein the element is cadmium, zinc, lead, tin, bismuth, antimony, indium, copper or mercury, Method of manufacturing field-effect transistors.

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