KR20070021502A - Bit line precharge power generation circuit - Google Patents

Abstract

The present invention relates to a bit line precharge power generation circuit for generating power applied to first and second bit lines of an open bit line structure, respectively. The circuit includes: a first bit line precharge power generation unit for generating power applied to the first bit line; A second bit line precharge power generation unit configured to generate power applied to the second bit line; A first power pad connected to the first bit line to selectively supply a first external power; And a second power pad connected to the second bit line to selectively supply a second external power.

Description

Bit line precharge power generation circuit {BIT LINE PRECHARGE POWER GENERATION CIRCUIT}

1 is a schematic diagram illustrating a structure of a bit line power supply wiring for applying stress between a bit line, a cell, and a plug according to a conventional example.

2 is a schematic diagram illustrating a structure of a bit line power supply wiring for applying stress between a bit line, a cell, and a plug according to another exemplary art.

2A is a circuit diagram of a first bit line precharge power generation unit according to another example of the related art.

2B is a circuit diagram of a second bit line precharge power generation unit according to another example of the related art.

2C is a circuit diagram of a bit line precharge power connection controller according to another exemplary embodiment of the prior art.

2D is a table illustrating an operation of a memory bit line precharge power generation circuit according to another conventional example.

2E is a waveform diagram illustrating an operation of a memory bit line precharge power generation circuit according to another example of the related art.

Figure 3 is a schematic diagram showing the structure of the bit line power supply wiring for applying stress between the bit line, cell, and plug according to the present invention.

3A is a circuit diagram of a first bit line precharge power generation unit according to the present invention;

3B is a circuit diagram of a second bit line precharge power generation unit according to the present invention;

3C is a circuit diagram of a bit line precharge power connection controller according to the present invention;

3D is a table illustrating operation of a memory bit line precharge power generation circuit in accordance with the present invention.

3E is a waveform diagram illustrating operation of a memory bit line precharge power generation circuit in accordance with the present invention.

Explanation of symbols on the main parts of the drawings

3100: memory cell array 3200: bit line precharge power generation circuit

3210: first bit line precharge power generation unit

3220: second bit line precharge power generation unit

3230: bit line precharge power connection control unit

3240,3250: Power Pad

The present invention relates to a bit line precharge power generation circuit for generating a power applied to a bit line.

In general, it is known that the probability of failure of a semiconductor device is the highest occurring within an initial 1000 hours, and thereafter, it is almost constant until the life of the semiconductor device is reached. In semiconductor production, burn-in processes undergo accelerated life tests under harsher conditions than typical service environments (eg temperatures of 125 ° C and voltages above the operating voltage). By detecting the initial failure of the device faster than the environment, it is performed to detect potential failures that may occur after shipping.

1 is a schematic diagram illustrating a structure of a bit line power supply wiring for applying stress between a bit line, a cell, and a plug according to a conventional example, and particularly, a memory cell having a folded bit line structure. An array 1100 and a bit line precharge power generation circuit 1200 are included.

As shown, a plurality of bit line pairs BL and BL are formed in a memory cell array 1100 having a folded bit line structure according to a conventional example, and a plurality of bit line pairs BL and BL are formed. A plurality of word lines WL0 to WL7 are formed perpendicularly to the plurality of word lines.

In addition, the bit line precharge power generation circuit 1200 according to the conventional example may have a bit line pair BL when the even word lines WL0, WL2, WL4, and WL6 are activated in the stress test mode. When the low level bit line precharge power supply VBLP is applied and the odd word lines WL1, WL3, WL5, and WL7 are activated, the bit line precharge power supply VBLP is applied to the bit line pair BL, / BL. A high level bit line precharge power supply (VBLP) is applied.

Therefore, the memory cell array 1100 having the folded bit line structure according to the related art applies different powers between neighboring cells through the bit line precharge power generation circuit 1200 to generate bit lines and cells. Find faults between, and plugs.

FIG. 2 is a schematic diagram illustrating a structure of a bit line power supply wiring for applying stress between a bit line, a cell, and a plug according to another exemplary embodiment of the related art. In particular, a memory having an open bit line structure A cell array 2100 and a bit line precharge power generation circuit 2200 are shown.

As illustrated, a plurality of bit line pairs BL and BL are formed in a memory cell array 2100 having an open bit line structure according to another exemplary embodiment, and a plurality of bit line pairs BL and BL are formed. A plurality of word lines (ISO WL, WL0, WL1, ISO WL, WL2, WL3, ISO WL) are formed perpendicularly.

Here, in the conventional memory cell array 2100 having an open bit line structure, one sense amplifier unit is connected to each cell block, and the bit lines connected to the sense amplifier unit are connected to different cell blocks. In mode, the same stress mode test as in FIG. 1 cannot be applied.

Accordingly, the memory cell array 2100 having an open bit line structure according to another exemplary embodiment may include a bit line precharge power supply VBLP and a first bit line precharge power supply VBLP0 and a second bit line precharge power supply VBLP1. Run the stress test.

That is, according to another conventional example, the bit line precharge power generation circuit 2200 may include a first bit line precharge power generation unit 2210, a second bit line precharge power generation unit 2220, and a bit line precharge. The first bit line precharge power generator 2210 may include a bit line connected to the odd word lines WL1 and WL3 when the odd word lines WL1 and WL3 are activated. The first bit line precharge power supply VBLP0 is applied to (BL). In addition, when the even-numbered word lines WL0 and WL2 are activated, the second bit line precharge power generator 2220 may include a second bit line in a bit line BL connected to the even-numbered word lines WL0 and WL2. The precharge power supply VBLP1 is applied.

Hereinafter, first and second bit line precharge power generations provided in the bit line precharge power generation circuit 2200 in the stress test mode of the memory cell array 2100 having the open bit line structure according to another exemplary embodiment. The operations of the units 2210 and 2220 and the bit line precharge power controller 2230 will be described in detail with reference to FIGS. 2A to 2E.

For reference, the first test control signal TRCPH is a signal used to apply the core voltage VCORE to all bit lines during the stress test, and the second test control signal TRCPL is all bit lines during the stress test. This signal is used to apply ground voltage (VSS). Also, the test off signal TVBLPOFF is a signal used to enter the stress test mode, and the bit line precharge signal BLP is a half core voltage (1/2 * VCORE) as a bit line in the normal mode. This signal is used when applying.

2A is a circuit diagram of a first bit line precharge power generation unit according to another example of the related art.

As illustrated, the first bit line precharge power generator 2210 according to another exemplary embodiment of the present invention performs a NOR operation on the first test control signal TRCPH and the test off signal TVBLPOFF. ); An NMOS transistor 2212 selectively outputting the bit line precharge signal BLP to the node 'A' according to the voltage level of the signal output from the NOR gate 2211; Inverters 2213 and 2214 delaying and outputting second test control signals TRCPL; A NAND gate 2215 for NAND-operating the inverted signal from the inverter 2213 and the first test control signal TRCPH; It is connected between the core voltage VCORE line and the ground voltage VSS line, and receives an output signal of the NAND gate 2215 and an output signal of the inverter 2214 to output the first bit line precharge power supply VBLP0. An output driver 2216.

Here, the output driver 2216 is connected between the core voltage VCORE line and the node 'A', and has a PMOS transistor 2216a that receives an output signal of the NAND gate 2215, a node 'A' and a ground voltage. And an NMOS transistor 2216b connected between the (VSS) lines and receiving the output signal of the inverter 2214.

2B is a circuit diagram of a second bit line precharge power generation unit according to another exemplary embodiment.

As shown in the drawing, the second bit line precharge power generator 2220 according to another exemplary embodiment of the present invention performs a NOR operation on the first test control signal TRCPH and the test off signal TVBLPOFF, and outputs the NOR gate 2221. ; An NMOS transistor 2222 for selectively outputting the bit line precharge signal BLP to the node 'B' according to the voltage level of the signal output from the NOR gate 2221; An inverter 2223 for inverting and outputting the first test control signal TRCPH; A NAND gate 2224 that NAND-operates and outputs the signal inverted by the inverter 2223 and the second test control signal TRCPL; An inverter 2225 for inverting and outputting a NAND-operated signal from the NAND gate 2224; And a second voltage connected between the core voltage VCORE line and the ground voltage VSS line and receiving the output signal of the inverter 2223 and the output signal of the inverter 2225 to output the second bit line precharge signal VBLP1. An output driver 2226;

Here, the output driver 2226 is connected between the core voltage VCORE line and the node 'B', and receives a PMOS transistor 2226a that receives the output signal of the inverter 2223, and the node 'B' and the ground voltage ( VSS) and NMOS transistors 2226b that receive the output signal of the inverter 2225.

FIG. 2C is a circuit diagram of a bit line precharge power supply connection control unit according to another exemplary embodiment. The first bit line precharge power supply VBLP0 and the second bit line precharge power supply VBLP1 are connected to each other (short) or separated (open). ) Is a circuit.

As illustrated, the bit line precharge power connection control unit 2230 according to another conventional example NAND gate 2231 outputs a NAND combination of the first test control signal TRCPH and the second test control signal TRCPL. ; An inverter 2232 for inverting and outputting a signal output from the NAND gate 2231; A level shifter 2233 for selectively outputting the ground voltage VSS or the highest voltage VPP according to the signal output from the inverter 2232; And an NMOS transistor 2234 for selectively connecting or disconnecting the first bit line precharge power supply VBLP0 and the second bit line precharge power supply VBLP1 according to the signal output from the level shifter 2233.

Here, the highest voltage VPP is a voltage at which a power supply voltage (for example, VCC) is boosted to a predetermined level through a puncture circuit (not shown).

FIG. 2D is a table illustrating an operation of a memory bit line precharge power generation circuit according to another exemplary embodiment, and FIG. 2E is a waveform diagram illustrating an operation of a memory bit line precharge power generation circuit according to another exemplary embodiment.

As shown in the drawing, the memory cell array stress circuit 2200 according to another exemplary embodiment operates in a normal mode when both the first and second test control signals TRCPH and TRCPL are at a low level. The bit line precharge power supplies (VBLP0, VBLP1) are all output at 1/2 core voltage (1/2 * VCORE).

In addition, the memory bit line precharge power generation circuit 2200 according to another exemplary embodiment may operate in a stress test mode when the first and second test control signals TRCPH and TRCPL are high level and low level, respectively. Both the first and second bit line precharge power supplies VBLP0 and VBLP1 are output as the core voltage VCORE.

In addition, the memory bit line precharge power generation circuit 2200 according to another exemplary embodiment may operate in a stress test mode when the first and second test control signals TRCPH and TRCPL are low level and high level, respectively. Both the first and second bit line precharge power supplies VBLP0 and VBLP1 are output to the ground voltage VSS.

In addition, the memory bit line precharge power generation circuit 2200 according to another exemplary embodiment may operate in the stress test mode when the first and second test control signals TRCPH and TRCPL are both at a high level, and thus, may be used in the first and second memory bit line precharge power generation circuits 2200. 2 bit line precharge power supplies VBLP0 and VBLP1 are output as ground voltage VSS and core voltage VCORE, respectively.

As described above, the memory bit line precharge power generation circuit 2200 according to another exemplary embodiment generates various internal power sources through the first and second test control signals TRCPH and TRCPL.

However, in the conventional memory bit line precharge power generation circuit according to another exemplary embodiment, only the ground voltage VSS and the core voltage VCORE are respectively provided when the first and second test control signals TRCPH and TRCPL are both at a high level. There is a problem with the output. That is, the memory bit line precharge power generation circuit according to another conventional example outputs the first bit line precharge power supply VBLP0 as the ground voltage VSS when different power is applied between neighboring cells. The second bit line precharge power supply VBLP1 is output as the core voltage VCORE. Therefore, the memory bit line precharge power generation circuit according to another example of the related art has a problem in that various internal power sources cannot be combined when different powers are applied between neighboring cells.

In addition, the memory bit line precharge power generation circuit according to another exemplary embodiment outputs the first and second bit line precharge power supplies VBLP0 and VBLP1 using an internal power source, and thus, voltage levels cannot be variously changed. There is a problem. That is, the memory bit line precharge power generation circuit according to another exemplary embodiment performs a stress test using only the core voltage VCORE, the ground voltage VSS, and the half core voltage (1/2 * VCORE). However, there is a problem that it is impossible to test by applying various voltage levels.

Therefore, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to apply from an internal power supply and an external power pad during a stress test of a memory cell array having an open bit line structure. The present invention provides a memory bit line precharge power generation circuit capable of selectively outputting an external power supply to stress test at various voltage levels.

In accordance with one aspect of the present invention, there is provided a bit line precharge power generation circuit for generating a power applied to each of the first and second bit lines of an open bit line structure in order to achieve the above object: A first bit line precharge power generation unit generating power applied to the first bit line; A second bit line precharge power generation unit configured to generate power applied to the second bit line; A first power pad connected to the first bit line to selectively supply a first external power; And a second power pad connected to the second bit line to selectively supply a second external power.

In the above configuration, in the normal mode, the first and second bit line precharge power generation units supply 1/2 core voltage to the first and second bit lines, respectively.

In the configuration, in the stress test mode, the first and second bit line precharge power generators supply a core voltage or a ground voltage to the first and second bit lines, respectively, or supply the first and second power pads. It is characterized in that for supplying the first and second external voltage through.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic diagram illustrating a structure of a bit line power supply wiring for applying stress between bit lines, cells, and plugs according to the present invention. In particular, a memory cell array 3100 and a bit having an open bit line structure are illustrated in FIG. A line precharge power generation circuit 3200 is shown.

As illustrated, the bit line precharge power generation circuit 3200 according to the present invention includes a first bit line precharge power generation unit 3210, a second bit line precharge power generation unit 3220, and a bit line precharge. And a power connection controller 3230 and power pads 3240 and 3250. The first bit line precharge power generator 3210 may include an odd word line when the odd word lines WL1 and WL3 are activated. The first bit line precharge power supply VBLP0 is applied to the bit line BL connected to the WL1 and WL3. In addition, when the even-numbered word lines WL0 and WL2 are activated, the second bit line precharge power generator 3320 may include a second bit line in a bit line BL connected to the even-numbered word lines WL0 and WL2. The precharge power supply VBLP1 is applied.

Hereinafter, the first and second bit line precharge power generators included in the bit line precharge power generation circuit 3200 in the stress test mode of the memory cell array 3100 having the open bit line structure according to the present invention. 3210 and 3220 and the configuration and operation of the bit line precharge power control unit 3230 will be described in detail with reference to FIGS. 3A to 3E.

3A is a circuit diagram of a first bit line precharge power generation unit according to the present invention.

As illustrated, the first bit line precharge power generator 3210 may include a NOR gate 3211 that performs a NOR operation on the first test control signal TRCPH and the test off signal TVBLPOFF; An NMOS transistor 3212 selectively outputting the bit line precharge signal BLP to the node 'C' according to the voltage level of the signal output from the NOR gate 3211; An inverter 3213 which inverts and outputs a power selection signal TM_TVBLPE; A NAND gate 3214 for NAND-operating the first test control signal TRCPH and the power selection signal TM_TVBLPE; An output driver 3215 for receiving an output signal of the NAND gate and a second test control signal TRCPL and outputting a first bit line precharge power supply VBLP0; And a power pad 3240 for outputting external power.

Here, the output driver 3215 is connected between the core voltage VCORE line and the node 'C', and receives a PMOS transistor 3215a that receives an output signal of the NAND gate 3214, a node 'C' and a ground voltage. The NMOS transistor 3215b is connected between the (VSS) lines and receives the second test control signal TRCPL.

In addition, the power pad 3240 is connected to the node 'C' to selectively output the external power. In other words, the power pad 3240 applies external power to the node 'C' only in the test mode.

3B is a circuit diagram of a second bit line precharge power generation unit according to the present invention.

As illustrated, the second bit line precharge power generation unit 3220 may include a NOR gate 3221 for performing a NOR operation on the first test control signal TRCPH and the test off signal TVBLPOFF; An NMOS transistor 3222 selectively outputting the bit line precharge signal BLP to the node 'D' according to the voltage level of the signal output from the NOR gate 3221; An inverter 3223 which inverts and outputs a power selection signal TM_TVBLPE; A NAND gate 3224 for NAND-operating the first test control signal TRCPH and the power selection signal TM_TVBLPE; And an output driver 3225 for receiving the output signal of the NAND gate and the second test control signal TRCPL to output the second bit line precharge power supply VBLP1. And a power pad 3250 for outputting external power.

Here, the output driver 3225 is connected between the core voltage VCORE line and the node 'D', and has a PMOS transistor 3225a receiving the output signal of the NAND gate 3224, a node 'D' and a ground voltage. The NMOS transistor 3225b is connected between the (VSS) lines and receives the second test control signal TRCPL.

In addition, the power pad 3250 is connected to the node 'D' to selectively output external power. In other words, the power pad 3250 applies external power to the node 'D' only in the test mode.

3C is a circuit diagram of a bit line precharge power connection controller according to the present invention.

As illustrated, the bit line precharge power connection controller 3230 may include a NAND gate 3231 for NAND combining the first test control signal TRCPH and the power selection signal TM_TVBLPE; An inverter 3322 for inverting and outputting a signal output from the NAND gate 3231; A level shifter 3333 for selectively outputting a ground voltage VSS or a highest voltage VPP according to the voltage level of the signal output from the inverter 3322; And an NMOS transistor 3234 selectively connecting or disconnecting the first precharge power supply VBLP0 and the second precharge power supply VBLP1 according to the voltage level of the signal output from the level shifter 3333.

An operation characteristic of the memory bit line precharge power generation circuit 3200 having the above configuration varies according to an operation mode of the memory cell array 3100, which will be described in detail with reference to FIGS. 3A through 3C. do.

First, the first and second bit line precharge power generators 3210 and 3220 according to the present invention may have low level first and second test control signals TRCPH and TRCPL in the normal mode of the memory cell array 3100. ) And the power selection signal TM_TVBLPE are turned off to turn off the output drivers 3215 and 3225, respectively. At this time, the test off signal TVBLPOFF becomes low level and is applied to the NOR gates 3211 and 3221, respectively. After that, the NOR gates 3211 and 3221 are the low level first test control signal TRCPH and the test off signal. (TVBLPOFF) is received and a high level voltage is output to the gate terminals of the NMOS transistors 3212 and 3322, respectively. The NMOS transistors 3212 and 3222 are then turned on to output the bit line precharge signals BLP to the first and second bit line precharge power supplies VBLP0 and VBLP1, respectively.

In brief, the first and second bit line precharge power generators 3210 and 3220 according to the present invention may operate at the low level of the first and second test control signals TRCPH, in the normal mode of the memory cell array 3100. TRCPL and the power selection signal TM_TVBLPE are received to output the bit line precharge signal BLP of 1/2 core voltage 1/2 * VCORE, respectively.

At the same time, the bit line precharge power connection controller 3230 connects the first bit line precharge power supply VBLP0 and the second bit line precharge power supply VBLP1 to each other.

In detail, the bit line precharge power connection controller 3230 receives the low level first test control signal TRCPH and the power selection signal TM_TVBLPE in the normal mode of the memory cell array 3100. The low level voltage is output to the level shifter 3333 via the NAND gate 3231 and the inverter 3332. Then, the level shifter 3333 receives the low level voltage output from the inverter 3322 and outputs the highest voltage VPP. Then, the NMOS transistor 3234 receives the highest voltage VPP and turns on. do. Accordingly, the first and second bit line precharge power supplies VBLP0 and VBLP1 connected to the source and drain terminals of the NMOS transistor 3234 are connected to each other by turning on the NMOS transistor 3234.

Accordingly, the bit line precharge power generation circuit 3200 according to the present invention uses the bit line precharge power supply control unit 3230 to provide the first bit line precharge power supply VBLP0 and the second bit line precharge power supply VBLP1. Connect the same bit line precharge signal (BLP) to the bit line.

Next, the first and second bit line precharge power generators 3210 and 3220 according to the present invention may be connected to the first and second test control signals TRCPH and TRCPL in a stress test mode of the memory cell array 3100. The first and second bit line precharge power supplies VBLP0 and VBLP1 having various voltage levels are output according to the voltage level of the power selection signal TM_TVBLPE.

Here, the bit line precharge power generation circuit 3200 according to the present invention receives the high level test off signal TVBLPOFF and the NMOS transistors 3212 and 3222 are turned off, respectively. The bit line precharge signal BLP is blocked from the node 'C' and the node 'D'. That is, the memory cell array 3100 operates in the stress test mode by the high level test off signal TVBLPOFF of the bit line precharge power generation circuit 3200.

In the stress test mode, first, when the first test control signal TRCPH is at a high level and the second test control signal TRCPL and the power selection signal TM_TVBLPE are at a low level, they are provided in the output drivers 3215 and 3225. The PMOS transistors 3215a and 3225a are turned on, respectively, and the NMOS transistors 3215b and 3225b included in the output drivers 3215 and 3225 are turned off, respectively. Accordingly, the first and second bit line precharge power generators 3210 and 3220 output both the first and second bit line precharge power supplies VBLP0 and VBLP1 as the core voltage VCORE. .

Next, when the first test control signal TRCPH and the power selection signal TM_TVBLPE are low level, and the second test control signal TRCPL is high level, the PMOS transistors 3215a of the output drivers 3215 and 3225 are provided. 3325a are turned off, respectively, and the NMOS transistors 3215b and 3225b included in the output drivers 3215 and 3225 are turned on, respectively. Accordingly, the first and second bit line precharge power generators 3210 and 3220 according to the present invention output both the first and second bit line precharge power supplies VBLP0 and VBLP1 to the ground voltage VSS. do.

Next, when the power selection signal TM_TVBLPE is high level and the second test control signal TRCPL is low level, the output drivers 3215 and 3225 are turned off, respectively. Accordingly, the first and second bit line precharge power supplies VBLP0 and VBLP1 are separated from the bit line precharge signal BLP, the core voltage VCORE, and the ground voltage VSS, respectively, to be in a floating state. do. In this case, the power pads 3240 and 3250 apply external power to the output nodes of the first and second bit line precharge power generators 3210 and 3220, that is, the nodes 'C' and the nodes 'D', respectively. Accordingly, the first and second bit line precharge power generators 3210 and 3220 output external power having various voltage levels to the first and second bit line precharge power supplies VBLP0 and VBLP1, respectively.

As described above, the memory bit line precharge power generation circuit 3200 according to the present invention selectively outputs the internal power supply and the external power supply according to the voltage level of the power selection signal TM_TVBLPE in the stress test mode. This will be described in detail with reference to FIGS. 3D and 3E.

3D is a table showing the operation of the memory bit line precharge power generation circuit according to the present invention, and FIG. 3E is a waveform diagram showing the operation of the memory bit line precharge power generation circuit according to the present invention.

As shown, the memory bit line precharge power generation circuit 3200 according to the present invention has a voltage level of the first and second test control signals TRCPH and TRCPL when the power selection signal TM_TVBLPE is at a low level. Outputs a variety of internal power supplies depending on the state. In addition, when the power selection signal TM_TVBLPE has a high level, the memory bit line precharge power generation circuit 3200 according to the present invention may use the power pad 3240, regardless of the voltage level of the first test control signal TRCPH. An external power source applied at 3250 is output. At this time, the second test control signal TRCPL should maintain a low level.

As described above, in the memory bit line precharge power generation circuit according to the present invention, the internal power supply and the external power supply according to the voltage level of the first and second test control signals TRCPH and TRCPL and the power selection signal TM_TVBLPE. Outputs an optional. Accordingly, the memory bit line precharge power generation circuit according to the present invention outputs the first and second bit line precharge power supplies VBLP0 and VBLP1 having various voltage levels, and accordingly, various voltage levels are applied to the memory cell array. There is an effect that can be tested by applying stress.

According to the configuration as described above of the present invention, in the memory bit line precharge power generation circuit, there is an effect that the stress test at various voltage levels by selectively outputting the external power applied from the internal power supply and the external power pad.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (3)

In the bit line precharge power generation circuit for generating a power applied to each of the first and second bit lines of the open bit line structure, A first bit line precharge power generation unit configured to generate power applied to the first bit line; A second bit line precharge power generation unit configured to generate power applied to the second bit line; A first power pad connected to the first bit line to selectively supply a first external power; And And a second power pad connected to the second bit line to selectively supply a second external power. The method of claim 1, The bit line precharge power generation circuit of claim 1, wherein the first and second bit line precharge power generation units supply 1/2 core voltage to the first and second bit lines, respectively. The method of claim 1, In the stress test mode, the first and second bit line precharge power generators supply a core voltage or a ground voltage to the first and second bit lines, respectively, or through the first and second power pads. And a second external power supply.

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