KR20070020391A - Dmac issue mechanism via streaming id method - Google Patents

Abstract

Apparatus, methods, and computer programs are provided for executing Direct Memory Access (DMA) instructions. Physical queues are divided into multiple virtual queues by software based on instruction types such as processor to processor, input / output (I / O) devices to the processor, and external or system memory to the processor. The command is then assigned to a slot based on the type of DMA command, i. Once assigned, the instructions can be changed between slots and executed by using a continuous system of slots to provide a more efficient way to execute DMA commands.

DMA, commands, queues, slots, quotas

Description

DMCA issuing mechanism by streaming ID method {DMAC ISSUE MECHANISM VIA STREAMING ID METHOD}

The present invention relates to the issue of a Direct Memory Access (DMA) request command, and more particularly to the operation of a command queue.

Over the years, DMAs have become an important aspect of computer architecture. In addition to DMA, multiprocessor systems have evolved using DMA to provide faster processing power. Especially with regard to DMA, there are two typical types of requests or instructions issued from a processor and executed by a DMA controller (DMAC), namely load and store. Of course, depending on the system, individual processors may have the ability to load or store from input / output (I / O) devices, local memory and memory devices of other processors, and the like.

Recently, however, multiprocessors and DMACs have been combined on a single chip. Reduction to a single chip allows for reduced speed as well as increased speed. The DMAC, processor, bus interface unit (BIU) and bus can all be coupled on a chip. The data flow of such a system starts from a processor core, which allocates DMA instructions, which are stored in a DMA instruction queue. Each DMA command can be expanded or split into smaller bus requests to the BIU. The resulting deployed request is stored in the BIU pending bus request queue. The BIU then sends a request to the bus controller. In general, requests are sent from the BIU in the order received from the DMA. When the bus request is completed, the BIU pending the bus request queue is able to receive a new DMA queue.

Meanwhile, a bottleneck may occur due to the physical size of the snoop queue at the receiving device and the BIU pending the bus request queue at the source device. Typically, the bottleneck is a function of queue order and / or delay of execution instructions. For example, a second instruction to load from the local memory of another processor may be delayed waiting for the first instruction to be stored in Dynamic Random Access Memory (DRAM). As a result, the resulting bottleneck can result in a significant loss in operating speed.

The bottleneck may be the execution of the DMA command order. In fact, certain instructions execute faster than others. For example, DMA instruction execution that moves data between processors on the same chip may be completed at a faster rate than DMA instruction execution to external memory or I / O devices, which typically takes longer periods. As a result, DMA commands for moving data to memory or I / O devices will stay longer in the pending BIU than the request queue. As a result, a BIU pending a request queue may be occupied by a later bus request, leaving little or no accommodation space for additional bus requests from the DMA. This causes performance degradation of the processor because the processor must stop to wait for the available space of the BIU pending the bus request queue.

Another factor in the bottleneck may be retry. When the composite source device moves data to / from the same receiving device, when the snoop queue is in a full state that causes the source device to retry the same bus request later, the receiving device receives the bus request. You must refuse.

Another factor in the bottleneck may be the order or execution of the command at the receiving device. In conventional DRAM access, DRAM devices may operate in parallel on successive memory banks. In addition, bidirectional buses are typically used to interface with DRAM devices. If the direction of data movement changes frequently, the bus bandwidth is reduced due to the additional bus cycles required for the bus to turn. In addition, in order to obtain larger parallel DRAM access, it is desirable to perform a series of reads or writes to the same memory page.

Accordingly, to solve the above problem, a method and / or apparatus for improving the efficiency of a DMA issuance mechanism is needed.

Various aspects of the present invention may address certain bottleneck problems associated with useful DMA requirements. The DMA controller receives the DMA command from the processing element and develops each request to the bus interface unit. The issue logic in the DMA controller determines which commands are allowed to issue and / or the timing of issuing the commands. The bus interface unit in the DMA controller has a queue, which holds the DMA request before the DMA request is issued to the bus. Each DMA request may target a external memory, I / O device or on-chip memory. Examples of on-chip memory include local storage memory (local memory of the processing element), memory mapped IO (MMIO) or cache-to-cache moving means.

In one overview, one or more attributes of multiple DMA requests in a DMA queue may help to reduce the total performance of the memory system. For example, one or more attributes may include whether the DMA request is for a DMA read command or for a DMA write command. Since each DMA command is divided into a number of memory accesses and then executed normally, a number of successive DMA read operations or numerous DMA write operations can reduce performance. Alternate read and write operations can solve this problem.

In accordance with one or more embodiments of the present invention, the concept of "slot" may be used to control the timing of issuing a memory access in response to a DMA request in a DMA queue. For example, assuming that constant memory access permits a certain time slot (or interval) "T" (T = 0, 1, 2, 3, ...), issuing a command for a read and write operation is a read. While the memory access operation is issued during slot 2T, the write memory access operation can be controlled to be issued during slot 2T + 1. For example, some systems may experience reduced performance when a continuous read or write operation is issued, processor-to-processor access is required, or I / O access is required at the processor. have. In such a system, successive read or write operations for memory accesses in the processor may not result in reduced performance. On the other hand, the loss of performance can be avoided by simply using the slot concept in the processor or in the I / O access context in the processor.

In addition, the use of the streaming ID concept may prove beneficial for maintaining high speed memory access. Streaming ID access may be used to identify the target of the requested access, such as identification between an access request to memory or an access request to an I / O device. To illustrate the operational problem solved by the streaming ID concept, assume that access to an I / O device requires more time than access to memory. Further assume that the number of memory access requests and the number of I / O access requests stored in the DMA queue are substantially the same. In such a case, the access time to memory may include excess time that is not normally present (due to servicing I / O access requests), and thus may be later than expected. In order to solve this problem, it is possible to allocate each quota, one quota for memory access requests and one quota for I / O access requests. Thus, even if an I / O access request is suspended (due to reaching an I / O access quota), since the memory access quota may not be reached, the speed of servicing the memory access request will be maintained without any reduction in performance. Can be.

Slot access and streaming ID access can be used individually or in combination. Accordingly, the issuance policy may consider at least one of the following factors: slot change, streaming ID group, and age of the DMA command. Those skilled in the art will appreciate that the detailed description herein mainly refers to the combination of slot and streaming ID access.

For example, in one embodiment of the present invention, a method and computer program for executing the instructions of DMAC have been considered. The slot is initially selected. Once the slot is selected, a determination is made as to which group of the selected slot is valid. If no valid group exists, another slot is selected. On the other hand, if there is at least one valid group, a continuous coordination plan is used to select the group. Within the selected group, the oldest undetermined DMA command is taken and deployed. The developed bus request is assigned to the BIU. After expansion, the DMA command parameters are updated and written back to the DMA command queue.

For a deeper understanding of the present invention and its advantages, reference is made to the following description in conjunction with the accompanying drawings.

1 is a block diagram illustrating a multiprocessor computer system using DMAC.

2A is a block diagram illustrating an improved DMAC command queue.

2B is a block diagram illustrating a control register of an improved DMAC command register.

3 is a flow diagram illustrating issuance of instructions by the DMAC issuance mechanism.

In the following, numerous specific details are set forth in order to provide a thorough understanding of the present invention. On the other hand, those skilled in the art will appreciate that the invention may be practiced without these specific details. In other instances, well-known elements are shown in outline or block diagram form in order to avoid obscuring the present invention from unnecessary description. Moreover, in most cases, details regarding network communications and electronic signal technology, etc., are omitted since such details are not considered necessary to obtain a thorough understanding of the present invention and are to be understood by those skilled in the art.

In addition, unless otherwise indicated, all of the functions described herein may be implemented in hardware, software, or any combination thereof. On the other hand, in a preferred embodiment, these functions may be provided to a processor, such as a computer or electronic data processor, in accordance with code such as computer program code, software and / or integrated circuits coded to carry out such functions, unless otherwise indicated. Is executed by

Referring to FIG. 1, generally reference numeral 100 denotes a multiprocessor computer system using DMAC. The system 100 includes a first processor 101, a second processor 103, a third processor 105, a bus 130, a memory controller 122, a memory device 124, an I / O controller 126. And I / O device 128. In addition, there are various types of storage or memory devices that can be used with the system 100. In addition, as shown in FIG. 1, there may be a single processor or a composite processor.

Each of the processors 101, 103, 105 are configured in a common manner to communicate data. Each of the first processor 101, the second processor 103, and the third processor 105 further includes a first processor core 104, a second processor core 106, and a third processor core 108 separately. do. The first processor core 104 is coupled to the first DMAC 110 via a first load communication channel 152 and a first storage communication channel 150. The second processor core 106 is coupled to the second DMAC 112 via a second load communication channel 156 and a second storage communication channel 154. The third processor core 108 is coupled to the third DMAC 114 via the third load communication channel 160 and the third storage communication channel 158. The first DMAC 110 is coupled to the first BIU 116 via a fourth storage communication channel 162 and a fourth load communication channel 164. The second DMAC 112 is coupled to the second BIU 118 via a fifth storage communication channel 166 and a fifth load communication channel 168. The third DMAC 114 is coupled to the third BIU 120 via the sixth storage communication channel 170 and the sixth load communication channel 172.

In addition, each of the individual processors operates in a common manner. Instructions such as load or store instructions originate from the processor core. There are various instructions that can be issued by a given processor. On the other hand, for the sake of explanation, it focuses on three separate instruction types: processor to processor, processor to memory device, and processor to I / O device. After the command is issued by the processor core, the command is sent over DMAC. The DMAC then deploys the command to the BIU, and the bus request queue pending at the BIU stores the deployed bus request. Next, the bus request is sent to the bus. If the bus controller provides a request, the source and receiving devices will execute the data transfer to complete the bus request.

Multiprocessor computer system 100 using DMAC operates by using bus 130 to communicate data and bus requests between various components. The first processor 101 is coupled to the bus 130 via a seventh storage communication channel 174 and a seventh load communication channel 176. The second processor 103 is coupled to the bus 130 via an eighth storage communication channel 178 and an eighth storage load communication channel 180. The third processor 105 is coupled to the bus 130 via a ninth storage communication channel 182 and a ninth load communication channel 184. Memory controller 122 uses a bidirectional memory bus implementation to communicate data to and from memory device 124. Accordingly, memory controller 122 is coupled to bus 130 by a bi-directional memory bus implementation via tenth storage communication channel 186 and tenth load communication channel 188. In addition, I / O controller 126 is coupled to bus 130 via eleventh storage communication channel 190 and eleventh load communication channel 192.

In addition to connections to the bus 130, there may also be connections between various other components. More specifically, controllers such as memory controller 122 and I / O controller 126 require connection to other separate devices. The memory controller 122 is coupled to the memory device 124 via a communication channel 194 controlled by the first bandwidth. I / O controller 126 is coupled to I / O device 128 via communication channel 196 controlled by the second bandwidth and communication channel 198 controlled by the third bandwidth.

2A and 2B, reference numerals 200 and 250 generally denote command queues and control registers of the DMAC, respectively. DMA command queue 200 includes a fixed number of entries, each entry having three fields: slot field 210, streaming ID field 220 and command field 230. Divided into. The DMA control register 25 includes a slotable register 252 and a quarter register 266.

In a DMAC, such as the DMAC 110 of FIG. 1, there is a limited number of queue entries that queue a command in a physical queue. The incoming DMA command can be placed in any available command queue entry. The slot designation for each DMA command is entered into the slot field 210. Since the DMA command is composed of an instruction operation code and operands, like the streaming ID, the streaming ID is placed in the streaming ID field 220 and the instruction operation code and other operands are placed in the instruction field 230. Each streaming ID is configured to have a slot function enabled or suppressed in a single bit slot enable register 252, where the single bit slot enabled register 252 is configured for the available slot 254 of group 0, the group 1; It is represented by a possible slot 256 and a possible slot 258 in group 2. Moreover, there are certain quotas represented by the quota 260 of group 0, the quota 262 of group 1, and the quota 264 of group 2. The total sum of quotas is limited by the size of the BIU's pending bus request queue.

Enabling or suppressing slots is used to match bus bandwidth characteristics (eg, slot functionality is suppressed if the bus is bidirectional, such as a memory bus). If the slot function is enabled for the Streaming ID group, the load command will be assigned a value of 0 in the slot field 210 and the save command will be assigned a value of 1 in the slot field 210. If the slot function is disabled, load and store instructions will be assigned a value of zero in the slot field 210.

Typically, however, three bus request operations may occur, i.e., an I / O device in the processor, an external or system memory in the processor, and a processor. Three operations may be assigned to a streaming ID group.

In general, processor instructions are assigned to streaming ID group 0 at the processor, memory instructions are assigned to streaming ID group 1 at the processor, and I / O instructions are assigned to streaming ID group 2 at the processor. In this case, in order to match the bus bandwidth characteristics associated with the DMA command, the slot function is enabled for streaming ID groups 0 and 2 and is suppressed for group 1.

DMA commands are typically deployed with one or more bus requests to the BIU. This bus request is queued in a BIU pending a DMA bus request queue, where the BIU pending a DMA bus request queue has a limited size. By configuring the quota for each streaming ID group, this queue is divided into three virtual queues. Depending on the software application, the size of the three virtual queues can be dynamically configured by streaming ID quota.

Referring to FIG. 3, generally reference numeral 300 represents a flow diagram illustrating issuance of instructions from a modified DMAC issuance mechanism.

As shown in the flowchart of FIG. 3, once a DMA command has been entered into the command queue, the DMAC should provide a process for issuing a command such as process 300. In step 302, a change between slot 0 and slot 1 occurs. To provide more efficient use of the available bandwidth for the unidirectional bus type, the DMAC changes between slots.

When slot 0 is chosen to be executed next, DMAC makes a series of measurements to determine the issue command queue. In step 304, the DMAC determines which group has a valid pending DMA command. Each group is associated with a maximum issue count or quota. The quota limits the number of bus requests that can be issued to prevent system overflow. In order to maintain proper operation of the system, DMAC determines whether each group of slots exceeds a respective quota of step 306.

Once the validity and quota decisions have been made, DMAC selects the following command: In step 308, the DMAC uses a continuous selection system between command groups. Upon selection, the decision is made according to whether there are any valid groups under the respective quota limits with pending commands in step 310. If no valid group exists under an individual quota limit with pending commands, the change is made to another slot, slot one. On the other hand, if there is a valid group under an individual quota with undecided commands, the oldest command from the selected group is transferred in step 312. The continuation pointer is adjusted to the next group of streaming ID commands, the size of the queue is reduced in step 314, and the slot is changed in step 302.

When slot 1 is chosen to be executed next, DMAC makes a series of measurements to determine the issue command queue. At step 316, the DMAC determines which group has a valid pending DMA command. Each group is associated with a maximum issue count or quota. Quotas limit the number of bus requests that can be issued to prevent system overflow. To maintain proper operation of the system, DMAC determines whether each group of slots exceeds each quota in step 318.

Once the validity and quota decisions have been made, DMAC selects the following command: In step 320, the DMAC uses a continuous selection system between command groups. Upon selection, the decision is made based on whether there are any valid groups under the respective quota limit with pending commands in step 322. If no valid group exists under an individual quota limit with pending commands, the change is made to another slot, slot 0. On the other hand, if there is a valid group under separate quota with pending commands, the oldest command from the selected group is developed in step 324. The continuous pointer is adjusted to the next group of streaming ID commands, the size of the queue is reduced in step 326, and the slot is changed in step 302.

In all processors that are load or store instructions, memory instructions are deployed through slot 0. The reason for issuing multiple commands in this way is to improve efficiency. Changing the direction of the bidirectional bus is time consuming. In addition, with the external memory, there are a plurality of banks that can each individually handle the request, so that the external memory can receive a compound command. In addition, the time required to handle the request is very long. This is advantageous for handling as multiple requests to external memory as burst load or storage, in order to minimize the change in the direction of the bidirectional bus and to maximize parallel load or storage in parallel.

From the above description, it should be further understood that in the preferred embodiment of the present invention, various modifications and changes can be made without departing from the spirit of the present invention. This description is for illustrative purposes only and should not be construed as limiting. It is intended that the scope of the invention should be limited only by the following claims.

Therefore, in describing the present invention with reference to the preferred embodiments of the present invention, the embodiments described herein are not inherently limited, and a wide variety of changes, modifications, changes, and substitutions are contemplated within the above description, and certain examples In the above, some features of the invention will be used without the corresponding use of other features. Many of these modifications and variations are understood by those skilled in the art upon examination of the preferred embodiments described above. Accordingly, the appended claims are to be construed broadly in accordance with the scope of the invention.

Claims (16)

A system for issuing a Direct Memory Access (DMA) request command originating from a processing element using a streaming ID, Bus means; DMA controller (DMAC) means having issuance logic means; A bus interface unit (BIU) means having a waiting queue means and connected between said bus means and said DMAC means; And A bus target means connected to the bus means and having at least one of an external memory, an input / output (IO) means, and an on-chip memory; The bus means is connected between the BIU means and the bus target means, The issue logic means determines which instructions are allowed to deploy as a bus request as a function of an issue policy with at least one of slot change, streaming ID group and age of the instructions, And the queue holding means holds each of the bus requests before issuing to the bus. The method of claim 1, wherein the DMAC means, An instruction code field having a plurality of entry positions; A slot field configured to be associated with at least an instruction designation and having a plurality of slot entries, each corresponding to at least one entry location of at least the plurality of entry locations; And And an identification field configured to include a streaming ID number corresponding to each entry location of at least the plurality of entry locations. 3. The system of claim 2, wherein the command designation further comprises a designation selected from the group consisting of a load command and a save command. 2. The system of claim 1, wherein said issuing logic means inhibits at least slot changes due to external devices having bidirectional buses. To issue a command with DMAC, Selecting one of the plurality of slots to provide the selected slot; Determining validity of the selected slot; If there is no valid group, selecting another one of the plurality of slots; If the at least one group is valid, selecting the oldest valid command; And Updating a group property for the group having the oldest valid command. 6. The method of claim 5, wherein selecting a slot further comprises selecting a load slot or a storage slot. The method of claim 5, wherein the determining the group validity, Determining a valid ID group of the plurality of ID groups; And Determining whether at least one valid ID group has reached a programmed quota. 6. The method of claim 5, wherein updating the queue characteristic further comprises moving a pointer to the group with the oldest valid instruction to the next pending bus request. A computer program product having a medium on which a computer program is recorded and for issuing instructions to DMAC, The computer program, Computer code for selecting any one of the plurality of slots to provide a selected slot; Computer code for determining group validity of the selected slot; Computer code for selecting another one of the plurality of slots when there is no valid group; Computer code for selecting the oldest valid command if at least one group is valid; And And computer code for updating a group property for the group having the oldest valid instruction. 10. The computer program product of claim 9, wherein the computer code for selecting the slots further comprises computer code for selecting a load slot or a storage slot. The computer code of claim 9, wherein the computer code for determining group validity is: Computer code for determining a valid ID group of the plurality of ID groups; And And computer code for determining whether at least one valid ID group has reached a programmed quota. 10. The computer program product of claim 9, wherein the computer code for updating the queue characteristic further comprises computer code for moving a pointer to a group having the oldest valid instruction to a next pending bus request. A processor that issues instructions to DMAC and has a computer program, Computer code for selecting any one of the plurality of slots to provide a selected slot; Computer code for determining group validity of the selected slot; Computer code for selecting another one of the plurality of slots when there is no valid group; Computer code for selecting the oldest valid command if at least one group is valid; And And computer code for updating a group property for the group having the oldest valid instruction. 14. The processor of claim 13, wherein the computer code for selecting the slots further comprises computer code for selecting a load slot or a storage slot. The computer code of claim 13, wherein the computer code for determining group validity is: Computer code for determining a valid ID group of the plurality of ID groups; And And computer code for determining whether at least one valid ID group has reached a programmed quota. 14. The processor of claim 13, wherein the computer code for updating the queue characteristic further comprises computer code for moving a pointer to the group having the oldest instruction to the next pending bus request.

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