KR20070017556A - Method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack - Google Patents

Abstract

The present invention provides a method and apparatus (10) for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor 22 and a memory 12 that includes at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on a transmission timing interval (TTI) of each data block such that a data block with a larger TTI is earlier than the data block with a smaller TTI. Allocated on the stack, and deallocated from the memory stack later than the data block with the smaller TTI. In one embodiment, the memory is a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated down And a fourth memory stack for the link channel.

Description

METHOD AND APPARATUS FOR EFFICIENTLY ALLOCATING AND DEALLOCATING INTERLEAVED DATA STORED IN A MEMORY STACK}

The present invention relates to storing and retrieving data stored in a memory. More specifically, the present invention relates to a method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack.

Interleaving is a well known process for those skilled in the art to improve resistance to errors when communicating data over the air interface. Many interleavers include a data buffer, which is an area of memory that temporarily holds data after interleaving or before deinterleaving.

Under the 3rd Generation Partnership Project (3GPP) standard, the data buffer in the first interleaver holds up to eight radio frames of data output from transmit (TX) transfer processing. 1 illustrates an example data block allocation in data buffer 100 in accordance with the prior art. The data buffer 100 is normally divided into eight memory regions 105, 110, 115, 120, 125, 130, 135, and 140 that are classified into the same size operating together as a circular buffer. During each 10 milliseconds (ms) of radio frames, one of the memory regions 105, 110, 115, 120, 125, 130, 135, 140 is consumed by the TX synthesis process and thus consumes new data from the TX transmission. The area is free.

The data buffer manager (not shown) stores information related to the locations of the memory areas 105, 110, 115, 120, 125, 130, 135, and 140, and stores the memory areas 105, 110, 115, 120, 125. Maintain calculations regarding the storage capacity currently assignable to each of the following operations. The allocation request in the data buffer 100 for storing data needs to specify the size and end time of the required storage area, which includes data buffer management information. The end time is specified within the radio frame associated with the current frame. The data buffer manager uses data buffer management information to find a suitable area for storing data.

Memory pointers and related functions that manage the data buffers are used to perform the interleaving process on the data. The memory pointer is used to point to the next available memory location of an adjacent segment of data and is also used on a given frame. Memory partitioning is a common problem that can be addressed by simply overspliting the data buffer 100.

The first interleaver memory is typically partitioned into up to eight equally classified segments corresponding to up to eight frames in which any newly arrived data can be used. The memory segment holds interleaved data corresponding to a single frame of data. For transmission, when a transport block set arrives, up to eight segments of all storage capacity are immediately allocated. For each of the following eight frames, only one memory segment is consumed and continuously free for use. For reception, as data is received, a memory is allocated for each frame of the transmission timing interval TTI of the transmission channel for up to eight frames. Next, after the transport channel is decoded, the memory is supplied freely at the same time.

The Universal Terrestrial Radio Access (UTRA) standard specifies a first interleaving step in the processing of data transmitted over a wireless air interface. The standard may code coded data within 80 milliseconds (8 frames). In order to avoid memory division, this data storage device may require 8 times as much memory as the amount of data reaching within a 10 millisecond frame. From the standard, one may realize eight times that the maximum amount of data that can be reached in a frame of 10 milliseconds does not have to be stored in the first interleaver buffer at a given time. It is worth noting that this limitation is described in Technical Specification (TS) 25.306 as the number of simultaneous bits that can be received within the matching TTI.

Accordingly, there is a need for new methods and apparatus for optimizing memory allocation in a first interleaver buffer that does not require large amounts of memory.

The present invention relates to a method and apparatus for use in a wireless communication system for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus may be an interleaver, a wireless transmit / receive unit (WTRU), a base station (ie, Node B) or an integrated circuit (IC). The apparatus includes a memory including a processor and at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is assigned to a specific transport channel (TrCH) and has a designated TTI. In addition, the processor stores the interleaved data blocks in the memory stack based on the TTI of each data block such that a data block with a larger TTI is assigned to the memory stack first, and later than a data block with a smaller TTI. Deallocated from the memory stack.

In one embodiment, the memory comprises a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated And a fourth memory stack for the downlink channel of.

Data blocks received from a dedicated channel and data blocks received from a common shared channel may be stored in separate regions of the memory stack.

Data blocks received from the uplink channel and data blocks received from the downlink channel may be stored in separate regions of the memory stack. Data blocks having the same TTI may be grouped together and sorted.

The memory may include a write pointer and a read pointer used to indicate the position of a segment in the memory stack to perform a write operation and a read operation, respectively. As soon as a block of data is received by the processor, a memory stack can be allocated for each frame of the TTI of the transport channel for up to eight frames.

A more detailed understanding of the invention may be possible from the following description of the preferred embodiments, which is provided for purposes of illustration with reference to the accompanying drawings.

1 is a diagram illustrating an exemplary data block allocation in accordance with the prior art.

2 is a block diagram of a first interleaver according to the present invention.

3 is a diagram illustrating an exemplary allocation of data blocks within a memory stack in accordance with the present invention.

4 is a diagram illustrating a block of data stored in a memory stack in accordance with the present invention.

5 is a flow diagram of a process including steps of a method for allocating and deallocating data in accordance with the present invention.

DESCRIPTION OF EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout. The invention can be implemented in both interleaver and deinterleaver. For convenience of explanation, only the interleaver will be described below.

The term "WTRU" hereinafter includes, but is not limited to, a user equipment (UE), a mobile station, a fixed or mobile subscriber unit, a pager, or any other type of device capable of operating in a wireless environment. . As referred to below, the term "node B" includes, but is not limited to, a base station, site controller, access point, or any other type of interfacing device in a wireless environment.

The present invention can be applied to time division duplex (TDD), frequency division duplex (FDD) and universal mobile telecommunications system (UMTS), time division synchronous CDMA (TDSCDMA) as generally applied to CDMA 2000 and CDMA. It may also be applicable to other wireless systems.

Features of the present invention may be integrated into an IC or may be configured in a circuit that includes a plurality of interconnect components. The invention may also be a process comprising a series of method steps implemented by executing a series of computer implemented instructions for a processor.

The present invention reduces the stack size of the first interleaver buffer by optimizing the stack for the TrCH data segment. The optimization of the first interleaver buffer depends on the ability to process the data values of the TTI from the first interleaver buffer of 10 millisecond frames. All frame rate components (software and hardware) are triggered to start processing at or near the start of a 10 millisecond frame, and also need to complete processing before the end of the same 10 millisecond frame. This ensures that no potential extra frames are introduced, thus supporting reducing the stack size requirement of the first interleaver buffer.

2 is a block diagram of an interleaver 10 operating in accordance with the present invention. The interleaver may be integrated into the WTRU and / or Node B of the wireless communication system. Interleaver 10 includes memory 12 including one or more stacks, controller 14, frame associated processor 16 and TrCH associated processor 22. The memory 12 indicates the position of the stack segment of the stack in the memory 12 to write the write pointer (WP) 18 and the read pointer (RP) 20 which are used to execute the write operation and the read operation, respectively. It is included. This frame association processor 16 retrieves the data stored in a particular portion of the memory 12 as indicated by the read pointer 20.

Transport blocks from a plurality of channels are time aligned with each other. Dedicated channels (DCHs) are also aligned with each other. These DCHs may only be initiated in radio frames that implement the relationship of Equation 1 below:

Connection Frame Number (CFN) mod Fi = 0

In this equation, Fi is " i " which is the TTI value of TrCh from the set {1, 2, 4, 8}. Thus, within the WTRU, all the DCHs are aligned with each other.

Common channels are also aligned with each other. Common channels include broadcast channel (BCH), paging channel (PCH), forward access channel (FACH), random access channel (RACH), uplink shared channel (USCH) and downlink shared channel (DSCH). Common channels may only be initiated on radio frames that implement the relationship of Equation 2:

System Frame Number (SFN) mod Fi = 0.

In this equation (2), Fi is " i " which is the TTI value of TrCh from the set {1, 2, 4, 8}.

If the higher layer advertises Layer 1 of the new channel configuration, the channel may be of the following four types: 1) a common shared type; 2) a dedicated type; 3) uplink type; Or 4) as appropriate for the downlink type. This channel type is used to determine in which stack the first interleaved data of a channel can be allocated. In total, there are four stacks in the memory 12. Two separate stacks are provided respectively for uplink processing and downlink processing, and two separate stacks are provided respectively for the DCH and a common shared channel. Thus, one stack is provided for the common shared TX (uplink) channel, one stack for the dedicated TX (uplink) channel, and one for the common shared receive (RX) (downlink) channel. Stacks and one stack for dedicated RX (downlink) channels. Since they are not necessarily aligned with each other, stacks for DCH and common channels are provided separately.

3 shows an exemplary allocation of data blocks to a stack of memory 12 in accordance with the present invention. Each group of transport blocks with an aligned TTI period is allocated to a stack of memory 12.

A last in first-out (LIFO) stack process is applied for the allocation and deallocation of TrCH data blocks from each stack in memory 12. Data blocks are allocated and deallocated in the stack of memory 12 depending on the TTI of each data block.

Data blocks with larger TTIs are previously allocated and deallocated later than data blocks with smaller TTIs. Thus, 80 millisecond TTI data blocks are previously allocated, deallocated later than 40 millisecond, 20 millisecond, and 10 millisecond TTI data blocks, and 10 millisecond TTI data blocks are allocated later, It is deallocated before a data block of 20 milliseconds, 40 milliseconds, and 80 milliseconds. A 20 millisecond data block and a 40 millisecond data block are allocated and deallocated in the same manner. This enables optimization of the stack, because if two aligned transport channels with the same TTI can be obtained, then the lifetime of such interleaved data begins and ends with each other in the same frame. For example, a transport block with a TTI of 40 milliseconds may start within every fourth frame to satisfy its TTI alignment constraint. Thus, the start frame and end frame for a transport block with a TTI of 40 milliseconds fall in every fourth frame. This is efficient for grouping transport blocks together into the same stack area.

Another reason that the present invention enables stack optimization is that the end of the life of the transport channel always matches the life of the lower TTI. For example, interleaved data of a 40 millisecond TTI transport channel (channel A) starts at frame 1 and ends at frame 4 (inclusive). Another channel with a 20 millisecond TTI (channel B) must be started in an odd number of frames to guarantee a TTI alignment limit. That is, channel B must start in frame 1, frame 3, or both frames. If channel B starts from frame 3, the life of channel A coincides with the end point of channel B. Thus, if channel A is deallocated, channel B is also deallocated from the stack of memory 12 at the same time.

Common channels are not aligned with DCHs (ie, a 20 millisecond DCH has the same start and end frame as a common channel with a 20 millisecond TTI). Thus, physically pulling the bits of the DCH and common channels together in the same stack results in increased partial formation. One way to solve this problem is to use separate memories for the common and dedicated channels. As described above, the present invention preferably utilizes separate stacks for the DCH and common channel, so that each stack stores only transport blocks that are aligned with each other.

Optionally, it is possible to limit the requirements for common shared channels based on previously known configurations. In particular, the forward access channel (FACH) has a case in which the data amount specified by the noted limit in TS 25.306 is never needed with respect to the number of simultaneous bits that can be received in the TTI whose data amounts coincide. In that case, the WTRU or Node B is capable of processing, thus providing a more stringent limit on the amount of data that allows the reduction of the size of the first interleaver buffer stacks.

Referring to FIG. 3, there are six channels with data blocks being transmitted, namely channels 1 through 6. These channels are aligned TTIs. Thus, they are either one of all common channels or all dedicated channels. The data blocks of channel 1 and channel 2 have a TTI of 80 milliseconds; The data block of channel 3 has a TTI of 40 milliseconds; The data block of channel 4 has a TTI of 20 milliseconds; The data blocks of channel 5 and channel 6 have a TTI of 10 milliseconds. The data blocks of channel 1 and channel 2 are the first region 12a (i.e., the "bottom" of the LIFO process) of the stack of memory 12 because the blocks have a maximum TTI. The first assigned place in the context). Next, the data block of channel 3 is allocated to the second region 12b adjacent to the region 12a in the stack of the memory 12. The data block of channel 4 is allocated to the third region 12c, and the data block of channel 5 and channel 6 is allocated to the fourth region 12d, which is the "top" of the stack of the memory 12. Part "[ie, the last allocated place in the context of the LIFO process]. In particular, although four regions 12a-12d are described herein, it will be understood by those skilled in the art that any number of larger or smaller regions may be implemented.

The data blocks are deallocated in the reverse order from the allocation of the stack of memory 12. Data blocks with the same TTI can be allocated contiguously in the same area of the stack of memory 12, while being deallocated from the stack of memory 12 simultaneously. As shown in FIG. 3, space remains in the upper portion of the stack of memory 12 to indicate that less than 100% of the available storage capacity is used in this example. In the worst case, the entire stack storage capacity can be used.

4 shows the lifetime of the transport block of FIG. 3 that transport blocks can allocate in the stack of memory 12. In particular, FIG. 3 is a snapshot of the stack of memory 12 in frame 14 of FIG. 4. Each block in FIG. 4 represents one TTI length of data that must be allocated to a particular transport channel. The transport blocks of channel 1 and channel 2 are allocated to region 12a in frame 9; The transport block of channel 3 is allocated to region 12b in frame 13; The transport block of channel 4 is allocated to area 12c in frame 13; In addition, the transport blocks of channels 5 and 6 are allocated to the region 12d in the frame 14. The data for channels 4, 5 and 6 have the same end point (frame 14) and can also be deallocated from the stack of memory 12 at the end of frame 14. At that time, it is possible that such a configuration can be changed or that new 20 millisecond or 10 millisecond TTI channels can be added. Since this may violate the TTI alignment rules given within the 3GPP TDD and FDD standards (TS 25.221 and TS 25.222), a new 40 millisecond or 80 millisecond TTI channel cannot be started in frame 15.

The present invention substantially reduces the amount of the first interleaver stack. Due to the minimal additional burden, a large reduction in stack memory capacity is achieved. Achieving this capacity reduction is important because the first interleaver buffer is the largest stack buffer in the TDD WTRU. Instead of a buffer that requires storage capacity to eight times the maximum amount of coded data that can reach 10 milliseconds, the present invention provides a maximum amount of the maximum amount of coded data that can reach 10 milliseconds. Requires twice the memory capacity.

The present invention supports shared channels, supporting the assignment of transmission data in all transmission channels in any combination. Although the WTRU may not support shared channels, the common channels have a very small transmission data size and the processing power requirement is determined by comparing the maximum total number of transmission bits in the aligned TTI for the DCH and shared channels. It is still possible to reduce one interleaver buffer stack requirement by approximately 50%. If a shared channel is taken out, the stack dedicated to the shared common channel is dramatically reduced. The maximum number of shared channel bits that can be received simultaneously is comparable to the maximum number of DCH bits that can be received simultaneously. The elimination of shared channel support allows the use of the maximum number of common channel bits as a limiting factor. Since the maximum number of common channel bits is expected to be less than the maximum number of shared channel bits, the stack portion of the shared common channel can be reduced in size.

5 is a flow diagram of a process 500 including the steps of a method for allocating data in a stack in accordance with the present invention. In step 505, a plurality of data blocks are received and interleaved from the plurality of TrCHs. This interleaved data block is stored in a memory stack (ie, a buffer). When storing the interleaved data block in a memory stack, the data block with the larger TTI is allocated before the data block with the smaller TTI (step 510). The stored data block is a read frame by frame. When deallocating an interleaved data block, the data block with the smaller TTI is deallocated before the data block with the larger TTI (step 515).

Although the present invention has been specifically illustrated and described with respect to preferred embodiments, those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit of the present invention described above.

Claims (47)

In a wireless communication system, a method for allocating and deallocating data stored in a memory stack, the method comprising: (a) receiving and interleaving a plurality of data blocks, each data block having a specified transmission timing interval (TTI); (b) storing the interleaved data blocks in a memory stack based on a designated transmission timing interval (TTI) of each data block. Including, A data block with a larger TTI is allocated to the memory stack prior to the data block with a smaller TTI, and is allocated data stored in the memory stack that is deallocated from the memory stack later than a data block with a smaller TTI. And how to deallocate. 2. The method of claim 1 wherein data blocks received from a dedicated channel and data blocks received from a common shared channel are stored in separate regions of the memory stack. 2. The method of claim 1 wherein the data block received from an uplink channel and the data block received from a downlink channel are stored in separate regions of the memory stack. 2. The method of claim 1 wherein each block of data is allocated for a particular transport channel (TrCH). 2. The method of claim 1 wherein the wireless communication system is a time division duplex (TDD) communication system. 2. The method of claim 1 wherein the wireless communication system is a frequency division duplex (FDD) communication system. The method of claim 1, wherein data blocks having the same TTI are grouped together. In a wireless communication system, an interleaver for allocating and deallocating data stored in a memory stack, (a) a processor for receiving and interleaving a plurality of data blocks, each data block having a designated transmission timing interval (TTI); (b) a memory comprising at least one memory stack Including, The processor stores the interleaved data blocks in the memory stack based on the transmission timing interval TTI of each data block such that a data block with a larger TTI is earlier than the data block with a smaller TTI. An interleaver for allocating and deallocating data stored in a memory stack that is allocated to a memory stack and is deallocated from the memory stack later than a block of data having a smaller TTI. 10. The interleaver of claim 8 wherein data blocks received from a dedicated channel and data blocks received from a common shared channel are stored in separate regions of the memory stack. 10. The interleaver of claim 8 wherein the data block received from the uplink channel and the data block received from the downlink channel are stored in separate regions of the memory stack. 10. The interleaver of claim 8 wherein each data block is allocated for a particular transport channel (TrCH). 10. The interleaver of claim 8 wherein the wireless communication system is a time division duplex (TDD) communication system. 10. The interleaver of claim 8 wherein the wireless communication system is a frequency division duplex (FDD) communication system. 10. The interleaver of claim 8 wherein data blocks having the same TTI are grouped together and aligned. 9. The memory of claim 8, wherein the memory comprises a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated down. An interleaver for allocating and deallocating data stored in the memory stack comprising a fourth memory stack for the link channel. 10. The memory stack of claim 8 wherein the memory includes a write pointer WP and a read pointer RP used to indicate the location of a segment on the memory stack to perform a write operation and a read operation, respectively. Interleaver to allocate and deallocate stored data. 9. The method of claim 8, wherein the data blocks are received by the processor such that the memory stack is allocated for each frame of the TTI of the transport channel for up to eight frames. Interleaver. In a wireless communication system, a wireless transmit / receive unit (WTRU) for allocating and deallocating data stored in a memory stack, (a) a processor for receiving and interleaving a plurality of data blocks, each data block having a designated transmission timing interval (TTI); (b) a memory comprising at least one memory stack Including, The processor stores the interleaved data blocks in the memory stack based on the transmission timing interval TTI of each data block such that a data block with a larger TTI is earlier than the data block with a smaller TTI. A wireless transmit / receive unit for allocating and deallocating data stored in a memory stack that is allocated to a memory stack and is deallocated from the memory stack later than a block of data having a smaller TTI. 19. The WTRU of claim 18 wherein a block of data received from a dedicated channel and a block of data received from a common shared channel are stored in separate regions of the memory stack. unit. 19. The WTRU of claim 18 wherein a block of data received from an uplink channel and a block of data received from a downlink channel are stored in separate regions of the memory stack. . 19. The WTRU of claim 18 wherein each data block is allocated for a particular transport channel (TrCH). 19. The WTRU of claim 18 wherein the wireless communication system is a time division duplex (TDD) communication system. 19. The WTRU of claim 18 wherein the wireless communication system is a frequency division duplex (FDD) communication system. 19. The WTRU of claim 18 wherein data blocks having the same TTI are grouped together and aligned. 19. The system of claim 18, wherein the memory comprises a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated down And a fourth memory stack for the link channel, the radio transceiver unit for allocating and deallocating data stored in the memory stack. 19. The memory stack of claim 18 wherein the memory includes a write pointer WP and a read pointer RP used to indicate the position of a segment on the memory stack to perform a write operation and a read operation, respectively. A radio transceiver unit for allocating and deassigning stored data. 19. The method of claim 18, wherein the data blocks are received by the processor such that the memory stack is allocated for each frame of the TTI of the transport channel for up to eight frames. Wireless transceiver unit. In a wireless communication system, a base station for allocating and deallocating data stored in a memory stack, (a) a processor for receiving and interleaving a plurality of data blocks, each data block having a designated transmission timing interval (TTI); (b) a memory comprising at least one memory stack Including, The processor stores the interleaved data blocks in the memory stack based on the transmission timing interval TTI of each data block such that a data block with a larger TTI is earlier than the data block with a smaller TTI. A base station for allocating and deallocating data stored in a memory stack that is allocated to a memory stack and is deallocated from the memory stack later than a block of data having a smaller TTI. 29. The base station of claim 28 wherein data blocks received from a dedicated channel and data blocks received from a common shared channel are stored in separate regions of the memory stack. 29. The base station of claim 28 wherein data blocks received from an uplink channel and data blocks received from a downlink channel are stored in separate regions of the memory stack. 29. The base station of claim 28 wherein each data block is allocated for a particular transport channel (TrCH). 29. The base station of claim 28 wherein the wireless communication system is a time division duplex (TDD) communication system. 29. The base station of claim 28 wherein the wireless communication system is a frequency division duplex (FDD) communication system. 29. The base station of claim 28 wherein data blocks having the same TTI are grouped together and aligned. 29. The memory of claim 28, wherein the memory comprises a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated down. And a base station for allocating and deallocating data stored in the memory stack comprising a fourth memory stack for the link channel. 29. The memory stack of claim 28 wherein the memory includes a write pointer WP and a read pointer RP used to indicate the position of a segment in the memory stack to perform a write operation and a read operation, respectively. A base station for allocating and deallocating stored data. 29. The method of claim 28, wherein the data blocks are received by the processor such that the memory stack is allocated for each frame of the TTI of the transport channel for up to eight frames. Base station. In a wireless communication system, an integrated circuit (IC) for allocating and deallocating data stored in a memory stack, (a) a processor for receiving and interleaving a plurality of data blocks, each data block having a designated transmission timing interval (TTI); (b) a memory comprising at least one memory stack Including, The processor stores the interleaved data blocks in the memory stack based on the transmission timing interval TTI of each data block such that a data block with a larger TTI is earlier than the data block with a smaller TTI. And allocating and deallocating data stored in a memory stack that is allocated to a memory stack and is deallocated from the memory stack later than a block of data having a smaller TTI. 39. The integrated circuit of claim 38, wherein data blocks received from a dedicated channel and data blocks received from a common shared channel are stored in separate regions of the memory stack. . 39. The integrated circuit of claim 38 wherein the data block received from an uplink channel and the data block received from a downlink channel are stored in separate regions of the memory stack. 39. The integrated circuit of claim 38 wherein each block of data is allocated for a particular transport channel (TrCH). 39. The integrated circuit of claim 38 wherein the wireless communication system is a time division duplex (TDD) communication system. 39. The integrated circuit of claim 38, wherein the wireless communication system is a frequency division duplex (FDD) communication system. 39. The integrated circuit of claim 38, wherein data blocks having the same TTI are grouped together and aligned. 39. The memory of claim 38, wherein the memory comprises a first memory stack for a common shared uplink channel, a second memory stack for a dedicated uplink channel, a third memory stack for a common shared downlink channel, and a dedicated down. And a fourth memory stack for the link channel, the integrated circuit for allocating and deallocating data stored in the memory stack. 39. The memory stack of claim 38 wherein the memory includes a write pointer WP and a read pointer RP used to indicate the position of a segment in the memory stack to perform a write operation and a read operation, respectively. Integrated circuit for allocating and deallocating stored data. 39. The method of claim 38, wherein the data blocks are received by the processor such that the memory stack is allocated for each frame of the TTI of the transport channel for up to eight frames. Integrated circuit.

Images