KR20070017339A - Method for detecting resistive-open defects in semiconductor memories - Google Patents

Abstract

The present invention relates to a method for detecting a delay failure in a semiconductor memory. In the exemplary embodiment 100, address bits and data bits are generated 110 in accordance with a check pattern suitable for checking a semiconductor memory. The address bits and the data bits are verified 120 and then provided to input ports 130 of the semiconductor memory. The memory operations 140, 150, 160, 170 are then started such that the time interval between the provision of address bits and data bits and the start of the memory operation is approximately equal to the operating clock cycle of the semiconductor memory. This timing allows both the address decoder and the read / write circuits to be properly forced in time, enabling detection of small delay failures.

Description

METHOD FOR DETECTING RESISTIVE-OPEN DEFECTS IN SEMICONDUCTOR MEMORIES}

The invention is filed on March 26, 2004 and claims priority of provisional patent application No. 60 / 556,706, entitled "A New Effective Method for Resolving Resistance-Open Defects for Semiconductor Memory." The entirety of which is incorporated by reference.

TECHNICAL FIELD The present invention relates to the field of inspection of semiconductor memories, and more particularly to a method for resistive-opening defects in semiconductor memories.

Systematic and automatic inspection of integrated circuits is becoming increasingly important. The density of new generation integrated circuit components actually increases the number of system functions and the clock speed. Integrated circuits have reached a level of complexity and speed in which processing defects can no longer be detected, even with the most expensive and expensive conventional inspection procedures. However, customers will not allow hidden defects in products to appear in operation and use, for example, making life support systems or aircraft control systems unreliable.

Nowadays, embedded semiconductor memories operate at high speed with clock cycles of up to 2ns for SRAM, or even shorter clock cycles for new generation CMOSs with critical dimensions of around 90 nanometers. The test of the embedded semiconductor memory is generally performed by a tester using a built-in self test (BIST) or a scan test mode. In a BIST or tester, successive test patterns are generated to perform read and write operations in memory in accordance with a predetermined march test. It is as if the test is well known in the art and is often regarded as a sufficient test for semiconductor memory.

Resistive open faults not only cause static faulty behavior of easily detectable semiconductor memory, but also cause dynamic faults known as "slow rise" or "slow fall" in the data path or in the address path. Depending on the resistance of the defect (defect size), the delays vary significantly. Large delays that lead to static disturbances are easily detected. Detection of small delays corresponding to small sized defects requires fast inspection using BIST or scan inspection. Ideally, semiconductor memories need to be checked at the operating frequency. If the semiconductor memory is not inspected at the operating frequency, small resistive open defects are not detected even if the correct test patterns are applied. However, fast BIST is not easily fused to memory placement because of the delay required for the BIST's output analyzer, the additional time required for synthesis, and the additional area required for fast BIST. Increasing the speed of BIST means substantially increasing the area for BIST, which is unacceptable for most applications. Furthermore, scanning the embedded semiconductor memory using scan scan mode requires additional scan time due to the scan-in and scan out of the data being continuously performed, thus for large memories with multiple pins. Inspection time is substantially increased.

As modern manufacturing processes change from aluminum based connections to copper based connections, resistive open defects are becoming major defects. For example, resistive metal bridging in aluminum processes is more dominant than resistive opening.

However, as outlined above, inspection at frequencies below the operating frequency of the semiconductor memory is called a delay failure that is not detected, such as those demonstrated by resistive open faults, resistive bridging, and capacitive coupling. Produces results.

There is a need to provide a method for reliably detecting delay failures in a new generation of semiconductor memory using a BIST or tester operating at a frequency lower than the operating frequency of the semiconductor memory.

The present invention has been found to be a useful method for detecting resistive open defects in semiconductor memories. These resistive open faults are delay delays that lead to slow rise and slow fall in memory address decoders, precharge circuits, write data lines, global inputs / outputs, and also in the memory cell matrix. Reveal defects.

Through a built-in self test (BIST) or test that operates at a frequency lower than the operating frequency of the semiconductor memory, the present invention provides a reliable method for detecting these delay failures.

In one embodiment according to the present invention, a method exists for checking for delay failures in a semiconductor memory. The method includes generating address bits and data bits in accordance with a check pattern suitable for checking a semiconductor memory. The address bits and data bits are verified. The address bits and data bits are provided to input ports of the semiconductor memory. The memory operation starts in accordance with the address bits, where the time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to the operating clock cycle of the semiconductor memory.

In another embodiment according to the present invention, a method is further provided for checking for delay failures in a semiconductor memory. The method includes generating address bits and data bits in accordance with a check pattern suitable for checking a semiconductor memory. The address bits and data bits are verified. These address bits and data bits are provided to the input pods of the semiconductor memory. According to the address bits, the data bits are written to the semiconductor memory, wherein the time interval between the provision of the address bits and the data bits and the start of the write operation is approximately equal to the operating clock cycle of the semiconductor memory. According to the check pattern, second address bits are generated. The second address bits are verified. The second data bit output of the semiconductor memory is read in accordance with the second address bits, wherein the time interval between the provision of the address bits and the start of the read operation is approximately equal to the operating clock cycle of the semiconductor memory. The second data bits are compared with predetermined data to obtain a comparison result, and if the comparison indicates a match, then the operation indicates that there was no failure.

In another embodiment according to the present invention, a check circuit for detecting delay failures in a semiconductor memory is provided, which circuit includes an address for generating address bits and data bits in accordance with a check pattern suitable for checking a semiconductor memory. It includes a data generating circuit. There is a verify circuit for verifying address bits and data bits. The connection circuit is for communicating with the semiconductor memory to provide the address bits and the data bits to the semiconductor memory. The timing circuit is adapted for timing the provision of the address bits and the data bits and the start timing of the memory operation such that the time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to the operating clock cycle of the semiconductor memory. To provide a timing signal.

The above summary of the present invention is not intended to represent each disclosed embodiment or every point of the present invention. Other details and exemplary embodiments are provided in the following figures and detailed description.

The invention will be more fully understood upon a closer examination of the following detailed description of various embodiments of the invention in conjunction with the accompanying drawings.

1 is a flowchart of a memory test according to an embodiment of the present invention.

2 is a diagram schematically showing an address and data setting time in a BIST.

3 is a diagram schematically showing simulation results for semiconductor memory test.

4 is a diagram schematically showing simulation results for semiconductor inspection with injected open defects in the least significant bit of the X address decoder.

FIG. 5 is a diagram schematically showing an enlarged portion of the diagram shown in FIG. 4. FIG.

6 is a schematic diagram showing simulation results of semiconductor inspection using the method according to the invention.

In the following the invention will be described in connection with BIST for simplicity. As will become evident, the present invention may also be implemented using a checker in scan check mode.

The frequency of BIST has a great influence on the detection of delay failure. The fast check improves the detection of delay failures, for example by detecting small delay failures caused by resistive open faults. However, the implementation of BIST at high test frequencies is not feasible for most applications.

The BIST generates data with the corresponding address, and executes the serial write and read operations in increasing and decreasing address order. In the case of a read operation, the BIST's output analyzer compares the read data with predetermined logic values. If the data read is consistent with the logic values, then the memory is fault free, otherwise the memory is faulty. See FIG. 2. 2 shows waveforms of data and address generations 221, 231 associated with the signal provided by the check clock CL. The address and data set time is defined as the time between address generation 222 and 223 and data generation 232 and 233 and the positive edge of the check clock CL.

The processing step 100 of the BIST is shown in FIG. As a march test, the BIST generates an address and data background 110. The BIST maintains 120 the state of the memory so that the data bits and the address bits are valid. The address and data background are passed to the memory input 130. Memory operation is started 140 using the positive and negative edges of the check clock. The memory operation can be read or written. Depending on the write enable signal, the data background may be written to or read from the memory (160). The read data is compared with predetermined logical values (170).

The above steps are repeated depending on the complexity of the test pattern and the memory size. The end of the test is reported by the BIST when a ready signal is sent with a second flag indicating no fault or fault of the device under test.

2 shows waveforms of address generation 230 and data generation 220 together with memory clock CL 210. The set times 225 and 235 for the address and data are the time between the address and data background generations 221 and 231 and the positive / negative edges of the clock (hold times 222 and 232 and the data valid interval 223, 233).

In general, addressing and data generation are performed at a frequency lower than the operating frequency of the present semiconductor memory. Delay faults are therefore hidden when the test patterns (address bits and data bits) are passed to the memory input for a fairly long time before the start of the memory operation (positive / negative edge of the clock signal). A BIST operating at 50 MHz generates address bits and data bits, and in the case of a write operation, 20 ns is needed for data comparison for the output analyzer. Therefore, approximately 10 ns is needed to generate and pass a set of address bits and data bits to memory inputs. For example, if the semiconductor memory operates at clock cycles of 2 ns, and the address bits and data bits are delivered at approximately 10 ns before the positive / negative edge of the clock signal, the peripheral circuitry of the memory may be a positive / negative edge of the clock signal. It is already substantially stable before. Therefore, a delay fault caused by a defect in the memory peripheral is not detected during the application of the test pattern due to a delay of 10 ns before the positive / negative edge of the clock signal that indicates the delay fault.

Today's memories are self-timed, i.e., an internal clock for controlling read / write operations is generated based on the positive / negative edge of the external clock signal. Self-timing techniques prevent incomplete read / write operations from occurring. To check for delay failures, the state of the memory circuit before the positive / negative edge of the internal clock is very important. Small delay faults are detected when the state of the memory circuit is not yet stable due to the delay fault. When the positive / negative edge of the external clock signal is correct, the internal clock signal of the memory is generated and the memory circuit is still not stable yet. Thus, delay failure is detected with a strong impact on memory action. Therefore, the time interval separating the transfer to the positive / negative clock edge and the memory input is very important. If the time interval between the provision of address bits and data bits and the positive / negative clock edge is large compared to the memory clock cycle, the address decoder, write circuit, sense amplifier, and precharge and discharge circuits read / write the positive / negative clock edge. It is already stable before initiating the action.

Referring to FIG. 3, a simulation result 300 is shown for a test of a memory with pins q [0, .., 5] of six outputs 320. The memory operates at clock cycles of 2ns, during which time the BIST performs a test as if at 50MHz (clock cycles of 20ns). Thus, the address and data setting time is approximately 10 ns. The output pin 320 and the clock 310 are plotted.

4 is performed under the same conditions with an injected open defect at the least significant bit of the X address decoder. This open defect results in the slow rise failure indicated in waveform 415 of the V (a_2_open) plot. The slow lift 425 can be seen more clearly in the enlarged portion shown in FIG. 5. Pins (a_2_) 410 reach a logic value of 1 with a delay of 5 ns while the memory is operating at clock cycles of 2 ns. However, this defect is not detected when the BIST operates at a frequency lower than the operating frequency of the semiconductor memory. Referring to FIG. 5, a slow rising defect 425 is magnified at coordinate 500, and pins a_2 510 are pins without resistive defects. Pin (a_2_open) 520 reaches logic 1 after 5 ns.

In a method for detecting delay disturbances in a semiconductor device in accordance with an embodiment of the present invention, the time between the transfer of address bits and data bits to a memory input and the start of a memory operation shifts the positive / negative clock edge. And by verifying address and data for detecting delay failures.

In another method for detecting delay disturbances in a semiconductor memory according to the present invention, data bits and address bits are generated according to a check pattern, such as a check. Address bits and data bits are then verified. After verification, the address bits and data bits are passed to memory inputs. The positive / negative edge of the check clock initiates a memory operation (read or write) in accordance with the write enable signal. The transfer of address bits and data bits and the start of memory operation are timed such that the time interval between these transfers and start is approximately equal to the operating clock cycle of the semiconductor memory. The appropriate time interval is obtained by proper timing of address and data verification, or alternatively by proper timing of the positive / negative edge of the check clock. In the case of a read memory operation, the data bits are read from the memory and compared with a predetermined logic value. The above steps are repeated by generating data bits and address bits and executing, for example, successive write and read operations in increasing or decreasing address order. In the case of a memory without a delay failure, the read data bits coincide with predetermined values, while for example if one data bit does not coincide with the predetermined value, the memory is determined to be faulty.

The method for detecting delay faults in semiconductor memories is very advantageous for enabling delay fault detection using BIST operating at frequencies below the operating frequency of the semiconductor memory. For example, a semiconductor memory operating at 200 MHz needs to be checked at the same frequency, otherwise smaller delay disturbances are not detected. Examining semiconductor memory at 50 MHz or even 150 MHz using conventional BIST does not make it possible to detect small delay disturbances. For the transfer of address bits and data bits and the start of memory operation, the timing between them is approximately equal to the operating clock cycle of the semiconductor memory, so that both the address decoder and the read / write circuit are properly timed. Forced to enable detection of small delay disturbances. Furthermore, the method according to the present invention is also applicable to checking semiconductor memories of self timing using the positive / negative edge of the internal memory clock signal.

This eliminates the need to operate the BIST at the operating frequency of the memory, effectively reducing the BIST area of the memory chip. In one embodiment, the BIST operates at the maximum possible frequency (in the region of the maximum possible trade-off), and the frequency gap between the BIST frequency and the operating frequency of the memory is then transferred to the address bits and data bits and the memory operation. Compensation is made by appropriate timing for the start of.

6 illustrates a simulation similar to the simulation of FIG. 5 with timings arranged in accordance with one embodiment of the present invention. This simulation 600 shows that a delay failure is detected when the proper timing for the delivery of address bits and data bits and the start of memory operation is applied. Memory outputs q_1 and q_2 provide an unexpected logic value 620 at 50ns, while all memory outputs provide an invalid logic value 630 at 240ns.

The method according to the invention is easily implemented in conventional BIST circuits or checker circuits, enabling the operation of the BIST or checker to be at a lower frequency than the operating frequency of the memory under test, while enabling the detection of small delay disturbances.

As defined in the appended claims, many other embodiments of the invention will be apparent to those skilled in the art without departing from the spirit and scope of the invention.

Claims (19)

A method 100 for detecting delay failures in a semiconductor memory, the method comprising: Providing (110, 120) address bits and data bits in accordance with a test pattern suitable for testing the semiconductor memory; Providing (130) the address bits and data bits to input ports of the semiconductor memory; Starting the memory operation according to the address bits (140, 150), The time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to the operating clock cycle of the semiconductor memory. A delay failure detection method of a semiconductor memory. The method of claim 1, Providing the address bits and data bits, Generating address bits and data bits; Verifying the address bits and data bits before providing the address bits and data bits to input ports of the semiconductor memory. A delay failure detection method of a semiconductor memory. The method of claim 1, And the memory operation includes writing the data bits to the semiconductor memory. The method of claim 3, wherein And wherein said memory operation includes reading data bits from said semiconductor memory (160). The method of claim 4, wherein And repeating the steps according to the check pattern. The method of claim 5, Comparing the read data with predetermined data to obtain at least one comparison result (170); If the at least one comparison indicates a match, further comprising providing a signal indicating that the semiconductor memory has no fault. The method of claim 6, Wherein said time interval is determined by an appropriate timing for said address and data verification. The method of claim 6, And the time interval is determined by an appropriate timing for the start of the memory operation. The method of claim 6, The test pattern is a delay test for detecting a delay failure of a semiconductor memory. A method for detecting delay failures in a semiconductor memory, the method comprising: Providing valid address bits and valid data bits in accordance with a check pattern suitable for checking the semiconductor memory; Providing the valid address bits and valid data bits to input pods of the semiconductor memory; Writing the valid data bits to the semiconductor memory in accordance with the valid address bits—the time interval between the provision of the valid address bits and valid data bits and the start of a write operation is approximately equal to an operating clock cycle of the semiconductor memory. Same--and, Providing second valid address bits in accordance with the check pattern; Providing the second valid address bits to input ports of the semiconductor memory; Reading second data bits from the semiconductor memory in accordance with the second valid address bits—the time interval between the provision of the second valid address bits and the start of a read operation is approximately an operating clock cycle of the semiconductor memory. Is the same as-- Comparing the second data bits with predetermined data to obtain a comparison result, and if the comparison indicates a match, indicating that the operation was free of failure. The method of claim 10, Providing the valid address bits and the valid data bits comprises generating address bits and data bits, and verifying the address bits and data bits to provide the valid address bits and valid data bits. Including, Providing the second valid address bits includes generating second address bits in accordance with the check pattern, and verifying the second address bits to provide the second valid address bits. A delay failure detection method of a semiconductor memory. The method of claim 10, And repeating the steps according to the check pattern. The method of claim 12, And the test pattern is a test. The method of claim 13, And the time interval is determined by an appropriate timing of the address and data verification. The method of claim 13, And the time interval is determined by an appropriate timing for the start of the memory operation. A check circuit for checking for delay failures in a semiconductor memory, An address and data generating circuit for generating address bits and data bits in accordance with a test pattern suitable for checking the semiconductor memory; A connection circuit for communicating with said semiconductor memory to provide said address bits and data bits to said semiconductor memory; For the provision of the address bits and data bits and the start timing of the memory operation such that the time interval between the provision of the address bits and data bits and the start of the memory operation is approximately equal to the operating clock cycle of the semiconductor memory. A timing circuit for providing a timing signal An inspection circuit for detecting a delay failure of a semiconductor memory. The method of claim 16, And a verification circuit for verifying the address bits and data bits. The method of claim 16, And a comparison circuit for comparing the read data with predetermined data to obtain a comparison result and if the comparison indicates that the operation is consistent, indicating that the operation was free of failure. The method of claim 18, And the address and data generating circuit, the verifying circuit, the connecting circuit, the timing circuit, and the comparing circuit are integrated in a chip including a semiconductor memory.

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