KR20070017312A - A dynamically reconfigurable signal processing apparatus and method for use in a high speed digital communication system - Google Patents

Abstract

A dynamically reconfigurable signal processing apparatus 158c is disclosed. This signal processing apparatus 158c includes at least one system controller 170 for detecting a state change in the high speed digital communication system 10. In one embodiment, in response to this state change, the signal processing function code is downloaded from the external memory 130 to be processed by the processor 120 of the array type in real time or near real time. In yet another embodiment, signal processing function codes for a plurality of signal processing functions are pre-stored in an array type processor 120 and are switch selectable in response to changes in system state, thereby eliminating the need to download signal processing function codes. Remove

Description

A DYNAMICALLY RECONFIGURABLE SIGNAL PROCESSING APPARATUS AND METHOD FOR USE IN A HIGH SPEED DIGITAL COMMUNICATION SYSTEM}

BACKGROUND OF THE INVENTION The present invention generally relates to dynamically reconfigurable signal processors for performing signal processing, in particular different signal processing functions in real time or near real time.

Wireless digital communication systems require a number of channel modulation and demodulation functions to be performed to transmit and receive digital data over such networks. Modulation and demodulation functions typically consist of signal processing functions, which are performed in the digital domain using well-known methods and techniques of digital signal processing (DSP). In high bandwidth radio frequency systems, the sampling rates required for DSPs are very high, so these functions have been customarily performed using common dedicated digital logic hardware (i.e., conventional DSP computer processors can achieve such high sampling rates). Cannot operate at the data rate required to support it).

More recently, some computer architectures have been developed that can perform DSP functions at the required sampling rate and are known in the art as "software radios." These so-called software-radios typically have parallel processing with a number of small but very fast computer processors working together to allow each processor to perform the required signal processing portion to perform the necessary DSP functions at the required sampling rate. It consists of an array. Such an architecture can be easily configured to operate with any of a plurality of communication schemes using various modulation and demodulation methods by simply programming the processor (s) with the necessary software to perform the appropriate function (s).

The term software radio describes radios that provide software control of various modulation technologies, wideband or narrowband operation, communication security features (such as hopping), current waveform requirements, and evolutionary standards over a wide frequency range. Used to

US Pat. No. 6,181,734, published by Palermo, discloses a software radio that operates according to a software program running on a common radio platform. An interactive waveform mode is added as a software application in a manner similar to further application to a personal computer.

Another example of this type of device is described in US Pat. No. 6,091,715 published by Vucetic regarding a hybrid radio transceiver. Vucetic points out that this type of radio transceiver provides software-limited parameters to achieve modulation and protocol type flexibility.

None of the above patents or existing techniques address the need for a software radio that can be dynamically reprogrammed in real time or near real time to perform different signal processing functions in response to detected changes in system state.

The present invention provides a dynamically reconfigurable digital signal processing device for performing different digital signal processing functions in real time or near real time in response to changes in system state. The invention also aims to implement a digital signal processing device with a reduced silicon surface area.

According to one aspect of the present invention, a system of the present invention includes at least one system controller, an array controller and an array processor. The arrayed processor includes a plurality of data processing elements, each data processing element also including a dedicated program memory for storing portions of signal processing function code for executing digital signal processing functions in response to changes in system state. Different signal processing functions may include, for example, FFT processing, correlation, digital filtering, and the like.

According to one embodiment of the invention, the signal processing device is configured to download signal processing function code data from an external memory to be stored in a dedicated program memory of each data processing element for execution, dynamically in real time or close to real time. Can be reconstructed.

According to another embodiment of the present invention, the dedicated memory of each data processing element may be configured as a plurality of memory banks. The plurality of memory banks are preloaded with signal processing function code data associated with different digital signal processing functions required at various stages of a high speed digital communication system. The arrayed processor is configured to switch in real time or near real time to a memory bank that stores the required signal processing functions in response to a change in system state. In this way, the signal processing function code data is immediately available for execution by the array processor. In this embodiment, the need to download the signal processing function code data from the external memory is eliminated.

According to another aspect of the present invention, in a digital signal processing device, a method of reconfiguring a device in real time or near real time to perform as many different signal processing functions as necessary,

(Iii) receiving input digital information at the network node,

(Ii) detecting a state change at the network node,

(Iii) identifying at least one signal processing function to be performed in response to the detected state change at the network node;

(Iii) in response to the detected change, dynamically reconfiguring signal processing device 128c in real time or near real time to perform the at least one signal processing function.

Advantageously, the signal processing device of the present invention provides functionality equivalent to that provided by a plurality of dedicated hardware and / or software signal processing devices of the prior art using less resources. In addition, the ability to dynamically reprogram the signal processing device of the present invention to perform different signal processing functions reduces silicon surface area compared to prior art circuits. This improves design productivity.

The foregoing features of the present invention will become more apparent and understandable through the following detailed description of exemplary embodiments of the invention taken in conjunction with the accompanying drawings.

1A illustrates a prior art system showing a cellular system in which the present invention may be employed.

2 is a block diagram generally illustrating the structure of a wireless network node constructed in accordance with the prior art;

3 is a more detailed view of the signal processing unit 158c of FIG. 2 configured in accordance with the prior art.

4 is a more detailed view of the signal processing unit 158c of FIG. 2 configured in accordance with one embodiment of the present invention.

5 is a more detailed view of the signal processing unit 158c of FIG. 2 configured in accordance with another embodiment of the present invention.

The present invention is generally intended to perform different signal processing functions in a high speed digital communication system in response to different criteria including but not limited to system data of a network node incorporating detected changes in a channel and / or signal processing apparatus. A technique for dynamically reconfiguring a signal processing device is provided.

The invention is illustrated with an exemplary architecture for processing data for transmission over a network. This exemplary system includes a network processor arrangement configured as a two-dimensional array, such as (M × N, N × N). However, the present invention is more generally applicable to any processor configuration in which it is desirable to provide signal processing functionally through the use of dynamic reconfigurability.

According to an embodiment of the present invention, the signal processing apparatus of the present invention may be dynamically reprogrammed in real time or near real time to perform a required signal processing function in response to a detected change in system state. This is in contrast to the prior art in which resources are organized in a form of dedicated hardware or software signal processors, dedicated only to each digital signal processing function to be performed (ie, hardwired).

The present invention has a particular application that is not exclusive to the various aspects of wireless data networking. It will be appreciated, however, that the present invention is not limited to this or any particular data networking application.

In the area of wireless data networking, network nodes must be able to perform a number of different digital communication functions, depending on the particular network standard. In many cases, however, only one digital communication function, that is, the currently active function, is used at any particular point in time. Thus, the signal processing apparatus of the present invention only needs to be configured to perform the necessary digital processing functions at that time. For example, IEEE 802.11a networking standards that support four different modulation methods, BPSK, QPSK, 16 and 64 level QAM, are well known. In the prior art, the approach of providing dedicated hardware / software for processing data in accordance with each standard is eliminated by the signal processing device of the present invention. In particular, the reconfigurable signal processing device of the present invention may be dynamically configured and reconfigured in real time or close to real time in order to operate according to each of the modulation methods described above. The required modulation method is detectable using the rate information transmitted in the packet header, which is usually transmitted after the preamble. In this way, the reconfigurable device of the present invention eliminates the need for dedicated hardware / software for each of the four modulation methods.

1 is a system diagram illustrating an exemplary cellular system 10 in which the present invention may be employed. Such cellular systems include a plurality of base stations 102, 104, 106, 108, 110, 112 serving wireless communication within each cell or sector. Such cellular systems serve wireless communications for a plurality of wireless subscriber units. These wireless subscriber units include wireless handsets 114, 118, 120, 126, mobile computers 124, 128, and desktop computers 116, 122. During normal operation, each of these subscriber units communicates with one or more base stations during handoff among base stations 102-112. Each subscriber unit 114-128 and base stations 102-112 include a signal processing apparatus configured in accordance with the present invention, as described below.

2 is a block diagram generally illustrating the structure of a wireless network node 100 constructed in accordance with the prior art. The general structure of the wireless device 100 may reside in either of the subscriber units 114-128 and the base stations 102-112 shown in FIG. Wireless device 100 includes a signal processing front end 154 that includes an antenna 160, an RF front end 152, and conventional signal processing components 158A, 158B, and 158C. The wireless device 100 also includes a plurality of host device components 160 that service all the requirements of the wireless device 100 except for RF requirements 152 and front end 154 signal processing requirements. Include.

3 illustrates in more detail the signal processing unit 158C of FIG. 2 configured according to the prior art. The signal processing device 158C consists of an input data interface 110 for receiving digital input data 9. The input data interface 110 buffers the digital input data 9 in the data buffer 23 and outputs the buffered digital data 11 to be provided to the processor array 120. Processor array 120 is implemented as a collection of processing elements 122 in a matrix configuration. The processing element 122 is preferably configured as an arrangement of primitive configurable processors designed for reconfigurable signal processing with high throughput. Each processor has a native instruction set, minimum local storage (program memory 124), and exchange data with adjacent processors using the nearest neighbor communication. Further details regarding array processing are described, for example, in "Array Processing For Channel Equalization" by G. Burns and K. Vaidyanathan of the US Philips Institute, which are incorporated herein by reference. have. The arrangement of processing elements 122 is configured to perform different signal processing functions by loading the appropriate digital processing function software into each of the memory elements 124 at appropriate times. Software for a particular signal processing function may be loaded from the memory unit 130 to the processor array 120 under the control of the array controller 140.

The signal processing device 158C receives the output data 15 processed by the processor array 120 and outputs the output data interface 160 for buffering the processed output data in the data buffer 25. It includes more. Buffered output data 13 is output to host device component 160 as needed.

Referring now to FIGS. 4 and 5, a preferred embodiment of the present invention is shown and described.

4 is a detailed view of the signal processing unit 158C of FIG. 3 in accordance with an embodiment of the present invention. As shown in FIG. 4, the signal processing unit 158C includes the elements described above in FIG. 3, and further includes a system controller 170.

System controller 170 is named first input 173 coupled to " input data " coupled to the output of input data interface 110 and " channel / system " coupled to a source of channel / system data. And a "reconstruction request" coupled to the second input 171, the third input 175 labeled "output data" coupled to the output of the output data interface 160, and the input of the array controller 140. It is shown to contain a single named output 177. It should be understood that different embodiments of the present invention may utilize different combinations of the inputs and outputs described above.

System controller 170 is then a protocol defined by (1) channel and system data received via “channel / system data” input 171, (2) dominant network standards (eg, IEEE 802.11b), The output fed back via the protocol in which the network node 100 operates, (3) the input data 9 received via the "input data" input 173 and (4) the "output data" input 175. Determine the current state of network node 100 according to one or more of the data. The current state of the network node 100 alternately instructs the signal processing unit 158C to be performed by the signal processing unit 158C at any point in time.

Array controller 140 receives external memory 130 via data line 180 to retrieve signal processing function code from memory 130 in response to a " reconfiguration request " command 177 output from system controller 170. It is shown as coupled to). The output of array controller 140 is shown coupled to an input of processor array 120 via data line 181 to output signal processing function codes from external memory 130 to processor array 120.

In operation, when system controller 170 detects a change in system state at network node 100 in accordance with one or more of the four aforementioned conditions cited above, it issues a "reconfiguration request" command 177 to array controller 140. Send to) The array controller responds to such a "reconfiguration request" command 177 by downloading the appropriate signal processing function software prestored in the external memory 130. The external memory 130 preferably stores signal processing function software for each of the digital signal processing functions to be performed by the network node 100. Stored signal processing functions may include, for example, functions associated with FFT processing, correlation, digital filtering, and the like. It is noted that the external memory 130 is preferably a nonvolatile memory or other suitable memory.

In response to the " reconfiguration request " command 177, the signal processing function software is downloaded from the external memory 130 to the processor array 120 to perform the required signal processing function at that point. In some cases, one or more signal processing functions may be required to be performed at any point in time. It should be noted that the concurrent execution of multiple signal processing functions requires that a portion of the processor arrangement 120 be dedicated to a particular signal processing function. It should also be noted that in other cases, the signal processing function to be performed may require less than the overall processing power of the processor array 120, in which case certain processing elements 122 in the array 120 may be idle.

In this embodiment, various processing elements 122 are loaded via dedicated lines 180, 181, which may be implemented as a single multiplexed data bus of processing elements 122 to program memory 124. . Those skilled in the art will appreciate that the software loading process into the program memory 124 via a single multiplexed bus 180, 181 should be performed at a sufficiently high speed to meet the timing requirements of the dominant network standard in which the network node 100 operates. Able to know. Since in some cases the allotted time may be very short, it is essential that the software loading mechanism be fast. In some embodiments, such as those shown in FIGS. 3-5, the input data and output data are shown to be buffered in the input data buffer 23 and the output data buffer 25 to ensure proper synchronization.

Once the software for the currently requested signal processing function is loaded into each program memory 124, the signal processing function is executed by the processor 120 to produce the processed output data 15, and this output data ( 15 is supplied to the output data interface 160.

According to another embodiment of the present invention, the time during which the processor array 120 is reconfigured may include a plurality of (ie, two or more) program memories 125a through 125n (see FIG. 5) each within the processor array 120. In association with the processing element 122, it can be improved by pre-storing signal processing function code data for multiple signal processing functions. In this way, the need to download signal processing function code data from an external memory such as external memory 130 is eliminated.

5 is a more detailed view of the signal processing unit 158C of FIG. 3 in accordance with the present invention. As shown in FIG. 5, the signal processing unit 158C includes the elements described above in FIG. 4. 5 further includes a plurality of dedicated program memory elements 125a through 125n associated with each processing element 122. Program memory elements 125a through 125n are banks selectable by array controller 140. That is, the array controller 140 is capable of switching from one program memory element to another program memory element in the bank at any point in time.

The multiple memory banks 125a through 125n associated with each processing element 122 are preferably preloaded, in which case each memory bank stores signal processing function code data relating to a particular signal processing function. For example, the first program memory bank 125a may be preloaded with signal processing function code data associated with the correlation signal processing function, and the second program memory bank 125b may be loaded with signal processing function code data associated with the FFT signal processing function. Can be preloaded.

An important feature of this embodiment is that each program memory is capable of substantial simultaneous access, which requires signal processing function codes that define corresponding signal processing functions without having to retrieve the signal processing function codes from the external memory 130. Pre-stored at 125a through 125n, providing significant performance advantages in terms of execution time and execution speed.

In operation, if a state change is detected, the system controller 170 switchably selects one of the preloaded program memory banks, such as bank 125j, to the array controller 140 to be performed in response to the detected state change. Instructs to save the signal processing function code associated with the signal processing function.

The ability to switch the selection of memory banks 125a through 125n provides substantial simultaneous access to the required signal processing function code. The time delay associated with downloading the function code from external memory 130 is eliminated. Thus, the reconfiguration of each processor element 122 may be performed in a time sufficient to meet the requirements of all well-known network standards.

It will be appreciated that the first embodiment can be used if it is well known in advance that the time allocated for reconfiguring the processor arrangement 120 is long enough. That is, when it is known that there is enough time to dynamically download the required function code from the external memory 130, the method of the first embodiment is sufficient.

In each of the embodiments described herein, it should be noted that the processor arrangement 120 can be treated individually as a group of processors or as an entire arrangement. In other words, if two signal processing functions are to be performed simultaneously in the processor arrangement 120, a first signal processing function, such as function A, may be performed in the first subset of processing elements 122, and the function A second function, such as (B), can be performed concurrently in the second subset of processing elements 122.

Example Application

The IEEE 802.11 wireless LAN standard represents an important exemplary application of the present invention. However, it should be noted that the present invention is not limited to this standard and can be used in many different communication standards.

According to the 802.11 standard, the "preamble" is transmitted before the "payload" (actual data) is transmitted. Signal processing requirements for the "preamble" portion required for receiver synchronization may be very different from those required for the payload portion used for data reception. The two operations occur at mutually exclusive times (ie, at any given time, a preamble or payload is received but never both at the same time). Also, a node receives or transmits data at a given time, but never happens at the same time. The signal processing device of the present invention may be configured to perform preamp processing at an appropriate time, and then may be dynamically reconfigured in real time or close to real time, to perform payload (data transmission) processing at an appropriate time. . For example, the signal processing apparatus may be initially configured as a correlator when required to process the preamble portion and subsequently reprogrammed as an FFT when required to process the payload data. It should be appreciated that the available radio resources can be optimized by dynamically reconfiguring the signal processing apparatus of the present invention in real time or near real time to perform the required special signal processing function at any point in time.

It will be apparent to those skilled in the art that the disclosed apparatus and method have numerous applications in the field of wireless data networking.

Although the invention has been described with reference to particular embodiments, it will be appreciated that many variations can be made without departing from the spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense and are not intended to limit the scope of the appended claims.

In interpreting the appended claims, the following points should be understood. In other words

a) The word "comprising" does not exclude the presence of elements or steps other than those listed in a given claim.

b) Singular expressions before an element do not exclude the presence of a plurality of such elements.

c) Any reference signs in the claims do not limit the claims.

d) Multiple "means" may be represented by the same item or by hardware or software implemented structures or functions.

e) Each disclosed element may consist of a hardware portion (eg, a separate electronic circuit), a software portion (eg, computer programming), or any combination thereof.

As noted above, the present invention is applicable to signal processing, particularly dynamically reconfigurable signal processors for performing different signal processing functions in real time or near real time.

Claims (12)

A signal processing device 158c for use in the high speed digital communication system 10, wherein the signal processing device 158c performs a predefined signal processing function, Input to receive input digital information, An array-type processor (120) configured to execute a signal processing function code using the input digital information, the function code corresponding to at least one of the predefined signal processing functions corresponding to a current system state. Processor 120, The high speed digital communication system 10 detects a change in the system state and, in real time or close to real time, applies a signal processing function code corresponding to at least one of the signal processing functions in response to the detected change in the system state. And at least one system controller (170) configured to dynamically reconfigure the arrayed processor (120) to execute. 2. The dedicated program of claim 1, wherein the arrayed processor 120 includes a plurality of data processors 122, wherein each of the data processors 122 in the arrayed processor is configured to store the signal processing function code. A memory (124), said plurality of data processors (122) operative to execute said signal processing function code stored in each dedicated program memory (124). The method of claim 2, wherein the reconfiguring of the arrayed processor 120 dynamically In response to the detected change in system state, downloading the signal processing function code corresponding to the at least one of the signal processing functions from an external memory 130, Storing at least a portion of the downloaded signal processing function code in dedicated program memory 124 of one or more of the plurality of data processors 120; and Executing the download signal processing function code in the one or more data processors 120. And a signal processing device for use in a high speed digital communication system. 2. The method of claim 1, further comprising an input data interface 110 configured to buffer the input digital input information, wherein the input data interface 110 has an output coupled to the input of the arrayed processor 120, Signal processing device for use in high speed digital communication systems. 2. The high speed of claim 1, further comprising an output data interface 160 configured to buffer digital output information output from the array processor, the output data interface having an input coupled to the output of the array processor. Signal processing device for use in digital communication systems. 3. The apparatus of claim 2, wherein the dedicated memory (124) is configured as a plurality of switch selectable memory banks (125a to 125n). The system of claim 2, wherein the at least one system controller is configured to switchably select one of a plurality of memory banks 125a-125n responsive to the detected change in system state. Signal processing device. 7. The apparatus of claim 6, wherein each of the plurality of memory banks (125a through 125n) is configured to store a signal processing function code associated with one of the predetermined signal processing functions. A method of reconfiguring a signal processing device 158c to perform a signal processing function in real time or near real time, for use in a network node of a high speed digital communication system, Receiving input digital information at the network node, Detecting a state change at the network node, Identifying at least one signal processing function to be executed in response to the detected state change at the network node; Dynamically reconfiguring signal processing device 158c to execute the at least one signal processing function in response to the detected change in system state in real time or near real time. And reconfiguring the signal processing device to perform the signal processing function in real time or near real time. 10. The method of claim 9, wherein detecting a state change at the network node comprises: (Iii) channel and system data (Ii) the protocol defined by the dominant network standard in which the network node operates, (Iii) the received input digital information and (Iii) output data associated with the signal processing device; Reconfiguring a signal processing device to perform a signal processing function in real time or near real time, in accordance with one or more criteria comprising. The method of claim 10, wherein reconfiguring the signal processing device Retrieving, from external memory 130, predetermined signal processing function code data in response to the detected change in system state; Storing the retrieved signal processing function code data in an array processor 120 of the signal processing device 158c. And reconfiguring the signal processing device to perform the signal processing function in real time or near real time. 12. The system of claim 11, wherein the arrayed processor comprises an array 120 of data processors 122, each data processor 122 in the array 120 having a dedicated memory configured to store signal processing function code data. 124), to reconfigure the signal processing device to perform the signal processing function in real time or near real time.

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