KR20070017057A - Method, Device And Program For Receiving A Data Stream - Google Patents

Abstract

According to the invention, an error correcting code comprises a data section distributed over data packets associated with and transmitted with each section, and receiving (20, 22) packets of the data stream by the interface module; Transmitting (42,50) the data stream, in packet units, from an interface module to a processing module, and incrementally calculating an error correcting code for a current data section upon receipt of data by the interface module ( 32) and if the entire section has been received, verifying the increased error correction code to deliver a section verification indicator (36).

Data Stream, Error Correction Code, Cyclic Redundancy Check (CRC)

Description

Method, Device And Program For Receiving A Data Stream}

1 and 2 illustrate reception of a transport stream according to two embodiments of the prior art.

3a and 3b illustrate the reception of a transport stream through a device and a detailed view of the device according to the invention, respectively.

4 is a flow chart of a method according to the invention.

The present invention relates to a processing upon reception of a data stream in which an error correction code is associated with each section and includes data sections distributed over data packets being transmitted.

In general, data streams are themselves distributed over data packets in sections. It is a normalized data format called MPEG, DVB-T, DBV-H, for example, in which service data streams called program specific information (PSI) and system information (SI) are distributed on data packets called base transport streams. This is the case.

Each section carries an error correcting code, such as a cyclical redundancy code or checksum called CRC to verify the integrity of the transmission. This error correction code is calculated by the emitter and sent with the data section. Upon receipt, a new error correction code is calculated from the received data section and compared with the received data section along with the data stream. Alternatively, the section carries a complementary code calculated by the emitter so that the CRC of the entire section including the complementary code is zero. Thus, upon receipt, the CRCs of the received sections are calculated and compared to determine if the sections are intact.

The datastream is received by the tuner and then transmitted to the processing module or host processor via an interface module or interface chip (IC), which is typically part of the demodulator.

In the first embodiment of the prior art shown in FIG. 1, the transport stream TS comprises four sections labeled S1, S2, S3 and S4 distributed over four packets labeled P1, P2, P3 and P4. do. This transport stream is received from the tuner by an interface chip IC which directly transmits a data packet received to the processor PRO. Thus, exactly the same stream of data is sent from the interface chip to the processor, which reassembles the sections and calculates the CRC to convey each section S1, S2, S3 and S4 with the verified CRC.

In the second embodiment of the prior art shown in Fig. 2, the same transport stream comprising four sections distributed over four packets is received by the interface chip (IC). In this embodiment, the IC passes the collected section back to the processor directly with the verified CRC to perform and send all calculations.

The first conventional embodiment consumes the same processor computation time as when the entire computation is performed by this element.

In the second conventional embodiment, the interface chip needs more memory, components and power to buffer the received data packets to reassemble the data sections and compare the CRCs.

Thus, all of the existing embodiments require expensive and power-consuming components that are not particularly suitable for processing equipment.

Accordingly, an object of the present invention is to solve a problem as described above, and an object of the present invention is to receive a data stream including a data section distributed on a data packet, which does not require too much memory and reduces power consumption. It is to solve the above problem by providing an efficient method and apparatus accordingly.

To achieve the above object, the present invention relates to a method for receiving a data stream as mentioned in claim 1 and a device accordingly as referred to in claim 8. The invention also relates to a program as mentioned in claim 13.

Due to the increased calculation of error correcting codes in this interface module, the present invention reduces the size of the memory and efficiently receives the data stream by redistributing the calculation between the interface module and the processing module.

Other features and advantages of the present invention will become apparent from the detailed description taken in conjunction with the drawings shown in the accompanying drawings.

In Figure 3a, the reception of a data stream in accordance with the present invention is shown. This data stream corresponds, for example, to DVB-H or DVB-T contained in MPEG data and is referred to as a transport stream (TS).

The depicted TS fragment comprises four sections labeled S1, S2, S3, and S4 distributed over four packets labeled P1, P2, P3, and P4. Each data section S1 through S4 corresponds to a CRC checksum and includes an error correcting code indicated by CRC1 through CRC4, respectively.

This data stream TS is received by the device 2 according to the invention. More precisely, this data stream is received by the interface module or interface chip (IC), which is labeled 4 and is part of the demodulator. The data stream is then sent to a processing module or processor PRO, indicated at 6.

The interface module 4 is configured to incrementally calculate the error correction code for the current data section with reception as described in more detail.

In the described embodiment, the data section is sent to the processing module 6 together with the CRC verified by the interface module 4. More strictly, the CRC received in each section is replaced with a flag indicating whether the section is intact, which flag is increased by verification by the CRC calculated incrementally.

Thus, some of the calculation of the CRC is made in the interface module 4 and some in the processing module 6. This allows for the use of small amounts of memory, and takes less time for the processor to calculate and saves power.

In the above-described embodiment, the interface module 4 is configured to repacket the received data packet before transmission to the processing module 6.

Thus, the interface module 4 transmits only one section of data and the processing module 6 segment of the data packet whose maximum size corresponds to the size of the data packet.

Thus, CRC verification is efficiently performed with little or no extra parts and without slowing down the processing module 5. Moreover, repackaging of data enables faster processing by the processing module and also better power management.

3A, 3B and 4, a detailed function of the function of the apparatus 2 will be described.

As shown in Fig. 3B, the interface module 4 has a receiving element indicated by reference numeral 8 connected to a buffer memory 10 whose size corresponds to the size of one data packet in the above-described embodiment. The buffer 10 is also connected to an emitter element 12 configured to transmit data to the processing module 6.

The interface module 4 also has a CRC calculation element 14, a CRC verification element 16 and a command element 18 which commands all elements of the interface module 4.

This device 2 is formed to achieve the receiving step 20 of the data packet P1 shown in FIG. 4, which is received by the receiving element 8 and buffered for the storing step 22. Is sent to 10.

Upon receipt of the data packet P1 by the interface module 4, the data is also sent to the CRC calculating element 14 for step 30 of incrementally calculating the error correcting code for the current data section S1.

Step 30 includes a subcalculation step 32 of a partial CRC code with the available data performed by the CRC calculation element 14.

Sub-step 32 is followed by a test 34 to determine if the received data is the last data set of the section.

If the test 34, which means that the entire section has been received, is positive, the method includes sub-passing 36 of the incremental error correcting code for the received data section. This code is the partial CRC calculated after receiving the last set of data from the current section.

In this step, if the end of the section has not yet been received and accordingly the test 34 is also negative, the last detection test 40 of the data packet to determine whether the received data set is the last set of data of the data packet. ) Follows.

Tests 34 and 40 are made by detecting a predetermined sequence of data forming the header or footer of each data section or data packet.

In this step, the test 40 is negative if the entire packet P1 has not yet been received. Thus, the method continues back to step 20 to receive the next data set from data packet P1.

The same step is repeated until the final set of data in the data packet P1 is received. In each loop, step 22 causes the received data set in the buffer 10 to be remembered and step 32 allows to perform an incremental calculation of the CRC for the current section.

If the test 40, which means that the entire data packet has been received, is positive, then the content release step 42 of the buffer memory 10 follows.

In step 42, the entire packet P1 is received and transmitted from the interface module 4 to the processor module 6. After the ejection in step 42, the buffer memory 10 is deleted (step 44). However, the incremented CRC is kept in memory.

The method continues by receiving the first set of data from the data packet P2 and returning to step 20 to store the set. Substep 32 is performed and some CRCs are incremented with the first set of data packets P2 still containing data from data section S1.

If the end of section S1 is detected in test 34, the method is calculated by substep 36 in which an incrementally calculated CRC is delivered.

In the step 36, the step of calculating the CRC 30 is followed by the step 46 of verifying the error correction code that has been incrementally calculated. This is done by comparing with the received error correcting code CRC1.

This verification performed by the verification element 16 provided with the incrementally calculated CRC is passed by the CRC calculation element 14 and the received CRC of the current section is passed by the receiving element 8.

In the above example, this verification 46 carries a verification indicator to indicate whether both CRCs are equal or otherwise different if the data section S1 is intact.

In step 48, the data set corresponding to the received error correcting code CRC1 stored in the buffer 10 is replaced with an indicator or a flag under the control of the command element 18.

The method also includes a step 50 of the release of the contents of the buffer memory 12 for transferring a segment of the data packet P2 containing the data from the data section S1 to the processor module 6. In this transmitted segment, the received error correction code can be replaced by a verification indicator.

Upon receipt of a data section with an invalid indicator, the processing module 6 may correct or discard the data section.

Step 50 is followed by step 52 in which the buffer memory 10 and the incrementally calculated CRC are erased.

The method continues by returning back to step 20 to receive the next data set. If the packet P2 has not been received in its entirety, the method continues by processing another set of data packets P2 that are part of the data section S2.

The data section S2 is entirely contained in the data packet P2, such that the data section S2 is sent if the last set of data is received and the test 34 is positive. As mentioned above, prior to transmission, the received CRC is replaced with a verification indicator that occurred due to the comparison performed in step 46.

Then, as shown in FIG. 3A, the remaining data of the data packet P2 is transmitted to the processing module 6 when the end of the packet P2 is detected. When the end of the data section S3 is detected, the segment of the data packet P3 is transmitted with the CRC indicator, and when the end of the data packet P3 is detected, the remaining data of the data packet P3 is transmitted. When the end of the data section S4 is detected, the remaining data of the data section S4 is transmitted along with the verification indicator accordingly.

In the above embodiment, the transmission is triggered each time the end of the section or the end of the packet is detected, so that the transmitted segment of the data packet contains data from only one data section, the size of which is at most one data. It is equal to the size of the packet.

Of course, many other embodiments are possible.

According to an embodiment, the error correcting code transmitted in the data stream may be a CRC calculated through the section or complementary code set such that the CRC of one entire section including the error correcting code may be a determined value such as zero.

In this case, the verification of the incrementally calculated CRC is compared with a predetermined value.

In another embodiment, the interface module may also cause the module to send an incremented error correcting code to the processing module, and the entire data section may receive the received error correcting code so that the processing module achieves a comparison between these two error correcting codes. Include. Advantageously, if the transmitted error correcting code is a complement code, only the incrementally calculated error correcting code is transmitted and compared to zero by the processing module.

In another embodiment, the buffer memory of the interface module is larger than the size of one data packet and thus the transmission is only triggered when the end of one data section is detected.

The method of the present invention, when executed by a processor, receives the data packet of the datastream, and upon receipt, incrementally calculates the error correction code for the current data section before transmitting the data stream to the processing module on a packet-by-packet basis. Let's do it.

Such a processor program may be formed to achieve any of the embodiments described above and may be formed on any type of electronic article and internal components thereof, such as digital television receivers, computers, laptops, portable devices, and the like.

The method, apparatus and program for receiving a data stream according to the present invention as described above may reduce the size of the memory and redistribute the calculation between the interface module and the processing module due to the increased calculation of error correction code in the interface module. There is an advantage of performing the reception efficiently.

Claims (14)

A method of receiving a data stream comprising data sections (S1, S2, S3, S4) in which error correction codes are associated with each section and distributed on data packets (P1, P2, P3, P4) transmitted together. Receiving (20,22) packets of the data stream TS by the interface module 4; Transmitting (42, 50) the data stream from the interface module to the processing module (6), in packet units, Incrementally calculating an error correcting code for the current data section upon receipt of the data by the interface module; And if the entire section has been received, verifying (36) the incrementally calculated error correction code to convey the section verification indicator. The method of claim 1, And the verifying step (36) comprises comparing the increased error correction code with a predetermined value. The method of claim 1, And said verifying step (36) comprises comparing said incremental error correcting code with said received error correcting code. The method according to any one of claims 1 to 3, And when the entire section is received, the incremental error correcting code is transmitted by the interface module to the processing module for performing the verification. The method according to any one of claims 1 to 3, The verifying step 36 is performed by the interface module and further comprises replacing the received error correcting code from the data section by the verification indicator prior to transmission to the processing module. . The method according to any one of claims 1 to 5, Repacketing the data packet received by the interface module prior to transmission to the processing module. The method of claim 6, The repacketing comprises segmenting a data packet comprising data from another section to transmit (42,50) a data packet segment comprising data from only one data section. . An apparatus for receiving a data stream comprising data sections (S1, S2, S3, S4) in which error correction codes are associated with each section and are distributed on data packets (P1, P2, P3, P4) transmitted together. An interface module 4 configured to receive packets of the data stream TS and transmit packets of the data stream on a packet basis; A processing module 6 configured to process the packet transmitted by the interface module, The interface module is configured to incrementally calculate an error correcting code for the current data section upon receipt of the data, And verifying that the error correction code has been increased and configured to deliver a section verification indicator. The method of claim 8, And the interface module is configured to transmit the increased error correction code to the processing module, and the processing module (6) is configured to perform the verification. The method of claim 8, And the interface module (4) is configured to perform the verification and replace the error correcting code received from the data section by the verification indicator. The method according to any one of claims 8 to 10, The interface module (4) is further configured to repacket the received data packet before sending the data packet to the processing module (6). The method of claim 11, The interface module 4 is configured to re-pitkit the data packet by dividing the data packet including the data of the other section to convey a segment of the data packet including the data of only one data section. . When performed by a processor, the processor Data stream TS comprising data sections S1, S2, S3, S4 with error correction code CRC associated with each section and distributed over data packets P1, P2, P3, P4 transmitted together. Receive Upon receipt of the data, an error correction code (CRC) is incremented for the current data section, And an instruction for causing the data stream to be transmitted to the processing module in packet units. The method of claim 13, And, when executed by the processor, cause the processor to verify the increased error correction code and to pass a section verification indicator.

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