KR20070017029A - Reduced crosstalk cmos image sensors - Google Patents

Abstract

The present invention relates, in particular, to a CMOS image sensor with high sensitivity and low interference at far infrared wavelengths, and to a method of manufacturing the image sensor. The CMOS image sensor includes a substrate, an epitaxial layer on the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor may also be adapted to prevent carriers generated within the substrate from moving to the epitaxial layer, at least one horizontal barrier layer between the substrate and the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer, It includes a plurality of transverse barrier layers between adjacent multiple pixels.

Description

Manufacturing method of a CMOS image sensor and a CMOS image sensor {REDUCED CROSSTALK CMOS IMAGE SENSORS}

1 is a schematic cross-sectional view of a portion of a prior art CMOS image sensor to aid in the description of the present invention;

2A illustrates a schematic cross-sectional view of a portion of a CMOS image sensor in accordance with an exemplary embodiment of the present invention;

2b schematically illustrates the function of a doping barrier in a P-type semiconductor to aid in explaining the present invention;

3 is a schematic cross-sectional view of a portion of a CMOS image sensor according to another exemplary embodiment of the present invention;

4 is a schematic plan view of the CMOS image sensor shown in FIG. 3;

5 to 12 schematically illustrate the steps of a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention;

13-15 schematically illustrate the steps of a method of manufacturing a CMOS image sensor in accordance with another exemplary embodiment of the present invention.

Complementary metal-oxide semiconductor (CMOS) image sensors suffer from reduced sensitivity and increased crosstalk in the far-red to infrared wavelength range (about 700 nm to about 1 mm). This is because the absorption depth at this wavelength is much deeper than the pixel depth. The interference increases because light impinging on the image sensor penetrates further below the silicon surface of the sensor, and electron-hole pairs occur deep within the substrate. This depth is further below the collection range of the pixels, so that photo-generated carriers can diverge freely in all directions. In a conventionally used substrate, the divergence length of electrons is about 5 mu m, and relatively electrons diverge to adjacent pixels to easily cause interference. The divergence length in the lower-doped epitaxial layer may be much longer, which can also result in severe interference with an improperly designed image sensor. In addition, the sensitivity of the CMOS image sensor in the far infrared wavelength range is reduced because a large number of deeply generated carriers are lost by recombination in the substrate.

Structures that reduce interference in CMOS image sensors are typically based on the manufacture of camera chips suitable for visible light. In general, the dopant profile of an image sensor is tailored such that a quasi-electric field in an undepleted region pushes the carrier back into the photodiode. Examples of conventional structures that reduce interference in the image sensor include providing a deep array implant, providing a thin and lightly doped layer on top of the substrate, blue and white except red pixels. Implanting a deep p + layer under the green pixel and providing any type of multi-layer structure. Such structures have some effect on reducing interference, especially at far infrared wavelengths, while also reducing the sensitivity of the image sensor.

The present invention relates, in particular, to a CMOS image sensor with high sensitivity and low interference at far infrared wavelengths, and to a method of manufacturing the image sensor. The CMOS image sensor according to the present invention comprises a substrate, an epitaxial layer on the substrate, and a plurality of pixels extending into the epitaxial layer to obtain light. The image sensor may also be adapted to prevent carriers generated within the substrate from moving to the epitaxial layer, at least one horizontal barrier layer between the substrate and the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer, It includes a plurality of transverse barrier layers between adjacent multiple pixels.

The present invention provides other features and advantages than the above or other embodiments as described above. These various features and advantages will become more apparent from the following description with reference to the accompanying drawings.

Exemplary embodiments according to the present invention provide a CMOS image sensor with high sensitivity and low interference, in particular at far-red to infrared wavelengths, and a method of manufacturing the same.

1 is a schematic cross-sectional view of a portion of a CMOS image sensor in the prior art to aid the techniques of the present invention. The CMOS image sensor, designated as reference numeral 100, is generally arranged in a substrate 102, an epitaxial layer 104 and an array on the substrate, and a plurality of pixels (only two extending into the epitaxial layer 104). Only pixels 110 and 112 are shown in FIG. 1). The substrate 102 and the epitaxial layer 104 are both made of silicon semiconductor material, but the substrate 102 is a P + semiconductor material (strongly doped P-type), and the epitaxial layer 104 is a P- semiconductor. It is made of a material (lightly doped P-type).

The pixels 110, 112 are photodiode n-wells 114, 116 and surface implant regions deposited on the photodiode n-wells 114, 116 to enhance contact with the pixels. 118 and 120, respectively. Photodiode n-wells 114 and 116 are made of N- semiconductor material (lightly doped N-type) and surface implant regions 118 and 120 are made of N + semiconductor material (strongly doped N-type). P-type semiconductor material (designated P-well 122 in FIG. 1) is provided to separate the pixels 110, 112 from each other.

As schematically shown in FIG. 1, when light 130 at a far infrared infrared wavelength (hereinafter generally referred to as an 'infrared wavelength') impinges on the pixel element 110, the light is transferred to the image sensor 100. Penetrates below the silicon surface, and an electron-hole pair is generated deep within the substrate 102. This depth is much deeper than the pixels collect, so the photo-generated carrier can diverge freely in all directions. In a conventional substrate, such as a heavily doped silicon substrate 102, the divergence length of the electrons is about 5 [mu] m, and a large number of electrons are relatively easy to diverge and cause interference with adjacent pixels, such as pixel 112. In addition, in the CMOS image sensor 100, a plurality of deeply generated carriers recombined in the substrate, which are distinguished from the carriers generated in the epitaxial layer with its own pixels, as schematically shown in FIG. The loss of sensitivity is reduced.

2A is a schematic cross-sectional view of a portion of a CMOS image sensor in accordance with an exemplary embodiment of the present invention. The image sensor is generally designated as reference numeral 200 and is similar to the CMOS image sensor shown in FIG. 1, and has a substrate 202, epitaxial layer 204 and photodiode n-wells 214, 216 and a surface. Pixels 210, 212 including implant regions 218, 220, respectively, and extending into epitaxial layer 204. Also similar to the CMOS image sensor 100 shown in FIG. 1, the substrate 202 includes a P + silicon semiconductor material, the epitaxial layer 204 includes a P− silicon semiconductor material, and photodiode n-wells. 214 and 216 are formed of an N− semiconductor material, and the surface implant regions 218 and 220 are formed of an N + semiconductor material. P-type semiconductor material (designated P-well 222) is provided to separate pixels 210, 212 from each other.

The CMOS image sensor 200 of FIG. 2A has an epitaxial layer 204 thicker than the epitaxial layer 104 (eg, a thickness of about 2 in a typical CMOS image sensor such as the image sensor 100 of FIG. 1). And deeper photodiode n-wells 214, 216 extending within epitaxial layer 204 (eg, FIG. CMOS image sensor 100 of FIG. 1 in that a typical CMOS image sensor such as image sensor 100 of 1 has a depth of about 2 μm to 10 μm, whereas the depth is about 1 μm to 2 μm. different. Thicker epitaxial layers and deeper photodiode n-wells allow penetration into the depth of depletion much lower than the surface of the pixel.

The epitaxial layer 204 is a lightly doped P-type material and below the depth of doping, the doping is gradientd to provide an electric field for moving the carrier. In addition, a horizontal barrier layer 224 is provided between the substrate 202 and the epitaxial layer 204 below the differentiated layer of the epitaxial layer. The horizontal barrier layer 224 serves to prevent carriers generated in the substrate 202 under the horizontal barrier layer from diverging toward nearby pixels causing interference.

Because the depth of the photodiode n-wells 214, 216 of the CMOS image sensor 200 increases, multiple carriers can be collected to increase the sensitivity of the image sensor. At the same time, electrons generated in the substrate 202 below the horizontal barrier layer 224 remain in the substrate and recombine. Therefore, the CMOS image sensor 200 has a high sensitivity at the infrared wavelength compared to the image sensor 100 of FIG. 1 and the interference is reduced.

FIG. 2B is a diagram schematically illustrating the action of a doping barrier in a P-type semiconductor to help explain the present invention. As shown, the semiconductor is generally designated as reference number 250 and, in fact, controls the more heavily doped region 252 which creates barrier 254 to control the activity of electrons such as electron 256. Include. In particular, as shown by arrow 258, electrons 256 may not cross barrier 254. As such, the barrier 254 can be used to prevent electrons from diverging to neighboring pixels causing interference.

In accordance with an exemplary embodiment of the present invention, the horizontal barrier layer 224 is provided by selective horizontal doping. In order to provide a very efficient barrier, very strongly boron doped layers having a thickness of about 100 kPa to about 1 μm and doped in the range of about 10 ¹⁹ / cm 3 to 10 ²⁰ / cm 3 are used. In addition, the typical thermal budget causes significant boron divergence and thus boron spreads out into the photodiode region of the image sensor, reducing the sensitivity, so that barrier layer 224 is difficult to match the thermal capacitance of a standard CMOS fabrication process. Must be able to withstand This outward divergence can reduce the amount of boron in the barrier layer and reduce its efficiency. According to an exemplary embodiment of the invention, the divergence of boron can be reduced by using a carbon barrier layer at a concentration of less than 3%.

Another problem associated with providing a horizontal barrier layer 224 is that the addition of boron and carbon reduces the lattice constant of silicon, which will limit the thickness of the barrier layer. According to an exemplary embodiment of the present invention, a thicker barrier layer can be grown by strain-compensating strains by adding Ge to reduce the lattice stress while limiting the divergence of boron. According to an exemplary embodiment of the present invention, the horizontal barrier layer 224 generally includes one or more of boron, aluminum, indium, phosphorus, arsenic, antimony, germanium, and carbon, in order to limit divergence and reduce lattice strain. do.

According to another exemplary embodiment of the present invention, by capping or encapsulating with a layer of strongly boron doped Si which provides a horizontal barrier layer on one or both sides of the thin carbon containing layer Lattice stress can be reduced while limiting the divergence of boron. It may also be capped with a Si layer doped with carbon after solid-source divergence.

3 shows a schematic cross-sectional view of a portion of a CMOS image sensor in accordance with another exemplary embodiment of the present invention. The image sensor is generally designated as reference number 300, and includes a substrate 302, an epitaxial layer 304, a horizontal barrier layer 324 between the substrate and the epitaxial layer, photodiode n-wells 314, 316. And pixels 310 and 312, each of which includes surface implant regions 318 and 320, similar to the CMOS image sensor 200 of FIG. 2A. Also similar to the image sensor 200 of FIG. 2A, the substrate 302 includes a P + silicon semiconductor material, the epitaxial layer 304 includes a P− silicon semiconductor layer, and the horizontal barrier layer 324 A layer heavily doped with boron, the photodiode n-wells 314, 316 are made of N- semiconductor material, and the surface implant regions 318, 320 are made of N + semiconductor material. P-type semiconductor material (designated as P-well 322) is provided between pixels 310 and 312.

The CMOS image sensor 300 extends to a point where the P-well 322 between adjacent pixels 310, 312 extends much deeper than the P-well 222 of FIG. 2A (eg, the image sensor 100 of FIG. 1). A depth of about 2 μm to 20 μm below the surface), and also includes a deep trench 326 in each P-well 322, while the depth in a typical CMOS image sensor is about 1 μm to 2 μm It is different from the CMOS image sensor 200 in that it is.

In particular, as provided in the CMOS image sensor 200, due to the deeper photodiode collection layer, lateral divergence within the epitaxial layer will have the effect of increasing interference. However, in image sensor 300, deep P-well 322 with trench 326 serves as a transverse barrier layer between adjacent pixels to prevent transverse divergence between the pixels. The trench may have a thickness of about 0.5 μm to 5 μm and the lateral barrier layer comprising the P-well and the trench may have a thickness of about 1 μm to 10 μm.

According to an exemplary embodiment of the present invention, the deep trench 326 is preferably formed prior to providing the P-well isolation 322. This allows boron to be injected deep into the device. Alternatively, P-doped polysilicon may be deposited as a trench-fill, followed by the release of P-dopant in the polysilicon. Other trench fills that may be used include silicon nitride and silicon dioxide. Doped SiO ₂ (borosilicate glass) can be used to provide boron.

In the image sensor 300, the depletion region from the p-n junction or n-well should not touch the trench. This is because the surface of the trench contains a surface condition, and if the depleted area touches the trench, it will generate a flow of leakage current. In fact, this is the main cause of boron emissions. Boron prevents the depletion region from the n-well from reaching the trench. Boron also aids pixel separation, as in embodiments without trenches.

4 is a schematic plan view of a portion of the CMOS image sensor shown in FIG. 3. In particular, FIG. 4 includes a plurality of pixels 402 in the CMOS image sensor 300, defining the trench 326 of FIG. 3 forming a lateral barrier layer that prevents lateral divergence between adjacent pixels. The mask 404 provided in FIG.

Therefore, CMOS image sensor 300 has a horizontal barrier layer 324 in the connection with a thicker epitaxial layer and a deeper photodiode junction, and a deeper photodiode to provide high sensitivity and reduced interference at infrared wavelengths. Provides a transverse barrier layer defined by the deep p-well 324 and trench 326 between adjacent pixels to reduce transverse divergence therebetween.

Therefore, according to an exemplary embodiment of the present invention, a thicker epitaxial layer and a deeper photodiode junction, along with one or more horizontal barrier layers between the substrate and the epitaxial layer of the image sensor, transverse between adjacent pixels. CMOS image sensors with a barrier layer in the direction provide an image sensor with increased sensitivity and reduced interference, especially in light of far infrared wavelengths. The present invention is suitable for motion detection devices such as optical mice and infrared imaging devices such as eye recognition devices, in particular using CMOS image sensors with low cost infrared light sources such as AlGaAs / GaAs of 780 nm or 840 nm, It will be appreciated that the light is not limited to the use of any particular wavelength of light or any particular device. Infrared light sources are particularly suitable for eye detection devices because the reflectance is improved by the retina and the eye can be recognized without scattering the object.

5 to 12 are schematic diagrams illustrating steps of a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention. In particular, FIGS. 5-12 illustrate steps of a method of manufacturing a CMOS image sensor having a lateral barrier layer between pixels, which does not include trenches as provided in the image sensor 300 shown in FIG. 3.

Referring first to FIG. 5, an initial silicon block 502 is first provided doped with boron as strongly as about 5E18. It will be appreciated that the present invention is not limited to boron, which is a P-type dopant. Other P-type dopants may be used including aluminum, gallium and indium. Similarly, other N-type dopants may be used, including phosphorous, arsenic and antimony. Then, a thermal oxide layer 504 having a thickness of 10,000 Å and an LTO having a thickness of 5,000 Å are grown on the silicon, and a photoresist layer 506 is applied on the oxide layer.

Referring to FIG. 6, pattern 508 develops in photoresist layer 506. As shown in FIG. 7, the oxide layer is etched 510 as shown, and the photoresist layer 506 is then stripped as shown in FIG. 7.

Implant oxide 512 is grown as shown schematically in FIG. 8. This will then form a step inside the silicon after the epitaxial layer has been applied. A large amount of boron is then implanted with a plurality of energies. This allows boron to penetrate at different depths 514, thus forming a transverse divergence barrier. Implant amounts and energies according to an exemplary embodiment of the present invention are as follows:

Energy 30 kev Dose 2.9E14

Energy 60 kev Dose 5.8E14

Energy 90 kev Dose 6.4E14

Energy 120 kev Dose 7.7E14

5.Energy 180 kev Dose 1.15E15

6.Energy 240 kev Dose 1.34E15

It should be appreciated that higher energy implants can be made through implants of boron ionized twice at half the energy level.

A high temperature heat cooling and implant divergence 516 is then performed as schematically shown in FIG. 9. The induction recipe of the buried layer according to an exemplary embodiment of the present invention is as follows:

1. Load at nitrogen at 850 ℃

2. Raise by 5 ℃ per minute to 1000 ℃ in nitrogen.

3. Anneal for 90 minutes at 1000 ° C in nitrogen

4. Raise 3 ° C. per minute to 1125 ° C. in nitrogen.

5. Run for 220 minutes at 1125 ℃ in nitrogen and 2.5% oxygen

6. Rise 3 ° C. per minute to 1000 ° C. in nitrogen

7. Anneal for 240 minutes at 1000 ° C. in nitrogen.

8. Raise 3 ° C. per minute to 850 ° C. in nitrogen.

9. Push wafers into nitrogen

Oxides are then removed as shown in FIG. 10 and p-epitaxial layer 518 is grown as shown in FIG. After processing, the transverse barrier layer (lateral doping barrier) 520 diverges as shown in FIG. 12. Upward expansion 522 aids in the bondage of the former.

13 to 15 are schematic diagrams illustrating steps of a method of manufacturing a CMOS image sensor according to another exemplary embodiment of the present invention. In particular, FIGS. 13-15 illustrate a CMOS image comprising both a horizontal barrier layer between a substrate and an epitaxial layer of an image sensor and a lateral barrier layer between adjacent pixels in an image sensor according to an exemplary embodiment of the invention. The steps of the manufacturing method of the sensor are schematically shown.

First, as shown in FIG. 13, a very heavily doped horizontal barrier layer (> 1e19B) 604 is formed over the top of the heavily doped silicon substrate (˜5e18B) 602. An epitaxial layer 606 is then provided over the horizontal barrier layer 604 with appropriately anchored or differential doping. The differential doping profile will provide an electric field that moves the carriers upwards and improves collection efficiency.

The fabrication process of the CMOS image sensor with the transverse barrier layer described above with reference to FIGS. 5-12 is performed to provide the transverse barrier layer 610 in the epitaxial layer 606 as shown in FIG. do. Finally, the lightly doped photodiode epitaxial layer 612 is grown as shown in FIG. 15 to complete the image sensor.

While the foregoing description constitutes exemplary embodiments in accordance with the present invention, modifications may be made in various ways without departing from the scope of the present invention. By way of example, while a method of manufacturing a CMOS image sensor has been described in an embodiment according to the present invention, the image sensor according to the present invention may be manufactured in a number of different ways without departing from the scope of the present invention. In addition, certain properties of the CMOS image sensor described herein may be modified in various ways without departing from the present invention. By way of example, the image sensor described herein can be fabricated using the opposite doping types, namely n + substrate, n- epitaxial layer, n-well blocking, p-well pixels and p + contact. The barrier layer in such an image sensor will be n +. In general, the term "CMOS image sensor" as used herein is intended to include any image sensor that can be manufactured in a CMOS process that is compatible with CMOS electronics and can be integrated.

As the exemplary embodiments of the present invention can be modified in various ways, it is to be understood that the invention is limited as required by the scope of the claims set out below.

The present invention provides a CMOS image sensor with high sensitivity and low interference, especially at far infrared wavelengths.

Claims (22)

Substrate, An epitaxial layer on the substrate, A plurality of pixels extending into the epitaxial layer for receiving light, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. A plurality of transverse barrier layers between a plurality of adjacent pixels. CMOS image sensor. The method of claim 1, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. And the plurality of transverse barrier layers between the adjacent plurality of pixels comprises at least a horizontal barrier layer. CMOS image sensor. The method of claim 2, The horizontal barrier layer comprises very heavily doped silicon CMOS image sensor. The method of claim 3, wherein The horizontal barrier layer comprises at least one of boron, aluminum, gallium, indium, phosphorus, arsenic, antimony, germanium and carbon CMOS image sensor. The method of claim 3, wherein The horizontal barrier layer is encapsulated into a carbon containing layer on one or both sides. CMOS image sensor. The method of claim 3, wherein The horizontal barrier layer has a thickness of about 100 microns to about 1 micron. CMOS image sensor. The method of claim 2, The epitaxial layer has a thickness of about 2 μm to about 20 μm, each of the plurality of pixels including a well portion extending into the epitaxial layer to a depth of about 1 μm to about 15 μm. CMOS image sensor. The method of claim 7, wherein The doping of the epitaxial layer is gradient below the depth depth to provide an electric field for moving the carriers. CMOS image sensor. The method of claim 1, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. The plurality of transverse barrier layers between the plurality of adjacent pixels comprises at least a plurality of transverse barrier layers. CMOS image sensor. The method of claim 9, Each of the plurality of lateral barrier layers includes a deep P-well between adjacent pixels extending into the epitaxial layer to a depth of about 2 μm to about 20 μm. CMOS image sensor. The method of claim 10, Each of the plurality of transverse barrier layers further comprises trenches in the deep P-well CMOS image sensor. The method of claim 11, The trenches in the plurality of transverse barrier layers are filled with at least one of polysilicon, silicon oxide and silicon dioxide. CMOS image sensor. The method of claim 1, The CMOS image sensor includes at least one horizontal barrier layer between the substrate and the epitaxial layer and transverse of the electrons in the epitaxial layer to prevent carriers generated in the substrate from moving to the epitaxial layer. A plurality of transverse barrier layers between the plurality of adjacent pixels to prevent directional divergence. CMOS image sensor. The method of claim 1, The light includes light of a far infrared ray wavelength CMOS image sensor. Substrate, An epitaxial layer on the substrate, A plurality of pixels, each of which acquires light and extends into the epitaxial layer, A horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer; A plurality of transverse barrier layers between the plurality of adjacent pixels to prevent transverse divergence of electrons in the epitaxial layer. CMOS image sensor. The method of claim 15, The horizontal barrier layer comprises very heavily doped silicon CMOS image sensor. The method of claim 16, Doping of the epitaxial layer is gradientd below the depth of depletion to provide an electric field for moving carriers. CMOS image sensor. The method of claim 15, Each of the plurality of transverse barrier layers includes a deep P-well between adjacent pixels extending into the epitaxial layer to a depth of about 2 μm to about 20 μm, and a transverse trench in each of the deep P-wells. Containing CMOS image sensor. The method of claim 15, The light includes light of a far infrared ray wavelength CMOS image sensor. A method of manufacturing a CMOS image sensor comprising a substrate, an epitaxial layer on the substrate, and a plurality of pixels extending into the epitaxial layer, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. Forming a plurality of lateral barrier layers between adjacent plurality of pixels; Method of manufacturing a CMOS image sensor. The method of claim 20, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. Forming a plurality of lateral barrier layers between a plurality of adjacent pixels, Forming a horizontal barrier layer using very heavily doped silicon Method of manufacturing a CMOS image sensor. The method of claim 20, At least one horizontal barrier layer between the substrate and the epitaxial layer to prevent carriers generated within the substrate from moving to the epitaxial layer, and to prevent lateral divergence of electrons in the epitaxial layer. Forming a plurality of lateral barrier layers between a plurality of adjacent pixels, Forming a plurality of transverse barrier layers comprising a deep P-well and transverse trenches within the P-wells Method of manufacturing a CMOS image sensor.

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