KR20070016168A - Usb eye pattern test mode - Google Patents

Abstract

The USB transceiver in the digital system stores a special test mode that, when enabled, causes the USB eye pattern test data signal waveform, such as a continuous stream of USB state transitions (as defined by the USB specification) to be transmitted to the USB transceiver. It is transferred to the USB data line connected to it. A typical test device can be coupled to a USB data line to monitor the characteristics of the signal. If a circuit change occurs for a digital system, this result can be easily measured. If the USB eye pattern test data signal waveform characteristic on the USB data line of the digital system is good, the special test mode is stopped and the USB transceiver starts to operate as a normal USB device.

USB, eye pattern, test

Description

Universal Serial Bus Eye Pattern Test Mode {USB EYE PATTERN TEST MODE}

TECHNICAL FIELD The present invention relates to digital systems and, more particularly, to testing universal serial bus (USB) interfaces in digital systems.

The USB specification requires very strict control over the transmission and reception of electrical signals on USB cables. The USB Interface Forum (www.usbif.org) presents special test equipment and methods used to verify the integrity of USB signals (USB IF test). These USB IF tests are time consuming and involve expensive data acquisition systems.

Thus, there is a need for a simple, low-cost test for preliminary verification that can be completed early on USB operation to help ensure the success of the initial pass design of more complex and expensive USB IF tests. .

The present invention provides a method for introducing a USB board state transition of a circuit board and a conventional test apparatus for analyzing USB eye pattern signal characteristics for USB high-speed, USB full-speed, and / or USB low-speed operation. By providing a simple method that can be used, it is possible to overcome the above problems as well as problems in the existing technology.

According to one embodiment of the invention, the special test mode is stored in the USB transceiver of the digital system, and when the special test mode is activated, a continuous stream of USB state transitions such as, for example, a USB eye pattern test data signal waveform ( USB data lines are provided as defined by the USB specification. These signal levels follow the USB specification, but since this signal test pattern does not follow the USB specification, these tests cannot be performed when the device is connected to a USB host. However, while the test is in progress, a conventional test device can be connected to the USB data line and the signal characteristics can be monitored. Circuit changes can be made to the digital system and the results can be easily measured. If the continuous stream characteristic of the USB state transition in the USB data line of the digital system is good, the special test mode according to the present invention is stopped and the USB transceiver resumes operation as a normal USB device. Digital systems include microprocessors, microcontrollers, digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic arrays (PLAs), and the like.

A technical feature of the present invention is that while testing a USB interface in a digital system, conventional test devices may be used to resolve errors and verify satisfaction with the operation of the circuit under test. This enables higher reliability in the circuit design of the digital system and the layout of the USB circuit prior to performing a complete USB IF for final verification of the USB circuit of the digital system. Another feature is that the test method is simple and inexpensive, and the test can also be performed by a relatively inexperienced operator. Another feature is that it does not require a special test device to verify the characteristics of the circuit and layout design of the sub-components driving the digital system or USB.

Further technical advantages and features will be described in detail through the disclosed embodiments for the accompanying drawings and description.

The following figures are attached to more clearly describe the present invention.

1 is a schematic block diagram of a digital system including a USB interface having a test mode function according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of the digital system of FIG. 1 in which the USB bus is tested by a standard test device.

These embodiments described in detail with reference to the drawings are presented for illustrative purposes only, and the present invention is capable of various modifications and variations. It is, therefore, to be understood that the invention is not limited to the specific forms thereof, and includes all modifications, equivalents, and substitutions without departing from the spirit and scope of the invention as set forth in the appended claims.

An embodiment of the present invention will be described with reference to the drawings. In the drawings like elements are denoted by the same reference numerals, and like elements will be denoted using the same reference numerals and separate subscripts.

1 shows a schematic block diagram of a digital system including a USB interface with a test mode function. The digital system 100 includes a digital processor 102 and a USB interface 104. The USB interface 104 has an eye pattern test enable control line 106, where the control interface 106 is at a first logic level, the USB interface to the USB data line 108 when the USB interface is at the first logic level. It will provide a USB signal that conforms to. If the control line 106 is at the second logic level, the USB interface 104 may generate a USB eye pattern test data signal waveform, such as a continuous stream of USB state transitions (as defined by the USB specification). To 108. The digital processor 102 may be a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic array (PLA), or the like.

FIG. 2 shows a schematic block diagram of the digital system of FIG. 1 where the USB bus is tested by a standard test device. The standard test device 200 is connected to the USB data line 108 of the digital system 100. The standard test device 200 may be an oscilloscope, logic analyzer, data analyzer, spectrum analyzer, time domain reflectometer (TDR), frequency counter, or the like, but is not limited to this example. The effects of various physical and / or electrical changes on the digital system 100 and / or USB data line 108, for example by USB data line routing, which can bring crosstalk from other circuits. Effects and standing wave reflections can be observed on data lines and the like.

Circuit changes may be made to the digital system 100, and the results are easily measured by the test apparatus 200. If the characteristics of the continuous stream of USB state transitions on the USB data line 108 are good, then the control line 106 returns to the first logic level for a normal USB signal conforming to the USB specification, and the USB transceiver is connected to a normal USB. Operation as a device will be initiated. Later, more complex and expensive USB IF tests can be performed according to the USB IF test specification.

The digital processor 102 and the USB interface 104 may be formed on a die of a semiconductor integrated circuit, and the semiconductor integrated circuit die may be packaged in various kinds of integrated circuit packages.

The present invention can achieve the above objects and advantages. Although the present invention has been described, described, and defined with reference to exemplary embodiments, such references do not imply limitations on the invention, and such limitations should not be inferred. The present invention may allow various modifications, changes, and forms or functional equivalents by those skilled in the art or those skilled in the art to which the present invention pertains. The foregoing is merely illustrative and does not confirm the scope of the present invention. Accordingly, the invention should be limited by the spirit and scope of the appended claims, which give the greatest scope of recognition in light of all equivalents.

Claims (17)

Digital processor; And A digital device comprising a universal serial bus (USB) test mode, comprising: a USB interface coupled to the digital processor and having an eye pattern test mode selected by a test enable input. The eye pattern test mode allows the USB interface to transmit a USB eye pattern test data signal to a USB data line connected to the USB interface, whereby the USB signal performance of the USB data line can be verified by a standard test device. A digital device that includes a universal serial bus test mode. The method of claim 1, And the USB interface is in a normal operation mode when the test enable input is at a first logic level, and the USB interface is in a test mode when the test enable input is at a second logic level. Digital device containing a bus test mode. The method of claim 1, The digital processor includes a universal serial bus test mode, characterized in that selected from the group consisting of a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), programmable logic array (PLA). Digital devices. The method of claim 1, And the USB eye pattern test data signal waveform is a USB state transition for low-speed USB operation. The method of claim 1, And the USB eye pattern test data signal waveform is a USB state transition for full-speed USB operation. The method of claim 1, And the USB eye pattern test data signal waveform is a USB state transition for high-speed USB operation. Digital processor; A USB interface coupled to the digital processor and having an eye pattern test mode for transmitting a USB eye pattern test data signal to a connected USB data line based on a selection by a test enable input; And USB eye pattern test data A standard test device coupled to the USB data line for verifying the performance of a signal waveform; a system for testing a digital system having a universal serial bus interface using a standard test device. The method of claim 7, wherein The standard test device comprises a digital system having a universal serial bus interface using a standard test device, wherein the standard test device is selected from the group consisting of oscilloscopes, logic analyzers, data analyzers, spectrum analyzers, time domain reflectometers and frequency counters. System for testing. The method of claim 7, wherein When the test enable input is the first logic level, the USB interface is in the normal operation mode, and when the test enable input is the second logic level, the standard test device, characterized in that the USB interface in the test mode A system for testing digital systems having a universal serial bus interface. The method of claim 7, wherein And the USB eye pattern test data signal waveform is a USB state transition for low-speed USB operation. 18. The system for testing a digital system having a universal serial bus interface using a standard test device. The method of claim 7, wherein And the USB eye pattern test data signal waveform is a USB state transition for full-speed USB operation. 18. The system for testing a digital system having a universal serial bus interface using a standard test device. The method of claim 7, wherein And the USB eye pattern test data signal waveform is a USB state transition for high-speed USB operation. 18. The system for testing a digital system having a universal serial bus interface using a standard test device. Providing a USB interface having an eye pattern test mode and a normal operation mode; Selecting the eye pattern test mode to cause a USB interface to transmit a USB eye pattern test data signal waveform to a USB data line connected to the USB interface; And Verifying the goodness of performance of the USB eye pattern test data signal waveform with a standard test device; and testing a digital system having a universal serial bus interface with a standard test device. The method of claim 13, Selecting the USB interface as a normal operating mode to use a USB IF test when testing the USB interface. The method of claim 13, And said USB eye pattern test data signal waveform is a USB state transition for low-speed USB operation. The method of claim 13, And said USB eye pattern test data signal waveform is a USB state transition for full-speed USB operation. The method of claim 13, And said USB eye pattern test data signal waveform is a USB state transition for high-speed USB operation.

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